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authorThierry Reding <treding@nvidia.com>2017-11-01 10:59:44 -0400
committerThierry Reding <treding@nvidia.com>2017-12-15 04:14:17 -0500
commit50f5b841ba06f4dfb739e7a5ab9b87e8173d5915 (patch)
tree5f1708c0c2a4eb8051b359c95ebe9f51763d0b95
parent102ca26a62e61e54abf41b3fc51038b4be80f197 (diff)
arm64: tegra: Use sor1_out clock
Use the sor1_out clock instead of sor1_src. This is a more accurate model of the hardware and allows for more complicated configurations such as HDMI 2.0. Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210.dtsi4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 9bdf19f2cca7..9c2402108772 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -266,11 +266,11 @@
266 reg = <0x0 0x54580000 0x0 0x00040000>; 266 reg = <0x0 0x54580000 0x0 0x00040000>;
267 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 267 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 268 clocks = <&tegra_car TEGRA210_CLK_SOR1>,
269 <&tegra_car TEGRA210_CLK_SOR1_SRC>, 269 <&tegra_car TEGRA210_CLK_SOR1_OUT>,
270 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 270 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
271 <&tegra_car TEGRA210_CLK_PLL_DP>, 271 <&tegra_car TEGRA210_CLK_PLL_DP>,
272 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 272 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
273 clock-names = "sor", "source", "parent", "dp", "safe"; 273 clock-names = "sor", "out", "parent", "dp", "safe";
274 resets = <&tegra_car 183>; 274 resets = <&tegra_car 183>;
275 reset-names = "sor"; 275 reset-names = "sor";
276 pinctrl-0 = <&state_dpaux1_aux>; 276 pinctrl-0 = <&state_dpaux1_aux>;