Merge tag 'v4.19-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into next/dt

mt2712 - add spi slave node

mt7622:
- add timer node
- add CCI node
- add PMU node
- add bluetooth node
- add SPI slave node
- fix reference board (rfb1) memory and sort node alphabetically
- add support for Bananapi-R64

* tag 'v4.19-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  arm64: dts: Add spi slave dts
  arm64: dts: mt7622: add bananapi BPI-R64 board
  arm64: dts: mt7622: fix ram size for rfb1
  arm64: dts: mt7622: add a bluetooth 5 device node
  arm64: dts: mt7622: add timer, CCI-400 and PMU nodes

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

5 files changed, 702 insertions, 98 deletions

diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 5b7fd6ad96e4..e8f952fb279b 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -5,4 +5,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 75cc0f7cc088..ee627a7c7b45 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -301,6 +301,17 @@
                 status = "disabled";
         };
 
+        spis1: spi@10013000 {
+                compatible = "mediatek,mt2712-spi-slave";
+                reg = <0 0x10013000 0 0x100>;
+                interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&infracfg CLK_INFRA_AO_SPI1>;
+                clock-names = "spi";
+                assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
+                assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
+                status = "disabled";
+        };
+
         apmixedsys: syscon@10209000 {
                 compatible = "mediatek,mt2712-apmixedsys", "syscon";
                 reg = <0 0x10209000 0 0x1000>;
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
new file mode 100644
index 000000000000..5d6005c9b097
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -0,0 +1,530 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+#include "mt7622.dtsi"
+#include "mt6380.dtsi"
+
+/ {
+        model = "Bananapi BPI-R64";
+        compatible = "bananapi,bpi-r64", "mediatek,mt7622";
+
+        chosen {
+                bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
+        };
+
+        cpus {
+                cpu@0 {
+                        proc-supply = <&mt6380_vcpu_reg>;
+                        sram-supply = <&mt6380_vm_reg>;
+                };
+
+                cpu@1 {
+                        proc-supply = <&mt6380_vcpu_reg>;
+                        sram-supply = <&mt6380_vm_reg>;
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                factory {
+                        label = "factory";
+                        linux,code = <BTN_0>;
+                        gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
+                };
+
+                wps {
+                        label = "wps";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                green {
+                        label = "bpi-r64:pio:green";
+                        gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                red {
+                        label = "bpi-r64:pio:red";
+                        gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+        };
+
+        memory {
+                reg = <0 0x40000000 0 0x40000000>;
+        };
+
+        reg_1p8v: regulator-1p8v {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-1.8V";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-always-on;
+        };
+
+        reg_3p3v: regulator-3p3v {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+
+        reg_5v: regulator-5v {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-5V";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+};
+
+&bch {
+        status = "disabled";
+};
+
+&btif {
+        status = "okay";
+};
+
+&cir {
+        pinctrl-names = "default";
+        pinctrl-0 = <&irrx_pins>;
+        status = "okay";
+};
+
+&eth {
+        pinctrl-names = "default";
+        pinctrl-0 = <&eth_pins>;
+        status = "okay";
+
+        gmac1: mac@1 {
+                compatible = "mediatek,eth-mac";
+                reg = <1>;
+                phy-handle = <&phy5>;
+        };
+
+        mdio-bus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                phy5: ethernet-phy@5 {
+                        reg = <5>;
+                        phy-mode = "sgmii";
+                };
+        };
+};
+
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
+        status = "okay";
+};
+
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c2_pins>;
+        status = "okay";
+};
+
+&mmc0 {
+        pinctrl-names = "default", "state_uhs";
+        pinctrl-0 = <&emmc_pins_default>;
+        pinctrl-1 = <&emmc_pins_uhs>;
+        status = "okay";
+        bus-width = <8>;
+        max-frequency = <50000000>;
+        cap-mmc-highspeed;
+        mmc-hs200-1_8v;
+        vmmc-supply = <&reg_3p3v>;
+        vqmmc-supply = <&reg_1p8v>;
+        assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
+        assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+        non-removable;
+};
+
+&mmc1 {
+        pinctrl-names = "default", "state_uhs";
+        pinctrl-0 = <&sd0_pins_default>;
+        pinctrl-1 = <&sd0_pins_uhs>;
+        status = "okay";
+        bus-width = <4>;
+        max-frequency = <50000000>;
+        cap-sd-highspeed;
+        r_smpl = <1>;
+        cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
+        vmmc-supply = <&reg_3p3v>;
+        vqmmc-supply = <&reg_3p3v>;
+        assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
+        assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+};
+
+&nandc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&parallel_nand_pins>;
+        status = "disabled";
+};
+
+&nor_flash {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi_nor_pins>;
+        status = "disabled";
+
+        flash@0 {
+                compatible = "jedec,spi-nor";
+                reg = <0>;
+        };
+};
+
+&pcie {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
+        status = "okay";
+
+        pcie@0,0 {
+                status = "okay";
+        };
+
+        pcie@1,0 {
+                status = "okay";
+        };
+};
+
+&pio {
+        /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
+         * SATA functions. i.e. output-high: PCIe, output-low: SATA
+         */
+        asm_sel {
+                gpio-hog;
+                gpios = <90 GPIO_ACTIVE_HIGH>;
+                output-high;
+        };
+
+        /* eMMC is shared pin with parallel NAND */
+        emmc_pins_default: emmc-pins-default {
+                mux {
+                        function = "emmc", "emmc_rst";
+                        groups = "emmc";
+                };
+
+                /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
+                 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
+                 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
+                 */
+                conf-cmd-dat {
+                        pins = "NDL0", "NDL1", "NDL2",
+                               "NDL3", "NDL4", "NDL5",
+                               "NDL6", "NDL7", "NRB";
+                        input-enable;
+                        bias-pull-up;
+                };
+
+                conf-clk {
+                        pins = "NCLE";
+                        bias-pull-down;
+                };
+        };
+
+        emmc_pins_uhs: emmc-pins-uhs {
+                mux {
+                        function = "emmc";
+                        groups = "emmc";
+                };
+
+                conf-cmd-dat {
+                        pins = "NDL0", "NDL1", "NDL2",
+                               "NDL3", "NDL4", "NDL5",
+                               "NDL6", "NDL7", "NRB";
+                        input-enable;
+                        drive-strength = <4>;
+                        bias-pull-up;
+                };
+
+                conf-clk {
+                        pins = "NCLE";
+                        drive-strength = <4>;
+                        bias-pull-down;
+                };
+        };
+
+        eth_pins: eth-pins {
+                mux {
+                        function = "eth";
+                        groups = "mdc_mdio", "rgmii_via_gmac2";
+                };
+        };
+
+        i2c1_pins: i2c1-pins {
+                mux {
+                        function = "i2c";
+                        groups =  "i2c1_0";
+                };
+        };
+
+        i2c2_pins: i2c2-pins {
+                mux {
+                        function = "i2c";
+                        groups =  "i2c2_0";
+                };
+        };
+
+        i2s1_pins: i2s1-pins {
+                mux {
+                        function = "i2s";
+                        groups =  "i2s_out_mclk_bclk_ws",
+                                  "i2s1_in_data",
+                                  "i2s1_out_data";
+                };
+
+                conf {
+                        pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
+                               "I2S_WS", "I2S_MCLK";
+                        drive-strength = <12>;
+                        bias-pull-down;
+                };
+        };
+
+        irrx_pins: irrx-pins {
+                mux {
+                        function = "ir";
+                        groups =  "ir_1_rx";
+                };
+        };
+
+        irtx_pins: irtx-pins {
+                mux {
+                        function = "ir";
+                        groups =  "ir_1_tx";
+                };
+        };
+
+        /* Parallel nand is shared pin with eMMC */
+        parallel_nand_pins: parallel-nand-pins {
+                mux {
+                        function = "flash";
+                        groups = "par_nand";
+                };
+        };
+
+        pcie0_pins: pcie0-pins {
+                mux {
+                        function = "pcie";
+                        groups = "pcie0_pad_perst",
+                                 "pcie0_1_waken",
+                                 "pcie0_1_clkreq";
+                };
+        };
+
+        pcie1_pins: pcie1-pins {
+                mux {
+                        function = "pcie";
+                        groups = "pcie1_pad_perst",
+                                 "pcie1_0_waken",
+                                 "pcie1_0_clkreq";
+                };
+        };
+
+        pmic_bus_pins: pmic-bus-pins {
+                mux {
+                        function = "pmic";
+                        groups = "pmic_bus";
+                };
+        };
+
+        pwm7_pins: pwm1-2-pins {
+                mux {
+                        function = "pwm";
+                        groups = "pwm_ch7_2";
+                };
+        };
+
+        wled_pins: wled-pins {
+                mux {
+                        function = "led";
+                        groups = "wled";
+                };
+        };
+
+        sd0_pins_default: sd0-pins-default {
+                mux {
+                        function = "sd";
+                        groups = "sd_0";
+                };
+
+                /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
+                 *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
+                 *  DAT2, DAT3, CMD, CLK for SD respectively.
+                 */
+                conf-cmd-data {
+                        pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
+                               "I2S2_IN","I2S4_OUT";
+                        input-enable;
+                        drive-strength = <8>;
+                        bias-pull-up;
+                };
+                conf-clk {
+                        pins = "I2S3_OUT";
+                        drive-strength = <12>;
+                        bias-pull-down;
+                };
+                conf-cd {
+                        pins = "TXD3";
+                        bias-pull-up;
+                };
+        };
+
+        sd0_pins_uhs: sd0-pins-uhs {
+                mux {
+                        function = "sd";
+                        groups = "sd_0";
+                };
+
+                conf-cmd-data {
+                        pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
+                               "I2S2_IN","I2S4_OUT";
+                        input-enable;
+                        bias-pull-up;
+                };
+
+                conf-clk {
+                        pins = "I2S3_OUT";
+                        bias-pull-down;
+                };
+        };
+
+        /* Serial NAND is shared pin with SPI-NOR */
+        serial_nand_pins: serial-nand-pins {
+                mux {
+                        function = "flash";
+                        groups = "snfi";
+                };
+        };
+
+        spic0_pins: spic0-pins {
+                mux {
+                        function = "spi";
+                        groups = "spic0_0";
+                };
+        };
+
+        spic1_pins: spic1-pins {
+                mux {
+                        function = "spi";
+                        groups = "spic1_0";
+                };
+        };
+
+        /* SPI-NOR is shared pin with serial NAND */
+        spi_nor_pins: spi-nor-pins {
+                mux {
+                        function = "flash";
+                        groups = "spi_nor";
+                };
+        };
+
+        /* serial NAND is shared pin with SPI-NOR */
+        serial_nand_pins: serial-nand-pins {
+                mux {
+                        function = "flash";
+                        groups = "snfi";
+                };
+        };
+
+        uart0_pins: uart0-pins {
+                mux {
+                        function = "uart";
+                        groups = "uart0_0_tx_rx" ;
+                };
+        };
+
+        uart2_pins: uart2-pins {
+                mux {
+                        function = "uart";
+                        groups = "uart2_1_tx_rx" ;
+                };
+        };
+
+        watchdog_pins: watchdog-pins {
+                mux {
+                        function = "watchdog";
+                        groups = "watchdog";
+                };
+        };
+};
+
+&pwm {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pwm7_pins>;
+        status = "okay";
+};
+
+&pwrap {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pmic_bus_pins>;
+
+        status = "okay";
+};
+
+&sata {
+        status = "disable";
+};
+
+&sata_phy {
+        status = "disable";
+};
+
+&spi0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spic0_pins>;
+        status = "okay";
+};
+
+&spi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spic1_pins>;
+        status = "okay";
+};
+
+&ssusb {
+        vusb33-supply = <&reg_3p3v>;
+        vbus-supply = <&reg_5v>;
+        status = "okay";
+};
+
+&u3phy {
+        status = "okay";
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins>;
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart2_pins>;
+        status = "okay";
+};
+
+&watchdog {
+        pinctrl-names = "default";
+        pinctrl-0 = <&watchdog_pins>;
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
index a747b7bf132d..dcad0869b84c 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -51,7 +51,7 @@
         };
 
         memory {
-                reg = <0 0x40000000 0 0x3F000000>;
+                reg = <0 0x40000000 0 0x20000000>;
         };
 
         reg_1p8v: regulator-1p8v {
@@ -81,6 +81,103 @@
         };
 };
 
+&bch {
+        status = "disabled";
+};
+
+&btif {
+        status = "okay";
+};
+
+&cir {
+        pinctrl-names = "default";
+        pinctrl-0 = <&irrx_pins>;
+        status = "okay";
+};
+
+&eth {
+        pinctrl-names = "default";
+        pinctrl-0 = <&eth_pins>;
+        status = "okay";
+
+        gmac1: mac@1 {
+                compatible = "mediatek,eth-mac";
+                reg = <1>;
+                phy-handle = <&phy5>;
+        };
+
+        mdio-bus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                phy5: ethernet-phy@5 {
+                        reg = <5>;
+                        phy-mode = "sgmii";
+                };
+        };
+};
+
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
+        status = "okay";
+};
+
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c2_pins>;
+        status = "okay";
+};
+
+&mmc0 {
+        pinctrl-names = "default", "state_uhs";
+        pinctrl-0 = <&emmc_pins_default>;
+        pinctrl-1 = <&emmc_pins_uhs>;
+        status = "okay";
+        bus-width = <8>;
+        max-frequency = <50000000>;
+        cap-mmc-highspeed;
+        mmc-hs200-1_8v;
+        vmmc-supply = <&reg_3p3v>;
+        vqmmc-supply = <&reg_1p8v>;
+        assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
+        assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+        non-removable;
+};
+
+&mmc1 {
+        pinctrl-names = "default", "state_uhs";
+        pinctrl-0 = <&sd0_pins_default>;
+        pinctrl-1 = <&sd0_pins_uhs>;
+        status = "okay";
+        bus-width = <4>;
+        max-frequency = <50000000>;
+        cap-sd-highspeed;
+        r_smpl = <1>;
+        cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
+        vmmc-supply = <&reg_3p3v>;
+        vqmmc-supply = <&reg_3p3v>;
+        assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
+        assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+};
+
+&nandc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&parallel_nand_pins>;
+        status = "disabled";
+};
+
+&nor_flash {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi_nor_pins>;
+        status = "disabled";
+
+        flash@0 {
+                compatible = "jedec,spi-nor";
+                reg = <0>;
+        };
+};
+
 &pcie {
         pinctrl-names = "default";
         pinctrl-0 = <&pcie0_pins>;
@@ -344,103 +441,6 @@
         };
 };
 
-&bch {
-        status = "disabled";
-};
-
-&btif {
-        status = "okay";
-};
-
-&cir {
-        pinctrl-names = "default";
-        pinctrl-0 = <&irrx_pins>;
-        status = "okay";
-};
-
-&eth {
-        pinctrl-names = "default";
-        pinctrl-0 = <&eth_pins>;
-        status = "okay";
-
-        gmac1: mac@1 {
-                compatible = "mediatek,eth-mac";
-                reg = <1>;
-                phy-handle = <&phy5>;
-        };
-
-        mdio-bus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                phy5: ethernet-phy@5 {
-                        reg = <5>;
-                        phy-mode = "sgmii";
-                };
-        };
-};
-
-&i2c1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c1_pins>;
-        status = "okay";
-};
-
-&i2c2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c2_pins>;
-        status = "okay";
-};
-
-&mmc0 {
-        pinctrl-names = "default", "state_uhs";
-        pinctrl-0 = <&emmc_pins_default>;
-        pinctrl-1 = <&emmc_pins_uhs>;
-        status = "okay";
-        bus-width = <8>;
-        max-frequency = <50000000>;
-        cap-mmc-highspeed;
-        mmc-hs200-1_8v;
-        vmmc-supply = <&reg_3p3v>;
-        vqmmc-supply = <&reg_1p8v>;
-        assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
-        assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
-        non-removable;
-};
-
-&mmc1 {
-        pinctrl-names = "default", "state_uhs";
-        pinctrl-0 = <&sd0_pins_default>;
-        pinctrl-1 = <&sd0_pins_uhs>;
-        status = "okay";
-        bus-width = <4>;
-        max-frequency = <50000000>;
-        cap-sd-highspeed;
-        r_smpl = <1>;
-        cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
-        vmmc-supply = <&reg_3p3v>;
-        vqmmc-supply = <&reg_3p3v>;
-        assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
-        assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
-};
-
-&nandc {
-        pinctrl-names = "default";
-        pinctrl-0 = <&parallel_nand_pins>;
-        status = "disabled";
-};
-
-&nor_flash {
-        pinctrl-names = "default";
-        pinctrl-0 = <&spi_nor_pins>;
-        status = "disabled";
-
-        flash@0 {
-                compatible = "jedec,spi-nor";
-                reg = <0>;
-        };
-};
-
 &pwm {
         pinctrl-names = "default";
         pinctrl-0 = <&pwm7_pins>;
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index de2c47bdbe64..fe0c875f1d95 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -79,6 +79,7 @@
                         #cooling-cells = <2>;
                         enable-method = "psci";
                         clock-frequency = <1300000000>;
+                        cci-control-port = <&cci_control2>;
                 };
 
                 cpu1: cpu@1 {
@@ -92,6 +93,7 @@
                         #cooling-cells = <2>;
                         enable-method = "psci";
                         clock-frequency = <1300000000>;
+                        cci-control-port = <&cci_control2>;
                 };
         };
 
@@ -113,6 +115,13 @@
                 method      = "smc";
         };
 
+        pmu {
+                compatible = "arm,cortex-a53-pmu";
+                interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
+                interrupt-affinity = <&cpu0>, <&cpu1>;
+        };
+
         reserved-memory {
                 #address-cells = <2>;
                 #size-cells = <2>;
@@ -218,6 +227,16 @@
                 #reset-cells = <1>;
         };
 
+        timer: timer@10004000 {
+                compatible = "mediatek,mt7622-timer",
+                             "mediatek,mt6577-timer";
+                reg = <0 0x10004000 0 0x80>;
+                interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&infracfg CLK_INFRA_APXGPT_PD>,
+                         <&topckgen CLK_TOP_RTC>;
+                clock-names = "system-clk", "rtc-clk";
+        };
+
         scpsys: scpsys@10006000 {
                 compatible = "mediatek,mt7622-scpsys",
                              "syscon";
@@ -325,6 +344,42 @@
                       <0 0x10360000 0 0x2000>;
         };
 
+        cci: cci@10390000 {
+                compatible = "arm,cci-400";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0 0x10390000 0 0x1000>;
+                ranges = <0 0 0x10390000 0x10000>;
+
+                cci_control0: slave-if@1000 {
+                        compatible = "arm,cci-400-ctrl-if";
+                        interface-type = "ace-lite";
+                        reg = <0x1000 0x1000>;
+                };
+
+                cci_control1: slave-if@4000 {
+                        compatible = "arm,cci-400-ctrl-if";
+                        interface-type = "ace";
+                        reg = <0x4000 0x1000>;
+                };
+
+                cci_control2: slave-if@5000 {
+                        compatible = "arm,cci-400-ctrl-if";
+                        interface-type = "ace";
+                        reg = <0x5000 0x1000>;
+                };
+
+                pmu@9000 {
+                        compatible = "arm,cci-400-pmu,r1";
+                        reg = <0x9000 0x5000>;
+                        interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+                };
+        };
+
         auxadc: adc@11001000 {
                 compatible = "mediatek,mt7622-auxadc";
                 reg = <0 0x11001000 0 0x1000>;
@@ -475,6 +530,13 @@
                 reg-shift = <2>;
                 reg-io-width = <4>;
                 status = "disabled";
+
+                bluetooth {
+                        compatible = "mediatek,mt7622-bluetooth";
+                        power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
+                        clocks = <&clk25m>;
+                        clock-names = "ref";
+                };
         };
 
         nandc: nfi@1100d000 {