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authorMaxime Ripard <maxime.ripard@free-electrons.com>2014-11-17 08:42:16 -0500
committerVinod Koul <vinod.koul@intel.com>2014-12-22 01:58:59 -0500
commit502c2ef26dba04128af260de0ca3e2940e57fc7a (patch)
treec23a6a17150f4954c3d53f97b0ffc84fdfe2d8bb
parentd80f381f321ab739e8a702ecc882560a5838b1fb (diff)
dmaengine: imx: Split device_control
Split the device_control callback of the Freescale IMX DMA driver to make use of the newly introduced callbacks, that will eventually be used to retrieve slave capabilities. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
-rw-r--r--drivers/dma/imx-dma.c103
1 files changed, 51 insertions, 52 deletions
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 10bbc0a675b0..02d1f73bd12b 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -669,69 +669,67 @@ out:
669 669
670} 670}
671 671
672static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 672static int imxdma_terminate_all(struct dma_chan *chan)
673 unsigned long arg)
674{ 673{
675 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 674 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
676 struct dma_slave_config *dmaengine_cfg = (void *)arg;
677 struct imxdma_engine *imxdma = imxdmac->imxdma; 675 struct imxdma_engine *imxdma = imxdmac->imxdma;
678 unsigned long flags; 676 unsigned long flags;
679 unsigned int mode = 0;
680
681 switch (cmd) {
682 case DMA_TERMINATE_ALL:
683 imxdma_disable_hw(imxdmac);
684 677
685 spin_lock_irqsave(&imxdma->lock, flags); 678 imxdma_disable_hw(imxdmac);
686 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
687 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
688 spin_unlock_irqrestore(&imxdma->lock, flags);
689 return 0;
690 case DMA_SLAVE_CONFIG:
691 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
692 imxdmac->per_address = dmaengine_cfg->src_addr;
693 imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
694 imxdmac->word_size = dmaengine_cfg->src_addr_width;
695 } else {
696 imxdmac->per_address = dmaengine_cfg->dst_addr;
697 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
698 imxdmac->word_size = dmaengine_cfg->dst_addr_width;
699 }
700
701 switch (imxdmac->word_size) {
702 case DMA_SLAVE_BUSWIDTH_1_BYTE:
703 mode = IMX_DMA_MEMSIZE_8;
704 break;
705 case DMA_SLAVE_BUSWIDTH_2_BYTES:
706 mode = IMX_DMA_MEMSIZE_16;
707 break;
708 default:
709 case DMA_SLAVE_BUSWIDTH_4_BYTES:
710 mode = IMX_DMA_MEMSIZE_32;
711 break;
712 }
713 679
714 imxdmac->hw_chaining = 0; 680 spin_lock_irqsave(&imxdma->lock, flags);
681 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
682 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
683 spin_unlock_irqrestore(&imxdma->lock, flags);
684 return 0;
685}
715 686
716 imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) | 687static int imxdma_config(struct dma_chan *chan,
717 ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) | 688 struct dma_slave_config *dmaengine_cfg)
718 CCR_REN; 689{
719 imxdmac->ccr_to_device = 690 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
720 (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) | 691 struct imxdma_engine *imxdma = imxdmac->imxdma;
721 ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN; 692 unsigned int mode = 0;
722 imx_dmav1_writel(imxdma, imxdmac->dma_request,
723 DMA_RSSR(imxdmac->channel));
724 693
725 /* Set burst length */ 694 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
726 imx_dmav1_writel(imxdma, imxdmac->watermark_level * 695 imxdmac->per_address = dmaengine_cfg->src_addr;
727 imxdmac->word_size, DMA_BLR(imxdmac->channel)); 696 imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
697 imxdmac->word_size = dmaengine_cfg->src_addr_width;
698 } else {
699 imxdmac->per_address = dmaengine_cfg->dst_addr;
700 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
701 imxdmac->word_size = dmaengine_cfg->dst_addr_width;
702 }
728 703
729 return 0; 704 switch (imxdmac->word_size) {
705 case DMA_SLAVE_BUSWIDTH_1_BYTE:
706 mode = IMX_DMA_MEMSIZE_8;
707 break;
708 case DMA_SLAVE_BUSWIDTH_2_BYTES:
709 mode = IMX_DMA_MEMSIZE_16;
710 break;
730 default: 711 default:
731 return -ENOSYS; 712 case DMA_SLAVE_BUSWIDTH_4_BYTES:
713 mode = IMX_DMA_MEMSIZE_32;
714 break;
732 } 715 }
733 716
734 return -EINVAL; 717 imxdmac->hw_chaining = 0;
718
719 imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
720 ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
721 CCR_REN;
722 imxdmac->ccr_to_device =
723 (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
724 ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
725 imx_dmav1_writel(imxdma, imxdmac->dma_request,
726 DMA_RSSR(imxdmac->channel));
727
728 /* Set burst length */
729 imx_dmav1_writel(imxdma, imxdmac->watermark_level *
730 imxdmac->word_size, DMA_BLR(imxdmac->channel));
731
732 return 0;
735} 733}
736 734
737static enum dma_status imxdma_tx_status(struct dma_chan *chan, 735static enum dma_status imxdma_tx_status(struct dma_chan *chan,
@@ -1184,7 +1182,8 @@ static int __init imxdma_probe(struct platform_device *pdev)
1184 imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic; 1182 imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
1185 imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy; 1183 imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
1186 imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved; 1184 imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved;
1187 imxdma->dma_device.device_control = imxdma_control; 1185 imxdma->dma_device.device_config = imxdma_config;
1186 imxdma->dma_device.device_terminate_all = imxdma_terminate_all;
1188 imxdma->dma_device.device_issue_pending = imxdma_issue_pending; 1187 imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
1189 1188
1190 platform_set_drvdata(pdev, imxdma); 1189 platform_set_drvdata(pdev, imxdma);