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authorAlexander Shiyan <shc_work@mail.ru>2016-06-25 00:59:22 -0400
committerMark Brown <broonie@kernel.org>2016-06-29 14:20:11 -0400
commit4f14f5c11db161ab89b02f7196496ca32ca5dbf8 (patch)
tree2bf2e784ff82e60ca115c63172ab556e0ec8dc93
parent1a695a905c18548062509178b98bc91e67510864 (diff)
ASoC: fsl_ssi: Fix number of words per frame for I2S-slave mode
The i.MX51 datasheet says: Chapter 56.1.2.4 I2S Mode ... When I2S modes are entered (I2S master (01) or I2S slave (10)), the following settings are recommended: ... - TX Frame Rate should be 2 i.e. (STCCR[12:8] = 1) - RX Frame Rate should be 2 i.e. (SRCCR[12:8] = 1) Chapter 56.3.3.12 SSI Transmit and Receive Clock Control Registers (STCCR & SRCCR) ... Bits 12-8 DC4-DC0 Frame Rate Divider Control. These bits are used to control the divide ratio for the programmable frame rate dividers. The divide ratio works on the word clock. In Normal mode, this ratio determines the word transfer rate. In Network mode, this ratio sets the number of words per frame. The divide ratio ranges from 1 to 32 in Normal mode and from 2 to 32 in Network mode. In Normal mode, a divide ratio of 1 (DC=00000) provides continuous periodic data word transfer. A bit-length frame sync must be used in this case. Function fsl_ssi_hw_params() setup Normal mode for MONO output, so with DC=0, SSI enters to continuous periodic data word transfer. To fix this, setup DC for any I2S mode. Patch has tested on custom board based on Digi CCMX-51 module (i.MX51). Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--sound/soc/fsl/fsl_ssi.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 632ecc0e3956..bedec4a32581 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -952,16 +952,16 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev,
952 ssi_private->i2s_mode = CCSR_SSI_SCR_NET; 952 ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
953 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 953 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
954 case SND_SOC_DAIFMT_I2S: 954 case SND_SOC_DAIFMT_I2S:
955 regmap_update_bits(regs, CCSR_SSI_STCCR,
956 CCSR_SSI_SxCCR_DC_MASK,
957 CCSR_SSI_SxCCR_DC(2));
958 regmap_update_bits(regs, CCSR_SSI_SRCCR,
959 CCSR_SSI_SxCCR_DC_MASK,
960 CCSR_SSI_SxCCR_DC(2));
955 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 961 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
956 case SND_SOC_DAIFMT_CBM_CFS: 962 case SND_SOC_DAIFMT_CBM_CFS:
957 case SND_SOC_DAIFMT_CBS_CFS: 963 case SND_SOC_DAIFMT_CBS_CFS:
958 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER; 964 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
959 regmap_update_bits(regs, CCSR_SSI_STCCR,
960 CCSR_SSI_SxCCR_DC_MASK,
961 CCSR_SSI_SxCCR_DC(2));
962 regmap_update_bits(regs, CCSR_SSI_SRCCR,
963 CCSR_SSI_SxCCR_DC_MASK,
964 CCSR_SSI_SxCCR_DC(2));
965 break; 965 break;
966 case SND_SOC_DAIFMT_CBM_CFM: 966 case SND_SOC_DAIFMT_CBM_CFM:
967 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE; 967 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;