drm/i915/skl: Do not disable cdclk PLL if csr firmware is present

While display engine entering into low power state no need to disable
cdclk pll as CSR firmware of dmc will take care. If pll is already
enabled firmware execution sequence will be blocked. This is one
of the criteria for dmc to work properly.

v1: Initial version.

v2: Based on review comment from Daniel added code commnent.

Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-bt: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 10 insertions, 4 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 184725770ae7..5d8645ee3294 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5709,10 +5709,16 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
                 DRM_ERROR("DBuf power disable timeout\n");
 
-        /* disable DPLL0 */
-        I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
-        if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
-                DRM_ERROR("Couldn't disable DPLL0\n");
+        /*
+         * DMC assumes ownership of LCPLL and will get confused if we touch it.
+         */
+        if (dev_priv->csr.dmc_payload) {
+                /* disable DPLL0 */
+                I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
+                                        ~LCPLL_PLL_ENABLE);
+                if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
+                        DRM_ERROR("Couldn't disable DPLL0\n");
+        }
 
         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
 }