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authorArnd Bergmann <arnd@arndb.de>2018-10-05 11:22:59 -0400
committerArnd Bergmann <arnd@arndb.de>2018-10-05 11:23:48 -0400
commit4e6a32e6eb30bde332ba67373c6ba5d68abf7e43 (patch)
tree8483f23c23781ef67ff64881ccb3f53c7e302ce1
parent38764692af2ce6e4d1620169d95b2f26149dbe48 (diff)
parent91f84690b502075550ca01d853d5c49b319921eb (diff)
Merge tag 'mvebu-dt64-4.20-2' of git://git.infradead.org/linux-mvebu into next/dt
mvebu dt64 for 4.20 (part 2) - Add System Error Interrupt support to Armada SoCs (7K/8K) - Add CPU idle support on Armada 8K * tag 'mvebu-dt64-4.20-2' of git://git.infradead.org/linux-mvebu: arm64: dts: clearfog-gt-8k: add PCIe slot description arm64: dts: marvell: add CP110 ICU SEI subnode arm64: dts: marvell: use new bindings for CP110 interrupts arm64: dts: marvell: add AP806 SEI subnode arm64: dts: marvell: add CPU Idle power state support on Armada 7K/8K arm64: dts: marvell: Add node labels for the cpus Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--arch/arm64/boot/dts/marvell/armada-372x.dtsi2
-rw-r--r--arch/arm64/boot/dts/marvell/armada-37xx.dtsi2
-rw-r--r--arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts7
-rw-r--r--arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi4
-rw-r--r--arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi12
-rw-r--r--arch/arm64/boot/dts/marvell/armada-ap806.dtsi36
-rw-r--r--arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi16
-rw-r--r--arch/arm64/boot/dts/marvell/armada-cp110.dtsi149
8 files changed, 145 insertions, 83 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-372x.dtsi b/arch/arm64/boot/dts/marvell/armada-372x.dtsi
index 97558a64e276..6800945a88ad 100644
--- a/arch/arm64/boot/dts/marvell/armada-372x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-372x.dtsi
@@ -16,7 +16,7 @@
16 compatible = "marvell,armada3720", "marvell,armada3710"; 16 compatible = "marvell,armada3720", "marvell,armada3710";
17 17
18 cpus { 18 cpus {
19 cpu@1 { 19 cpu1: cpu@1 {
20 device_type = "cpu"; 20 device_type = "cpu";
21 compatible = "arm,cortex-a53","arm,armv8"; 21 compatible = "arm,cortex-a53","arm,armv8";
22 reg = <0x1>; 22 reg = <0x1>;
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index f5eaec531aa8..4472bcd8f9fb 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -40,7 +40,7 @@
40 cpus { 40 cpus {
41 #address-cells = <1>; 41 #address-cells = <1>;
42 #size-cells = <0>; 42 #size-cells = <0>;
43 cpu@0 { 43 cpu0: cpu@0 {
44 device_type = "cpu"; 44 device_type = "cpu";
45 compatible = "arm,cortex-a53", "arm,armv8"; 45 compatible = "arm,cortex-a53", "arm,armv8";
46 reg = <0>; 46 reg = <0>;
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
index 1db44b0ec030..9473d40a292a 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
@@ -233,6 +233,13 @@
233 }; 233 };
234}; 234};
235 235
236&cp0_pcie0 {
237 pinctrl-names = "default";
238 pinctrl-0 = <&cp0_pci0_reset_pins>;
239 reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
240 status = "okay";
241};
242
236&cp0_gpio2 { 243&cp0_gpio2 {
237 sata_reset { 244 sata_reset {
238 gpio-hog; 245 gpio-hog;
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
index 64b5e61a698e..d3c0636558ff 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
@@ -15,13 +15,13 @@
15 #address-cells = <1>; 15 #address-cells = <1>;
16 #size-cells = <0>; 16 #size-cells = <0>;
17 17
18 cpu@0 { 18 cpu0: cpu@0 {
19 device_type = "cpu"; 19 device_type = "cpu";
20 compatible = "arm,cortex-a72", "arm,armv8"; 20 compatible = "arm,cortex-a72", "arm,armv8";
21 reg = <0x000>; 21 reg = <0x000>;
22 enable-method = "psci"; 22 enable-method = "psci";
23 }; 23 };
24 cpu@1 { 24 cpu1: cpu@1 {
25 device_type = "cpu"; 25 device_type = "cpu";
26 compatible = "arm,cortex-a72", "arm,armv8"; 26 compatible = "arm,cortex-a72", "arm,armv8";
27 reg = <0x001>; 27 reg = <0x001>;
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
index 746e792767f5..64632c873888 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
@@ -15,29 +15,33 @@
15 #address-cells = <1>; 15 #address-cells = <1>;
16 #size-cells = <0>; 16 #size-cells = <0>;
17 17
18 cpu@0 { 18 cpu0: cpu@0 {
19 device_type = "cpu"; 19 device_type = "cpu";
20 compatible = "arm,cortex-a72", "arm,armv8"; 20 compatible = "arm,cortex-a72", "arm,armv8";
21 reg = <0x000>; 21 reg = <0x000>;
22 enable-method = "psci"; 22 enable-method = "psci";
23 cpu-idle-states = <&CPU_SLEEP_0>;
23 }; 24 };
24 cpu@1 { 25 cpu1: cpu@1 {
25 device_type = "cpu"; 26 device_type = "cpu";
26 compatible = "arm,cortex-a72", "arm,armv8"; 27 compatible = "arm,cortex-a72", "arm,armv8";
27 reg = <0x001>; 28 reg = <0x001>;
28 enable-method = "psci"; 29 enable-method = "psci";
30 cpu-idle-states = <&CPU_SLEEP_0>;
29 }; 31 };
30 cpu@100 { 32 cpu2: cpu@100 {
31 device_type = "cpu"; 33 device_type = "cpu";
32 compatible = "arm,cortex-a72", "arm,armv8"; 34 compatible = "arm,cortex-a72", "arm,armv8";
33 reg = <0x100>; 35 reg = <0x100>;
34 enable-method = "psci"; 36 enable-method = "psci";
37 cpu-idle-states = <&CPU_SLEEP_0>;
35 }; 38 };
36 cpu@101 { 39 cpu3: cpu@101 {
37 device_type = "cpu"; 40 device_type = "cpu";
38 compatible = "arm,cortex-a72", "arm,armv8"; 41 compatible = "arm,cortex-a72", "arm,armv8";
39 reg = <0x101>; 42 reg = <0x101>;
40 enable-method = "psci"; 43 enable-method = "psci";
44 cpu-idle-states = <&CPU_SLEEP_0>;
41 }; 45 };
42 }; 46 };
43}; 47};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 9a5abad72b66..073610ac0a53 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -28,6 +28,33 @@
28 method = "smc"; 28 method = "smc";
29 }; 29 };
30 30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 idle_states {
36 entry_method = "arm,pcsi";
37
38 CPU_SLEEP_0: cpu-sleep-0 {
39 compatible = "arm,idle-state";
40 local-timer-stop;
41 arm,psci-suspend-param = <0x0010000>;
42 entry-latency-us = <80>;
43 exit-latency-us = <160>;
44 min-residency-us = <320>;
45 };
46
47 CLUSTER_SLEEP_0: cluster-sleep-0 {
48 compatible = "arm,idle-state";
49 local-timer-stop;
50 arm,psci-suspend-param = <0x1010000>;
51 entry-latency-us = <500>;
52 exit-latency-us = <1000>;
53 min-residency-us = <2500>;
54 };
55 };
56 };
57
31 ap806 { 58 ap806 {
32 #address-cells = <2>; 59 #address-cells = <2>;
33 #size-cells = <2>; 60 #size-cells = <2>;
@@ -125,6 +152,15 @@
125 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 152 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
126 }; 153 };
127 154
155 sei: interrupt-controller@3f0200 {
156 compatible = "marvell,ap806-sei";
157 reg = <0x3f0200 0x40>;
158 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
159 #interrupt-cells = <1>;
160 interrupt-controller;
161 msi-controller;
162 };
163
128 xor@400000 { 164 xor@400000 {
129 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 165 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
130 reg = <0x400000 0x1000>, 166 reg = <0x400000 0x1000>,
diff --git a/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi b/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi
index 7d00ae78fc79..b788cb63caf2 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi
@@ -13,49 +13,49 @@
13 #size-cells = <0>; 13 #size-cells = <0>;
14 compatible = "marvell,armada-ap810-octa"; 14 compatible = "marvell,armada-ap810-octa";
15 15
16 cpu@0 { 16 cpu0: cpu@0 {
17 device_type = "cpu"; 17 device_type = "cpu";
18 compatible = "arm,cortex-a72", "arm,armv8"; 18 compatible = "arm,cortex-a72", "arm,armv8";
19 reg = <0x000>; 19 reg = <0x000>;
20 enable-method = "psci"; 20 enable-method = "psci";
21 }; 21 };
22 cpu@1 { 22 cpu1: cpu@1 {
23 device_type = "cpu"; 23 device_type = "cpu";
24 compatible = "arm,cortex-a72", "arm,armv8"; 24 compatible = "arm,cortex-a72", "arm,armv8";
25 reg = <0x001>; 25 reg = <0x001>;
26 enable-method = "psci"; 26 enable-method = "psci";
27 }; 27 };
28 cpu@100 { 28 cpu2: cpu@100 {
29 device_type = "cpu"; 29 device_type = "cpu";
30 compatible = "arm,cortex-a72", "arm,armv8"; 30 compatible = "arm,cortex-a72", "arm,armv8";
31 reg = <0x100>; 31 reg = <0x100>;
32 enable-method = "psci"; 32 enable-method = "psci";
33 }; 33 };
34 cpu@101 { 34 cpu3: cpu@101 {
35 device_type = "cpu"; 35 device_type = "cpu";
36 compatible = "arm,cortex-a72", "arm,armv8"; 36 compatible = "arm,cortex-a72", "arm,armv8";
37 reg = <0x101>; 37 reg = <0x101>;
38 enable-method = "psci"; 38 enable-method = "psci";
39 }; 39 };
40 cpu@200 { 40 cpu4: cpu@200 {
41 device_type = "cpu"; 41 device_type = "cpu";
42 compatible = "arm,cortex-a72", "arm,armv8"; 42 compatible = "arm,cortex-a72", "arm,armv8";
43 reg = <0x200>; 43 reg = <0x200>;
44 enable-method = "psci"; 44 enable-method = "psci";
45 }; 45 };
46 cpu@201 { 46 cpu5: cpu@201 {
47 device_type = "cpu"; 47 device_type = "cpu";
48 compatible = "arm,cortex-a72", "arm,armv8"; 48 compatible = "arm,cortex-a72", "arm,armv8";
49 reg = <0x201>; 49 reg = <0x201>;
50 enable-method = "psci"; 50 enable-method = "psci";
51 }; 51 };
52 cpu@300 { 52 cpu6: cpu@300 {
53 device_type = "cpu"; 53 device_type = "cpu";
54 compatible = "arm,cortex-a72", "arm,armv8"; 54 compatible = "arm,cortex-a72", "arm,armv8";
55 reg = <0x300>; 55 reg = <0x300>;
56 enable-method = "psci"; 56 enable-method = "psci";
57 }; 57 };
58 cpu@301 { 58 cpu7: cpu@301 {
59 device_type = "cpu"; 59 device_type = "cpu";
60 compatible = "arm,cortex-a72", "arm,armv8"; 60 compatible = "arm,cortex-a72", "arm,armv8";
61 reg = <0x301>; 61 reg = <0x301>;
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index f3a630efcf3a..b9d9f31e3ba1 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -43,7 +43,7 @@
43 #address-cells = <2>; 43 #address-cells = <2>;
44 #size-cells = <2>; 44 #size-cells = <2>;
45 compatible = "simple-bus"; 45 compatible = "simple-bus";
46 interrupt-parent = <&CP110_LABEL(icu)>; 46 interrupt-parent = <&CP110_LABEL(icu_nsr)>;
47 ranges; 47 ranges;
48 48
49 config-space@CP110_BASE { 49 config-space@CP110_BASE {
@@ -65,16 +65,16 @@
65 dma-coherent; 65 dma-coherent;
66 66
67 CP110_LABEL(eth0): eth0 { 67 CP110_LABEL(eth0): eth0 {
68 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>, 68 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
69 <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>, 69 <43 IRQ_TYPE_LEVEL_HIGH>,
70 <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>, 70 <47 IRQ_TYPE_LEVEL_HIGH>,
71 <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>, 71 <51 IRQ_TYPE_LEVEL_HIGH>,
72 <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>, 72 <55 IRQ_TYPE_LEVEL_HIGH>,
73 <ICU_GRP_NSR 59 IRQ_TYPE_LEVEL_HIGH>, 73 <59 IRQ_TYPE_LEVEL_HIGH>,
74 <ICU_GRP_NSR 63 IRQ_TYPE_LEVEL_HIGH>, 74 <63 IRQ_TYPE_LEVEL_HIGH>,
75 <ICU_GRP_NSR 67 IRQ_TYPE_LEVEL_HIGH>, 75 <67 IRQ_TYPE_LEVEL_HIGH>,
76 <ICU_GRP_NSR 71 IRQ_TYPE_LEVEL_HIGH>, 76 <71 IRQ_TYPE_LEVEL_HIGH>,
77 <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>; 77 <129 IRQ_TYPE_LEVEL_HIGH>;
78 interrupt-names = "hif0", "hif1", "hif2", 78 interrupt-names = "hif0", "hif1", "hif2",
79 "hif3", "hif4", "hif5", "hif6", "hif7", 79 "hif3", "hif4", "hif5", "hif6", "hif7",
80 "hif8", "link"; 80 "hif8", "link";
@@ -84,16 +84,16 @@
84 }; 84 };
85 85
86 CP110_LABEL(eth1): eth1 { 86 CP110_LABEL(eth1): eth1 {
87 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>, 87 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
88 <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>, 88 <44 IRQ_TYPE_LEVEL_HIGH>,
89 <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>, 89 <48 IRQ_TYPE_LEVEL_HIGH>,
90 <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>, 90 <52 IRQ_TYPE_LEVEL_HIGH>,
91 <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>, 91 <56 IRQ_TYPE_LEVEL_HIGH>,
92 <ICU_GRP_NSR 60 IRQ_TYPE_LEVEL_HIGH>, 92 <60 IRQ_TYPE_LEVEL_HIGH>,
93 <ICU_GRP_NSR 64 IRQ_TYPE_LEVEL_HIGH>, 93 <64 IRQ_TYPE_LEVEL_HIGH>,
94 <ICU_GRP_NSR 68 IRQ_TYPE_LEVEL_HIGH>, 94 <68 IRQ_TYPE_LEVEL_HIGH>,
95 <ICU_GRP_NSR 72 IRQ_TYPE_LEVEL_HIGH>, 95 <72 IRQ_TYPE_LEVEL_HIGH>,
96 <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>; 96 <128 IRQ_TYPE_LEVEL_HIGH>;
97 interrupt-names = "hif0", "hif1", "hif2", 97 interrupt-names = "hif0", "hif1", "hif2",
98 "hif3", "hif4", "hif5", "hif6", "hif7", 98 "hif3", "hif4", "hif5", "hif6", "hif7",
99 "hif8", "link"; 99 "hif8", "link";
@@ -103,16 +103,16 @@
103 }; 103 };
104 104
105 CP110_LABEL(eth2): eth2 { 105 CP110_LABEL(eth2): eth2 {
106 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>, 106 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
107 <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>, 107 <45 IRQ_TYPE_LEVEL_HIGH>,
108 <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>, 108 <49 IRQ_TYPE_LEVEL_HIGH>,
109 <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>, 109 <53 IRQ_TYPE_LEVEL_HIGH>,
110 <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>, 110 <57 IRQ_TYPE_LEVEL_HIGH>,
111 <ICU_GRP_NSR 61 IRQ_TYPE_LEVEL_HIGH>, 111 <61 IRQ_TYPE_LEVEL_HIGH>,
112 <ICU_GRP_NSR 65 IRQ_TYPE_LEVEL_HIGH>, 112 <65 IRQ_TYPE_LEVEL_HIGH>,
113 <ICU_GRP_NSR 69 IRQ_TYPE_LEVEL_HIGH>, 113 <69 IRQ_TYPE_LEVEL_HIGH>,
114 <ICU_GRP_NSR 73 IRQ_TYPE_LEVEL_HIGH>, 114 <73 IRQ_TYPE_LEVEL_HIGH>,
115 <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>; 115 <127 IRQ_TYPE_LEVEL_HIGH>;
116 interrupt-names = "hif0", "hif1", "hif2", 116 interrupt-names = "hif0", "hif1", "hif2",
117 "hif3", "hif4", "hif5", "hif6", "hif7", 117 "hif3", "hif4", "hif5", "hif6", "hif7",
118 "hif8", "link"; 118 "hif8", "link";
@@ -183,16 +183,31 @@
183 CP110_LABEL(icu): interrupt-controller@1e0000 { 183 CP110_LABEL(icu): interrupt-controller@1e0000 {
184 compatible = "marvell,cp110-icu"; 184 compatible = "marvell,cp110-icu";
185 reg = <0x1e0000 0x440>; 185 reg = <0x1e0000 0x440>;
186 #interrupt-cells = <3>; 186 #address-cells = <1>;
187 interrupt-controller; 187 #size-cells = <1>;
188 msi-parent = <&gicp>; 188
189 CP110_LABEL(icu_nsr): interrupt-controller@10 {
190 compatible = "marvell,cp110-icu-nsr";
191 reg = <0x10 0x20>;
192 #interrupt-cells = <2>;
193 interrupt-controller;
194 msi-parent = <&gicp>;
195 };
196
197 CP110_LABEL(icu_sei): interrupt-controller@50 {
198 compatible = "marvell,cp110-icu-sei";
199 reg = <0x50 0x10>;
200 #interrupt-cells = <2>;
201 interrupt-controller;
202 msi-parent = <&sei>;
203 };
189 }; 204 };
190 205
191 CP110_LABEL(rtc): rtc@284000 { 206 CP110_LABEL(rtc): rtc@284000 {
192 compatible = "marvell,armada-8k-rtc"; 207 compatible = "marvell,armada-8k-rtc";
193 reg = <0x284000 0x20>, <0x284080 0x24>; 208 reg = <0x284000 0x20>, <0x284080 0x24>;
194 reg-names = "rtc", "rtc-soc"; 209 reg-names = "rtc", "rtc-soc";
195 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>; 210 interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
196 }; 211 };
197 212
198 CP110_LABEL(syscon0): system-controller@440000 { 213 CP110_LABEL(syscon0): system-controller@440000 {
@@ -212,10 +227,10 @@
212 #gpio-cells = <2>; 227 #gpio-cells = <2>;
213 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>; 228 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
214 interrupt-controller; 229 interrupt-controller;
215 interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>, 230 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
216 <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>, 231 <85 IRQ_TYPE_LEVEL_HIGH>,
217 <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>, 232 <84 IRQ_TYPE_LEVEL_HIGH>,
218 <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>; 233 <83 IRQ_TYPE_LEVEL_HIGH>;
219 status = "disabled"; 234 status = "disabled";
220 }; 235 };
221 236
@@ -227,10 +242,10 @@
227 #gpio-cells = <2>; 242 #gpio-cells = <2>;
228 gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>; 243 gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
229 interrupt-controller; 244 interrupt-controller;
230 interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>, 245 interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
231 <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>, 246 <81 IRQ_TYPE_LEVEL_HIGH>,
232 <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>, 247 <80 IRQ_TYPE_LEVEL_HIGH>,
233 <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>; 248 <79 IRQ_TYPE_LEVEL_HIGH>;
234 status = "disabled"; 249 status = "disabled";
235 }; 250 };
236 }; 251 };
@@ -253,7 +268,7 @@
253 "generic-xhci"; 268 "generic-xhci";
254 reg = <0x500000 0x4000>; 269 reg = <0x500000 0x4000>;
255 dma-coherent; 270 dma-coherent;
256 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>; 271 interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
257 clock-names = "core", "reg"; 272 clock-names = "core", "reg";
258 clocks = <&CP110_LABEL(clk) 1 22>, 273 clocks = <&CP110_LABEL(clk) 1 22>,
259 <&CP110_LABEL(clk) 1 16>; 274 <&CP110_LABEL(clk) 1 16>;
@@ -265,7 +280,7 @@
265 "generic-xhci"; 280 "generic-xhci";
266 reg = <0x510000 0x4000>; 281 reg = <0x510000 0x4000>;
267 dma-coherent; 282 dma-coherent;
268 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>; 283 interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
269 clock-names = "core", "reg"; 284 clock-names = "core", "reg";
270 clocks = <&CP110_LABEL(clk) 1 23>, 285 clocks = <&CP110_LABEL(clk) 1 23>,
271 <&CP110_LABEL(clk) 1 16>; 286 <&CP110_LABEL(clk) 1 16>;
@@ -277,7 +292,7 @@
277 "generic-ahci"; 292 "generic-ahci";
278 reg = <0x540000 0x30000>; 293 reg = <0x540000 0x30000>;
279 dma-coherent; 294 dma-coherent;
280 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>; 295 interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&CP110_LABEL(clk) 1 15>, 296 clocks = <&CP110_LABEL(clk) 1 15>,
282 <&CP110_LABEL(clk) 1 16>; 297 <&CP110_LABEL(clk) 1 16>;
283 status = "disabled"; 298 status = "disabled";
@@ -330,7 +345,7 @@
330 reg = <0x701000 0x20>; 345 reg = <0x701000 0x20>;
331 #address-cells = <1>; 346 #address-cells = <1>;
332 #size-cells = <0>; 347 #size-cells = <0>;
333 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>; 348 interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
334 clock-names = "core", "reg"; 349 clock-names = "core", "reg";
335 clocks = <&CP110_LABEL(clk) 1 21>, 350 clocks = <&CP110_LABEL(clk) 1 21>,
336 <&CP110_LABEL(clk) 1 17>; 351 <&CP110_LABEL(clk) 1 17>;
@@ -342,7 +357,7 @@
342 reg = <0x701100 0x20>; 357 reg = <0x701100 0x20>;
343 #address-cells = <1>; 358 #address-cells = <1>;
344 #size-cells = <0>; 359 #size-cells = <0>;
345 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>; 360 interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
346 clock-names = "core", "reg"; 361 clock-names = "core", "reg";
347 clocks = <&CP110_LABEL(clk) 1 21>, 362 clocks = <&CP110_LABEL(clk) 1 21>,
348 <&CP110_LABEL(clk) 1 17>; 363 <&CP110_LABEL(clk) 1 17>;
@@ -353,7 +368,7 @@
353 compatible = "snps,dw-apb-uart"; 368 compatible = "snps,dw-apb-uart";
354 reg = <0x702000 0x100>; 369 reg = <0x702000 0x100>;
355 reg-shift = <2>; 370 reg-shift = <2>;
356 interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>; 371 interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
357 reg-io-width = <1>; 372 reg-io-width = <1>;
358 clock-names = "baudclk", "apb_pclk"; 373 clock-names = "baudclk", "apb_pclk";
359 clocks = <&CP110_LABEL(clk) 1 21>, 374 clocks = <&CP110_LABEL(clk) 1 21>,
@@ -365,7 +380,7 @@
365 compatible = "snps,dw-apb-uart"; 380 compatible = "snps,dw-apb-uart";
366 reg = <0x702100 0x100>; 381 reg = <0x702100 0x100>;
367 reg-shift = <2>; 382 reg-shift = <2>;
368 interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>; 383 interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
369 reg-io-width = <1>; 384 reg-io-width = <1>;
370 clock-names = "baudclk", "apb_pclk"; 385 clock-names = "baudclk", "apb_pclk";
371 clocks = <&CP110_LABEL(clk) 1 21>, 386 clocks = <&CP110_LABEL(clk) 1 21>,
@@ -377,7 +392,7 @@
377 compatible = "snps,dw-apb-uart"; 392 compatible = "snps,dw-apb-uart";
378 reg = <0x702200 0x100>; 393 reg = <0x702200 0x100>;
379 reg-shift = <2>; 394 reg-shift = <2>;
380 interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>; 395 interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
381 reg-io-width = <1>; 396 reg-io-width = <1>;
382 clock-names = "baudclk", "apb_pclk"; 397 clock-names = "baudclk", "apb_pclk";
383 clocks = <&CP110_LABEL(clk) 1 21>, 398 clocks = <&CP110_LABEL(clk) 1 21>,
@@ -389,7 +404,7 @@
389 compatible = "snps,dw-apb-uart"; 404 compatible = "snps,dw-apb-uart";
390 reg = <0x702300 0x100>; 405 reg = <0x702300 0x100>;
391 reg-shift = <2>; 406 reg-shift = <2>;
392 interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>; 407 interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
393 reg-io-width = <1>; 408 reg-io-width = <1>;
394 clock-names = "baudclk", "apb_pclk"; 409 clock-names = "baudclk", "apb_pclk";
395 clocks = <&CP110_LABEL(clk) 1 21>, 410 clocks = <&CP110_LABEL(clk) 1 21>,
@@ -408,7 +423,7 @@
408 reg = <0x720000 0x54>; 423 reg = <0x720000 0x54>;
409 #address-cells = <1>; 424 #address-cells = <1>;
410 #size-cells = <0>; 425 #size-cells = <0>;
411 interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>; 426 interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
412 clock-names = "core", "reg"; 427 clock-names = "core", "reg";
413 clocks = <&CP110_LABEL(clk) 1 2>, 428 clocks = <&CP110_LABEL(clk) 1 2>,
414 <&CP110_LABEL(clk) 1 17>; 429 <&CP110_LABEL(clk) 1 17>;
@@ -420,7 +435,7 @@
420 compatible = "marvell,armada-8k-rng", 435 compatible = "marvell,armada-8k-rng",
421 "inside-secure,safexcel-eip76"; 436 "inside-secure,safexcel-eip76";
422 reg = <0x760000 0x7d>; 437 reg = <0x760000 0x7d>;
423 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>; 438 interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
424 clock-names = "core", "reg"; 439 clock-names = "core", "reg";
425 clocks = <&CP110_LABEL(clk) 1 25>, 440 clocks = <&CP110_LABEL(clk) 1 25>,
426 <&CP110_LABEL(clk) 1 17>; 441 <&CP110_LABEL(clk) 1 17>;
@@ -430,7 +445,7 @@
430 CP110_LABEL(sdhci0): sdhci@780000 { 445 CP110_LABEL(sdhci0): sdhci@780000 {
431 compatible = "marvell,armada-cp110-sdhci"; 446 compatible = "marvell,armada-cp110-sdhci";
432 reg = <0x780000 0x300>; 447 reg = <0x780000 0x300>;
433 interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>; 448 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
434 clock-names = "core", "axi"; 449 clock-names = "core", "axi";
435 clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>; 450 clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>;
436 dma-coherent; 451 dma-coherent;
@@ -440,12 +455,12 @@
440 CP110_LABEL(crypto): crypto@800000 { 455 CP110_LABEL(crypto): crypto@800000 {
441 compatible = "inside-secure,safexcel-eip197b"; 456 compatible = "inside-secure,safexcel-eip197b";
442 reg = <0x800000 0x200000>; 457 reg = <0x800000 0x200000>;
443 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>, 458 interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
444 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>, 459 <88 IRQ_TYPE_LEVEL_HIGH>,
445 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>, 460 <89 IRQ_TYPE_LEVEL_HIGH>,
446 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>, 461 <90 IRQ_TYPE_LEVEL_HIGH>,
447 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>, 462 <91 IRQ_TYPE_LEVEL_HIGH>,
448 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>; 463 <92 IRQ_TYPE_LEVEL_HIGH>;
449 interrupt-names = "mem", "ring0", "ring1", 464 interrupt-names = "mem", "ring0", "ring1",
450 "ring2", "ring3", "eip"; 465 "ring2", "ring3", "eip";
451 clock-names = "core", "reg"; 466 clock-names = "core", "reg";
@@ -474,8 +489,8 @@
474 /* non-prefetchable memory */ 489 /* non-prefetchable memory */
475 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>; 490 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
476 interrupt-map-mask = <0 0 0 0>; 491 interrupt-map-mask = <0 0 0 0>;
477 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 492 interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
478 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 493 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
479 num-lanes = <1>; 494 num-lanes = <1>;
480 clock-names = "core", "reg"; 495 clock-names = "core", "reg";
481 clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>; 496 clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
@@ -501,8 +516,8 @@
501 /* non-prefetchable memory */ 516 /* non-prefetchable memory */
502 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>; 517 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
503 interrupt-map-mask = <0 0 0 0>; 518 interrupt-map-mask = <0 0 0 0>;
504 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 519 interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
505 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 520 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
506 521
507 num-lanes = <1>; 522 num-lanes = <1>;
508 clock-names = "core", "reg"; 523 clock-names = "core", "reg";
@@ -529,8 +544,8 @@
529 /* non-prefetchable memory */ 544 /* non-prefetchable memory */
530 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>; 545 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
531 interrupt-map-mask = <0 0 0 0>; 546 interrupt-map-mask = <0 0 0 0>;
532 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 547 interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
533 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 548 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
534 549
535 num-lanes = <1>; 550 num-lanes = <1>;
536 clock-names = "core", "reg"; 551 clock-names = "core", "reg";
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 19:04:47 -0400