diff options
author | Dave Airlie <airlied@redhat.com> | 2013-08-23 04:52:37 -0400 |
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committer | Dave Airlie <airlied@redhat.com> | 2013-08-23 04:52:37 -0400 |
commit | 4dd17ee95742f3e9fd55d07463981711a637bd20 (patch) | |
tree | 38e7748d84ec850cf66e9cf1f42fa9905e13ca8c | |
parent | 6f1e120438144a47463b80c3e113334a6bd0e77c (diff) | |
parent | 884020bf3d2a3787a1cc6df902e98e0eec60330b (diff) |
Merge tag 'drm-intel-fixes-2013-08-23' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixes
Just one patch that soaked for quite a bit to fix a resume issue,
resulting in gpu hangs (or worse) due to tlb containing garbage.
* tag 'drm-intel-fixes-2013-08-23' of git://people.freedesktop.org/~danvet/drm-intel:
drm/i915: Invalidate TLBs for the rings after a reset
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 12 |
2 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6f514297c483..53cddd985406 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -752,6 +752,8 @@ | |||
752 | will not assert AGPBUSY# and will only | 752 | will not assert AGPBUSY# and will only |
753 | be delivered when out of C3. */ | 753 | be delivered when out of C3. */ |
754 | #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ | 754 | #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ |
755 | #define INSTPM_TLB_INVALIDATE (1<<9) | ||
756 | #define INSTPM_SYNC_FLUSH (1<<5) | ||
755 | #define ACTHD 0x020c8 | 757 | #define ACTHD 0x020c8 |
756 | #define FW_BLC 0x020d8 | 758 | #define FW_BLC 0x020d8 |
757 | #define FW_BLC2 0x020dc | 759 | #define FW_BLC2 0x020dc |
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 664118d8c1d6..079ef0129e74 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c | |||
@@ -968,6 +968,18 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring) | |||
968 | 968 | ||
969 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); | 969 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
970 | POSTING_READ(mmio); | 970 | POSTING_READ(mmio); |
971 | |||
972 | /* Flush the TLB for this page */ | ||
973 | if (INTEL_INFO(dev)->gen >= 6) { | ||
974 | u32 reg = RING_INSTPM(ring->mmio_base); | ||
975 | I915_WRITE(reg, | ||
976 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | ||
977 | INSTPM_SYNC_FLUSH)); | ||
978 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, | ||
979 | 1000)) | ||
980 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | ||
981 | ring->name); | ||
982 | } | ||
971 | } | 983 | } |
972 | 984 | ||
973 | static int | 985 | static int |