drm/i915: Move WaProgramL3SqcReg1Default:bdw to init_clock_gating()

GEN8_L3SQCREG1 isn't saved in the context (verified by going through
a context dump), and so we shouldn't be using the ring w/a code to
initialize it. Also Bspec explicitly talks about MMIO and writing it
with the CPU.

Additionally there's another w/a WaTempDisableDOPClkGating:bdw which
tells us to disable DOP clock gating around the GEN8_L3SQCREG1 write
to make sure everyone notices the change. So let's do that as well.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2 files changed, 10 insertions, 3 deletions

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cfc748086088..85ba52bacfea 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6174,6 +6174,7 @@ static void broadwell_init_clock_gating(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         enum pipe pipe;
+        uint32_t misccpctl;
 
         ilk_init_lp_watermarks(dev);
 
@@ -6204,6 +6205,15 @@ static void broadwell_init_clock_gating(struct drm_device *dev)
         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 
+        /*
+         * WaProgramL3SqcReg1Default:bdw
+         * WaTempDisableDOPClkGating:bdw
+         */
+        misccpctl = I915_READ(GEN7_MISCCPCTL);
+        I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
+        I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
+        I915_WRITE(GEN7_MISCCPCTL, misccpctl);
+
         lpt_init_clock_gating(dev);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 052265ae8de1..d934f857394d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -853,9 +853,6 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
                             GEN6_WIZ_HASHING_MASK,
                             GEN6_WIZ_HASHING_16x4);
 
-        /* WaProgramL3SqcReg1Default:bdw */
-        WA_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
-
         return 0;
 }