drm/amd/display: Use the maximum link setting which EDP reported.

Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 6 insertions, 0 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 00528b214a9f..61e8c3e02d16 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1470,6 +1470,12 @@ void decide_link_settings(struct dc_stream_state *stream,
                 return;
         }
 
+        /* EDP use the link cap setting */
+        if (stream->sink->sink_signal == SIGNAL_TYPE_EDP) {
+                *link_setting = link->verified_link_cap;
+                return;
+        }
+
         /* search for the minimum link setting that:
          * 1. is supported according to the link training result
          * 2. could support the b/w requested by the timing