diff options
author | Marcin Nowakowski <marcin.nowakowski@imgtec.com> | 2016-08-17 06:22:33 -0400 |
---|---|---|
committer | Daniel Lezcano <daniel.lezcano@linaro.org> | 2016-08-26 09:55:59 -0400 |
commit | 4d0e701659aa869a445823149e172e23faa6edac (patch) | |
tree | ec38f8e9d9626f143f4578b645df0e71f9f97d5a | |
parent | 699e36e5b8e9f77b2be4c23f0b309e53be4b2880 (diff) |
drivers/clocksource/pistachio: Fix memory corruption in init
Driver init code incorrectly uses the block base address and as a result
clears clocksource structure's fields instead of the hardware registers.
Commit 09a998201649 ("timekeeping: Lift clocksource cacheline
restriction") has changed the offsets within pistachio_clocksource
structure and what has previously gone unnoticed now leads to a kernel
panic during boot.
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-rw-r--r-- | drivers/clocksource/time-pistachio.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/clocksource/time-pistachio.c b/drivers/clocksource/time-pistachio.c index a7d9a08e4b0e..a8e6c7df853d 100644 --- a/drivers/clocksource/time-pistachio.c +++ b/drivers/clocksource/time-pistachio.c | |||
@@ -202,10 +202,10 @@ static int __init pistachio_clksrc_of_init(struct device_node *node) | |||
202 | rate = clk_get_rate(fast_clk); | 202 | rate = clk_get_rate(fast_clk); |
203 | 203 | ||
204 | /* Disable irq's for clocksource usage */ | 204 | /* Disable irq's for clocksource usage */ |
205 | gpt_writel(&pcs_gpt.base, 0, TIMER_IRQ_MASK, 0); | 205 | gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 0); |
206 | gpt_writel(&pcs_gpt.base, 0, TIMER_IRQ_MASK, 1); | 206 | gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 1); |
207 | gpt_writel(&pcs_gpt.base, 0, TIMER_IRQ_MASK, 2); | 207 | gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 2); |
208 | gpt_writel(&pcs_gpt.base, 0, TIMER_IRQ_MASK, 3); | 208 | gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 3); |
209 | 209 | ||
210 | /* Enable timer block */ | 210 | /* Enable timer block */ |
211 | writel(TIMER_ME_GLOBAL, pcs_gpt.base); | 211 | writel(TIMER_ME_GLOBAL, pcs_gpt.base); |