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authorDave Jiang <dave.jiang@intel.com>2018-06-11 15:49:03 -0400
committerVinod Koul <vkoul@kernel.org>2018-06-19 00:30:16 -0400
commit4cb0e60112168594da2ac8a7752b0250c4387733 (patch)
tree05c7b217c60a1e897b0c93f76605300704eedfb6
parentce397d215ccd07b8ae3f71db689aedb85d56ab40 (diff)
dmaengine: ioatdma: set the completion address register after channel reset
It seems that starting with Skylake Xeon, channel reset clears the completion address register. Make sure the completion address register is set again after reset. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
-rw-r--r--drivers/dma/ioat/dma.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c
index 8b5b23a8ace9..23fb2fa04000 100644
--- a/drivers/dma/ioat/dma.c
+++ b/drivers/dma/ioat/dma.c
@@ -688,6 +688,12 @@ static void ioat_restart_channel(struct ioatdma_chan *ioat_chan)
688{ 688{
689 u64 phys_complete; 689 u64 phys_complete;
690 690
691 /* set the completion address register again */
692 writel(lower_32_bits(ioat_chan->completion_dma),
693 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
694 writel(upper_32_bits(ioat_chan->completion_dma),
695 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
696
691 ioat_quiesce(ioat_chan, 0); 697 ioat_quiesce(ioat_chan, 0);
692 if (ioat_cleanup_preamble(ioat_chan, &phys_complete)) 698 if (ioat_cleanup_preamble(ioat_chan, &phys_complete))
693 __cleanup(ioat_chan, phys_complete); 699 __cleanup(ioat_chan, phys_complete);