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authorGeert Uytterhoeven <geert+renesas@glider.be>2015-01-20 08:44:58 -0500
committerSimon Horman <horms+renesas@verge.net.au>2016-04-27 00:15:03 -0400
commit4c8eb3c8896d842d3fb4802dc6e5f39733596733 (patch)
tree3dd8113175061014961d7a6b0b0ea504a1e746cf
parentb2df3aa487395a1b7170b719569769bc78939dd1 (diff)
ARM: dts: r8a7790: Add SYSC PM Domains
Add a device node for the System Controller. Hook up the Cortex-A15 and Cortex-A7 CPU cores and L2 caches/SCUs to their respective PM Domains. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi17
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 776a2aed81d2..36c91d921771 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -13,6 +13,7 @@
13#include <dt-bindings/clock/r8a7790-clock.h> 13#include <dt-bindings/clock/r8a7790-clock.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/power/r8a7790-sysc.h>
16 17
17/ { 18/ {
18 compatible = "renesas,r8a7790"; 19 compatible = "renesas,r8a7790";
@@ -52,6 +53,7 @@
52 voltage-tolerance = <1>; /* 1% */ 53 voltage-tolerance = <1>; /* 1% */
53 clocks = <&cpg_clocks R8A7790_CLK_Z>; 54 clocks = <&cpg_clocks R8A7790_CLK_Z>;
54 clock-latency = <300000>; /* 300 us */ 55 clock-latency = <300000>; /* 300 us */
56 power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
55 next-level-cache = <&L2_CA15>; 57 next-level-cache = <&L2_CA15>;
56 58
57 /* kHz - uV - OPPs unknown yet */ 59 /* kHz - uV - OPPs unknown yet */
@@ -68,6 +70,7 @@
68 compatible = "arm,cortex-a15"; 70 compatible = "arm,cortex-a15";
69 reg = <1>; 71 reg = <1>;
70 clock-frequency = <1300000000>; 72 clock-frequency = <1300000000>;
73 power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
71 next-level-cache = <&L2_CA15>; 74 next-level-cache = <&L2_CA15>;
72 }; 75 };
73 76
@@ -76,6 +79,7 @@
76 compatible = "arm,cortex-a15"; 79 compatible = "arm,cortex-a15";
77 reg = <2>; 80 reg = <2>;
78 clock-frequency = <1300000000>; 81 clock-frequency = <1300000000>;
82 power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
79 next-level-cache = <&L2_CA15>; 83 next-level-cache = <&L2_CA15>;
80 }; 84 };
81 85
@@ -84,6 +88,7 @@
84 compatible = "arm,cortex-a15"; 88 compatible = "arm,cortex-a15";
85 reg = <3>; 89 reg = <3>;
86 clock-frequency = <1300000000>; 90 clock-frequency = <1300000000>;
91 power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
87 next-level-cache = <&L2_CA15>; 92 next-level-cache = <&L2_CA15>;
88 }; 93 };
89 94
@@ -92,6 +97,7 @@
92 compatible = "arm,cortex-a7"; 97 compatible = "arm,cortex-a7";
93 reg = <0x100>; 98 reg = <0x100>;
94 clock-frequency = <780000000>; 99 clock-frequency = <780000000>;
100 power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
95 next-level-cache = <&L2_CA7>; 101 next-level-cache = <&L2_CA7>;
96 }; 102 };
97 103
@@ -100,6 +106,7 @@
100 compatible = "arm,cortex-a7"; 106 compatible = "arm,cortex-a7";
101 reg = <0x101>; 107 reg = <0x101>;
102 clock-frequency = <780000000>; 108 clock-frequency = <780000000>;
109 power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
103 next-level-cache = <&L2_CA7>; 110 next-level-cache = <&L2_CA7>;
104 }; 111 };
105 112
@@ -108,6 +115,7 @@
108 compatible = "arm,cortex-a7"; 115 compatible = "arm,cortex-a7";
109 reg = <0x102>; 116 reg = <0x102>;
110 clock-frequency = <780000000>; 117 clock-frequency = <780000000>;
118 power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
111 next-level-cache = <&L2_CA7>; 119 next-level-cache = <&L2_CA7>;
112 }; 120 };
113 121
@@ -116,6 +124,7 @@
116 compatible = "arm,cortex-a7"; 124 compatible = "arm,cortex-a7";
117 reg = <0x103>; 125 reg = <0x103>;
118 clock-frequency = <780000000>; 126 clock-frequency = <780000000>;
127 power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
119 next-level-cache = <&L2_CA7>; 128 next-level-cache = <&L2_CA7>;
120 }; 129 };
121 }; 130 };
@@ -141,12 +150,14 @@
141 150
142 L2_CA15: cache-controller@0 { 151 L2_CA15: cache-controller@0 {
143 compatible = "cache"; 152 compatible = "cache";
153 power-domains = <&sysc R8A7790_PD_CA15_SCU>;
144 cache-unified; 154 cache-unified;
145 cache-level = <2>; 155 cache-level = <2>;
146 }; 156 };
147 157
148 L2_CA7: cache-controller@1 { 158 L2_CA7: cache-controller@1 {
149 compatible = "cache"; 159 compatible = "cache";
160 power-domains = <&sysc R8A7790_PD_CA7_SCU>;
150 cache-unified; 161 cache-unified;
151 cache-level = <2>; 162 cache-level = <2>;
152 }; 163 };
@@ -1450,6 +1461,12 @@
1450 }; 1461 };
1451 }; 1462 };
1452 1463
1464 sysc: system-controller@e6180000 {
1465 compatible = "renesas,r8a7790-sysc";
1466 reg = <0 0xe6180000 0 0x0200>;
1467 #power-domain-cells = <1>;
1468 };
1469
1453 qspi: spi@e6b10000 { 1470 qspi: spi@e6b10000 {
1454 compatible = "renesas,qspi-r8a7790", "renesas,qspi"; 1471 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1455 reg = <0 0xe6b10000 0 0x2c>; 1472 reg = <0 0xe6b10000 0 0x2c>;