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authorVivek Gautam <vivek.gautam@codeaurora.org>2017-07-19 11:59:08 -0400
committerThierry Reding <treding@nvidia.com>2018-03-19 04:42:39 -0400
commit4c817ccf73abaf7b06a2630e8352d82648c8bc70 (patch)
tree5d2f68eb642bfa3c99fde676b8ffd7a085f190b5
parent507c655a06c8553a67122c371608b024b997b0e0 (diff)
soc/tegra: pmc: Use the new reset APIs to manage reset controllers
Make use of of_reset_control_array_get_exclusive() to manage an array of reset controllers available with the device. Cc: Jon Hunter <jonathanh@nvidia.com> Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> [p.zabel@pengutronix.de: switch to hidden reset control array] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--drivers/soc/tegra/pmc.c92
1 files changed, 18 insertions, 74 deletions
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index 0efdc4ec019f..d9fcdb592b39 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -127,8 +127,7 @@ struct tegra_powergate {
127 unsigned int id; 127 unsigned int id;
128 struct clk **clks; 128 struct clk **clks;
129 unsigned int num_clks; 129 unsigned int num_clks;
130 struct reset_control **resets; 130 struct reset_control *reset;
131 unsigned int num_resets;
132}; 131};
133 132
134struct tegra_io_pad_soc { 133struct tegra_io_pad_soc {
@@ -369,34 +368,6 @@ out:
369 return err; 368 return err;
370} 369}
371 370
372static int tegra_powergate_reset_assert(struct tegra_powergate *pg)
373{
374 unsigned int i;
375 int err;
376
377 for (i = 0; i < pg->num_resets; i++) {
378 err = reset_control_assert(pg->resets[i]);
379 if (err)
380 return err;
381 }
382
383 return 0;
384}
385
386static int tegra_powergate_reset_deassert(struct tegra_powergate *pg)
387{
388 unsigned int i;
389 int err;
390
391 for (i = 0; i < pg->num_resets; i++) {
392 err = reset_control_deassert(pg->resets[i]);
393 if (err)
394 return err;
395 }
396
397 return 0;
398}
399
400int __weak tegra210_clk_handle_mbist_war(unsigned int id) 371int __weak tegra210_clk_handle_mbist_war(unsigned int id)
401{ 372{
402 return 0; 373 return 0;
@@ -407,7 +378,7 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg,
407{ 378{
408 int err; 379 int err;
409 380
410 err = tegra_powergate_reset_assert(pg); 381 err = reset_control_assert(pg->reset);
411 if (err) 382 if (err)
412 return err; 383 return err;
413 384
@@ -431,7 +402,7 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg,
431 402
432 usleep_range(10, 20); 403 usleep_range(10, 20);
433 404
434 err = tegra_powergate_reset_deassert(pg); 405 err = reset_control_deassert(pg->reset);
435 if (err) 406 if (err)
436 goto powergate_off; 407 goto powergate_off;
437 408
@@ -467,7 +438,7 @@ static int tegra_powergate_power_down(struct tegra_powergate *pg)
467 438
468 usleep_range(10, 20); 439 usleep_range(10, 20);
469 440
470 err = tegra_powergate_reset_assert(pg); 441 err = reset_control_assert(pg->reset);
471 if (err) 442 if (err)
472 goto disable_clks; 443 goto disable_clks;
473 444
@@ -486,7 +457,7 @@ static int tegra_powergate_power_down(struct tegra_powergate *pg)
486assert_resets: 457assert_resets:
487 tegra_powergate_enable_clocks(pg); 458 tegra_powergate_enable_clocks(pg);
488 usleep_range(10, 20); 459 usleep_range(10, 20);
489 tegra_powergate_reset_deassert(pg); 460 reset_control_deassert(pg->reset);
490 usleep_range(10, 20); 461 usleep_range(10, 20);
491 462
492disable_clks: 463disable_clks:
@@ -597,8 +568,7 @@ int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
597 pg.id = id; 568 pg.id = id;
598 pg.clks = &clk; 569 pg.clks = &clk;
599 pg.num_clks = 1; 570 pg.num_clks = 1;
600 pg.resets = &rst; 571 pg.reset = rst;
601 pg.num_resets = 1;
602 pg.pmc = pmc; 572 pg.pmc = pmc;
603 573
604 err = tegra_powergate_power_up(&pg, false); 574 err = tegra_powergate_power_up(&pg, false);
@@ -787,45 +757,22 @@ err:
787static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 757static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
788 struct device_node *np, bool off) 758 struct device_node *np, bool off)
789{ 759{
790 struct reset_control *rst;
791 unsigned int i, count;
792 int err; 760 int err;
793 761
794 count = of_count_phandle_with_args(np, "resets", "#reset-cells"); 762 pg->reset = of_reset_control_array_get_exclusive(np);
795 if (count == 0) 763 if (IS_ERR(pg->reset)) {
796 return -ENODEV; 764 err = PTR_ERR(pg->reset);
797 765 pr_err("failed to get device resets: %d\n", err);
798 pg->resets = kcalloc(count, sizeof(rst), GFP_KERNEL); 766 return err;
799 if (!pg->resets)
800 return -ENOMEM;
801
802 for (i = 0; i < count; i++) {
803 pg->resets[i] = of_reset_control_get_by_index(np, i);
804 if (IS_ERR(pg->resets[i])) {
805 err = PTR_ERR(pg->resets[i]);
806 goto error;
807 }
808
809 if (off)
810 err = reset_control_assert(pg->resets[i]);
811 else
812 err = reset_control_deassert(pg->resets[i]);
813
814 if (err) {
815 reset_control_put(pg->resets[i]);
816 goto error;
817 }
818 } 767 }
819 768
820 pg->num_resets = count; 769 if (off)
821 770 err = reset_control_assert(pg->reset);
822 return 0; 771 else
823 772 err = reset_control_deassert(pg->reset);
824error:
825 while (i--)
826 reset_control_put(pg->resets[i]);
827 773
828 kfree(pg->resets); 774 if (err)
775 reset_control_put(pg->reset);
829 776
830 return err; 777 return err;
831} 778}
@@ -917,10 +864,7 @@ remove_genpd:
917 pm_genpd_remove(&pg->genpd); 864 pm_genpd_remove(&pg->genpd);
918 865
919remove_resets: 866remove_resets:
920 while (pg->num_resets--) 867 reset_control_put(pg->reset);
921 reset_control_put(pg->resets[pg->num_resets]);
922
923 kfree(pg->resets);
924 868
925remove_clks: 869remove_clks:
926 while (pg->num_clks--) 870 while (pg->num_clks--)