Merge tag 'drm-intel-next-fixes-2018-12-27' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

GVT fixes for v4.21-rc1

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87imzfwh73.fsf@intel.com

6 files changed, 43 insertions, 5 deletions

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 77edbfcb0f75..77ae634eb11c 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -1900,11 +1900,11 @@ static struct cmd_info cmd_info[] = {
 
         {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
 
-        {"ME_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL, F_LEN_VAR, R_ALL,
+        {"MI_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL, F_LEN_VAR, R_ALL,
                 D_BDW_PLUS, 0, 8, NULL},
 
-        {"ME_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT, F_LEN_VAR, R_ALL, D_BDW_PLUS,
-                ADDR_FIX_1(2), 8, cmd_handler_mi_semaphore_wait},
+        {"MI_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT, F_LEN_VAR, R_ALL,
+                D_BDW_PLUS, ADDR_FIX_1(2), 8, cmd_handler_mi_semaphore_wait},
 
         {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
                 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c
index 6ef5a7fc70df..733a2a0d0c30 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.c
+++ b/drivers/gpu/drm/i915/gvt/gvt.c
@@ -437,7 +437,7 @@ int intel_gvt_init_device(struct drm_i915_private *dev_priv)
 
         ret = intel_gvt_debugfs_init(gvt);
         if (ret)
-                gvt_err("debugfs registeration failed, go on.\n");
+                gvt_err("debugfs registration failed, go on.\n");
 
         gvt_dbg_core("gvt device initialization is done\n");
         dev_priv->gvt = gvt;
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 31f6cdbe5c42..b4ab1dad0143 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -159,6 +159,10 @@ struct intel_vgpu_submission {
         struct kmem_cache *workloads;
         atomic_t running_workload_num;
         struct i915_gem_context *shadow_ctx;
+        union {
+                u64 i915_context_pml4;
+                u64 i915_context_pdps[GEN8_3LVL_PDPES];
+        };
         DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
         DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
         void *ring_scan_buffer[I915_NUM_ENGINES];
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index aa280bb07125..b5475c91e2ef 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -475,6 +475,7 @@ static i915_reg_t force_nonpriv_white_list[] = {
         _MMIO(0x7704),
         _MMIO(0x7708),
         _MMIO(0x770c),
+        _MMIO(0x83a8),
         _MMIO(0xb110),
         GEN8_L3SQCREG4,//_MMIO(0xb118)
         _MMIO(0xe100),
diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c
index 5daa23ae566b..6b9d1354ff29 100644
--- a/drivers/gpu/drm/i915/gvt/interrupt.c
+++ b/drivers/gpu/drm/i915/gvt/interrupt.c
@@ -126,7 +126,7 @@ static const char * const irq_name[INTEL_GVT_EVENT_MAX] = {
         [FDI_RX_INTERRUPTS_TRANSCODER_C] = "FDI RX Interrupts Combined C",
         [AUDIO_CP_CHANGE_TRANSCODER_C] = "Audio CP Change Transcoder C",
         [AUDIO_CP_REQUEST_TRANSCODER_C] = "Audio CP Request Transcoder C",
-        [ERR_AND_DBG] = "South Error and Debug Interupts Combined",
+        [ERR_AND_DBG] = "South Error and Debug Interrupts Combined",
         [GMBUS] = "Gmbus",
         [SDVO_B_HOTPLUG] = "SDVO B hotplug",
         [CRT_HOTPLUG] = "CRT Hotplug",
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index b8fbe3fabea3..1ad8c5e1455d 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -1079,6 +1079,21 @@ err:
         return ret;
 }
 
+static void
+i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s)
+{
+        struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
+        int i;
+
+        if (i915_vm_is_48bit(&i915_ppgtt->vm))
+                px_dma(&i915_ppgtt->pml4) = s->i915_context_pml4;
+        else {
+                for (i = 0; i < GEN8_3LVL_PDPES; i++)
+                        px_dma(i915_ppgtt->pdp.page_directory[i]) =
+                                                s->i915_context_pdps[i];
+        }
+}
+
 /**
  * intel_vgpu_clean_submission - free submission-related resource for vGPU
  * @vgpu: a vGPU
@@ -1091,6 +1106,7 @@ void intel_vgpu_clean_submission(struct intel_vgpu *vgpu)
         struct intel_vgpu_submission *s = &vgpu->submission;
 
         intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
+        i915_context_ppgtt_root_restore(s);
         i915_gem_context_put(s->shadow_ctx);
         kmem_cache_destroy(s->workloads);
 }
@@ -1116,6 +1132,21 @@ void intel_vgpu_reset_submission(struct intel_vgpu *vgpu,
         s->ops->reset(vgpu, engine_mask);
 }
 
+static void
+i915_context_ppgtt_root_save(struct intel_vgpu_submission *s)
+{
+        struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
+        int i;
+
+        if (i915_vm_is_48bit(&i915_ppgtt->vm))
+                s->i915_context_pml4 = px_dma(&i915_ppgtt->pml4);
+        else {
+                for (i = 0; i < GEN8_3LVL_PDPES; i++)
+                        s->i915_context_pdps[i] =
+                                px_dma(i915_ppgtt->pdp.page_directory[i]);
+        }
+}
+
 /**
  * intel_vgpu_setup_submission - setup submission-related resource for vGPU
  * @vgpu: a vGPU
@@ -1138,6 +1169,8 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
         if (IS_ERR(s->shadow_ctx))
                 return PTR_ERR(s->shadow_ctx);
 
+        i915_context_ppgtt_root_save(s);
+
         bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
 
         s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload",