diff options
author | Rex Zhu <Rex.Zhu@amd.com> | 2017-04-20 04:33:23 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2017-04-28 17:32:51 -0400 |
commit | 4bae05e196c518c2c95022fbdbee551bbc6893a5 (patch) | |
tree | 46f894cc88c4d94dddcbaea24424b4fb99f2fec1 | |
parent | afc0255c9a5ecede2f235f4d117c2913059aa3c3 (diff) |
drm/amd/powerplay: Fix AVFS param.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c index 0042c339415f..278def7380e7 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | |||
@@ -2163,7 +2163,7 @@ static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) | |||
2163 | 2163 | ||
2164 | pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1_shift = 24; | 2164 | pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1_shift = 24; |
2165 | pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2_shift = 12; | 2165 | pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2_shift = 12; |
2166 | pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b_shift = 0; | 2166 | pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b_shift = 12; |
2167 | 2167 | ||
2168 | if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != | 2168 | if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != |
2169 | data->dcef_clk_quad_eqn_a) && | 2169 | data->dcef_clk_quad_eqn_a) && |
@@ -2186,7 +2186,7 @@ static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) | |||
2186 | 2186 | ||
2187 | pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1_shift = 24; | 2187 | pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1_shift = 24; |
2188 | pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2_shift = 12; | 2188 | pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2_shift = 12; |
2189 | pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b_shift = 0; | 2189 | pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b_shift = 12; |
2190 | 2190 | ||
2191 | if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != | 2191 | if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != |
2192 | data->pixel_clk_quad_eqn_a) && | 2192 | data->pixel_clk_quad_eqn_a) && |
@@ -2209,7 +2209,7 @@ static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) | |||
2209 | 2209 | ||
2210 | pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1_shift = 24; | 2210 | pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1_shift = 24; |
2211 | pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2_shift = 12; | 2211 | pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2_shift = 12; |
2212 | 2212 | pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b_shift = 12; | |
2213 | if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != | 2213 | if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != |
2214 | data->phy_clk_quad_eqn_a) && | 2214 | data->phy_clk_quad_eqn_a) && |
2215 | (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != | 2215 | (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != |
@@ -2231,7 +2231,7 @@ static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) | |||
2231 | 2231 | ||
2232 | pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1_shift = 24; | 2232 | pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1_shift = 24; |
2233 | pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2_shift = 12; | 2233 | pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2_shift = 12; |
2234 | pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b_shift = 0; | 2234 | pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b_shift = 12; |
2235 | } else { | 2235 | } else { |
2236 | data->smu_features[GNLD_AVFS].supported = false; | 2236 | data->smu_features[GNLD_AVFS].supported = false; |
2237 | } | 2237 | } |