diff options
author | Jani Nikula <jani.nikula@intel.com> | 2018-02-01 06:03:42 -0500 |
---|---|---|
committer | Jani Nikula <jani.nikula@intel.com> | 2018-02-02 02:50:45 -0500 |
commit | 4ba285d4154ab587cc00bf9bd04bb8c7b19b595a (patch) | |
tree | 28d7d468464691d6d8f83ca8c2e8869819534eb2 | |
parent | 10ebb736960cd90eeec7239da2c2b3e8c8a24ef6 (diff) |
drm/i915/dp: clean up source rate limiting for cnl
Make the limiting rate based instead of messing with the array size.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/cb03b9419191a7d6359bf371aacb2d3725c746de.1517482774.git.jani.nikula@intel.com
-rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 1d4eced394cf..bee510514826 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c | |||
@@ -240,7 +240,7 @@ intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp) | |||
240 | return max_dotclk; | 240 | return max_dotclk; |
241 | } | 241 | } |
242 | 242 | ||
243 | static int cnl_adjusted_max_rate(struct intel_dp *intel_dp, int size) | 243 | static int cnl_max_source_rate(struct intel_dp *intel_dp) |
244 | { | 244 | { |
245 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | 245 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
246 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | 246 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
@@ -250,17 +250,17 @@ static int cnl_adjusted_max_rate(struct intel_dp *intel_dp, int size) | |||
250 | 250 | ||
251 | /* Low voltage SKUs are limited to max of 5.4G */ | 251 | /* Low voltage SKUs are limited to max of 5.4G */ |
252 | if (voltage == VOLTAGE_INFO_0_85V) | 252 | if (voltage == VOLTAGE_INFO_0_85V) |
253 | return size - 2; | 253 | return 540000; |
254 | 254 | ||
255 | /* For this SKU 8.1G is supported in all ports */ | 255 | /* For this SKU 8.1G is supported in all ports */ |
256 | if (IS_CNL_WITH_PORT_F(dev_priv)) | 256 | if (IS_CNL_WITH_PORT_F(dev_priv)) |
257 | return size; | 257 | return 810000; |
258 | 258 | ||
259 | /* For other SKUs, max rate on ports A and B is 5.4G */ | 259 | /* For other SKUs, max rate on ports A and B is 5.4G */ |
260 | if (port == PORT_A || port == PORT_D) | 260 | if (port == PORT_A || port == PORT_D) |
261 | return size - 2; | 261 | return 540000; |
262 | 262 | ||
263 | return size; | 263 | return 810000; |
264 | } | 264 | } |
265 | 265 | ||
266 | static void | 266 | static void |
@@ -269,7 +269,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) | |||
269 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | 269 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
270 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | 270 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
271 | const int *source_rates; | 271 | const int *source_rates; |
272 | int size; | 272 | int size, max_rate = 0; |
273 | 273 | ||
274 | /* This should only be done once */ | 274 | /* This should only be done once */ |
275 | WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates); | 275 | WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates); |
@@ -279,7 +279,8 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) | |||
279 | size = ARRAY_SIZE(bxt_rates); | 279 | size = ARRAY_SIZE(bxt_rates); |
280 | } else if (IS_CANNONLAKE(dev_priv)) { | 280 | } else if (IS_CANNONLAKE(dev_priv)) { |
281 | source_rates = cnl_rates; | 281 | source_rates = cnl_rates; |
282 | size = cnl_adjusted_max_rate(intel_dp, ARRAY_SIZE(cnl_rates)); | 282 | size = ARRAY_SIZE(cnl_rates); |
283 | max_rate = cnl_max_source_rate(intel_dp); | ||
283 | } else if (IS_GEN9_BC(dev_priv)) { | 284 | } else if (IS_GEN9_BC(dev_priv)) { |
284 | source_rates = skl_rates; | 285 | source_rates = skl_rates; |
285 | size = ARRAY_SIZE(skl_rates); | 286 | size = ARRAY_SIZE(skl_rates); |
@@ -292,6 +293,9 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) | |||
292 | size = ARRAY_SIZE(default_rates) - 1; | 293 | size = ARRAY_SIZE(default_rates) - 1; |
293 | } | 294 | } |
294 | 295 | ||
296 | if (max_rate) | ||
297 | size = intel_dp_rate_limit_len(source_rates, size, max_rate); | ||
298 | |||
295 | intel_dp->source_rates = source_rates; | 299 | intel_dp->source_rates = source_rates; |
296 | intel_dp->num_source_rates = size; | 300 | intel_dp->num_source_rates = size; |
297 | } | 301 | } |