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authorYue Hin Lau <Yuehin.Lau@amd.com>2017-12-08 15:57:44 -0500
committerAlex Deucher <alexander.deucher@amd.com>2017-12-20 14:48:08 -0500
commit4b8240bf916f047e7b8b225e2240d93052de374f (patch)
treee3d978bdf9ba92f66f7a702998f7c9ac230e8ef5
parent4b4f8f74a8e36e6be8b13c1573c7d299c3b8cf49 (diff)
drm/amd/display: hubp refactor
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c18
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h216
2 files changed, 120 insertions, 114 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 943b7ac17ed9..585b33384002 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -107,10 +107,12 @@ static void hubp1_vready_workaround(struct hubp *hubp,
107} 107}
108 108
109void hubp1_program_tiling( 109void hubp1_program_tiling(
110 struct dcn10_hubp *hubp1, 110 struct hubp *hubp,
111 const union dc_tiling_info *info, 111 const union dc_tiling_info *info,
112 const enum surface_pixel_format pixel_format) 112 const enum surface_pixel_format pixel_format)
113{ 113{
114 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
115
114 REG_UPDATE_6(DCSURF_ADDR_CONFIG, 116 REG_UPDATE_6(DCSURF_ADDR_CONFIG,
115 NUM_PIPES, log_2(info->gfx9.num_pipes), 117 NUM_PIPES, log_2(info->gfx9.num_pipes),
116 NUM_BANKS, log_2(info->gfx9.num_banks), 118 NUM_BANKS, log_2(info->gfx9.num_banks),
@@ -127,13 +129,14 @@ void hubp1_program_tiling(
127} 129}
128 130
129void hubp1_program_size_and_rotation( 131void hubp1_program_size_and_rotation(
130 struct dcn10_hubp *hubp1, 132 struct hubp *hubp,
131 enum dc_rotation_angle rotation, 133 enum dc_rotation_angle rotation,
132 enum surface_pixel_format format, 134 enum surface_pixel_format format,
133 const union plane_size *plane_size, 135 const union plane_size *plane_size,
134 struct dc_plane_dcc_param *dcc, 136 struct dc_plane_dcc_param *dcc,
135 bool horizontal_mirror) 137 bool horizontal_mirror)
136{ 138{
139 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
137 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c, mirror; 140 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c, mirror;
138 141
139 /* Program data and meta surface pitch (calculation from addrlib) 142 /* Program data and meta surface pitch (calculation from addrlib)
@@ -189,9 +192,10 @@ void hubp1_program_size_and_rotation(
189} 192}
190 193
191void hubp1_program_pixel_format( 194void hubp1_program_pixel_format(
192 struct dcn10_hubp *hubp1, 195 struct hubp *hubp,
193 enum surface_pixel_format format) 196 enum surface_pixel_format format)
194{ 197{
198 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
195 uint32_t red_bar = 3; 199 uint32_t red_bar = 3;
196 uint32_t blue_bar = 2; 200 uint32_t blue_bar = 2;
197 201
@@ -435,13 +439,11 @@ void hubp1_program_surface_config(
435 struct dc_plane_dcc_param *dcc, 439 struct dc_plane_dcc_param *dcc,
436 bool horizontal_mirror) 440 bool horizontal_mirror)
437{ 441{
438 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
439
440 hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks); 442 hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks);
441 hubp1_program_tiling(hubp1, tiling_info, format); 443 hubp1_program_tiling(hubp, tiling_info, format);
442 hubp1_program_size_and_rotation( 444 hubp1_program_size_and_rotation(
443 hubp1, rotation, format, plane_size, dcc, horizontal_mirror); 445 hubp, rotation, format, plane_size, dcc, horizontal_mirror);
444 hubp1_program_pixel_format(hubp1, format); 446 hubp1_program_pixel_format(hubp, format);
445} 447}
446 448
447void hubp1_program_requestor( 449void hubp1_program_requestor(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index 58a792f522f3..26f638d36a20 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -127,112 +127,114 @@
127 SRI(CURSOR_HOT_SPOT, CURSOR, id), \ 127 SRI(CURSOR_HOT_SPOT, CURSOR, id), \
128 SRI(CURSOR_DST_OFFSET, CURSOR, id) 128 SRI(CURSOR_DST_OFFSET, CURSOR, id)
129 129
130#define HUBP_COMMON_REG_VARIABLE_LIST \
131 uint32_t DCHUBP_CNTL; \
132 uint32_t HUBPREQ_DEBUG_DB; \
133 uint32_t DCSURF_ADDR_CONFIG; \
134 uint32_t DCSURF_TILING_CONFIG; \
135 uint32_t DCSURF_SURFACE_PITCH; \
136 uint32_t DCSURF_SURFACE_PITCH_C; \
137 uint32_t DCSURF_SURFACE_CONFIG; \
138 uint32_t DCSURF_FLIP_CONTROL; \
139 uint32_t DCSURF_PRI_VIEWPORT_DIMENSION; \
140 uint32_t DCSURF_PRI_VIEWPORT_START; \
141 uint32_t DCSURF_SEC_VIEWPORT_DIMENSION; \
142 uint32_t DCSURF_SEC_VIEWPORT_START; \
143 uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C; \
144 uint32_t DCSURF_PRI_VIEWPORT_START_C; \
145 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; \
146 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; \
147 uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH; \
148 uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS; \
149 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH; \
150 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS; \
151 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH; \
152 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS; \
153 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; \
154 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; \
155 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C; \
156 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C; \
157 uint32_t DCSURF_SURFACE_INUSE; \
158 uint32_t DCSURF_SURFACE_INUSE_HIGH; \
159 uint32_t DCSURF_SURFACE_INUSE_C; \
160 uint32_t DCSURF_SURFACE_INUSE_HIGH_C; \
161 uint32_t DCSURF_SURFACE_EARLIEST_INUSE; \
162 uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH; \
163 uint32_t DCSURF_SURFACE_EARLIEST_INUSE_C; \
164 uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C; \
165 uint32_t DCSURF_SURFACE_CONTROL; \
166 uint32_t HUBPRET_CONTROL; \
167 uint32_t DCN_EXPANSION_MODE; \
168 uint32_t DCHUBP_REQ_SIZE_CONFIG; \
169 uint32_t DCHUBP_REQ_SIZE_CONFIG_C; \
170 uint32_t BLANK_OFFSET_0; \
171 uint32_t BLANK_OFFSET_1; \
172 uint32_t DST_DIMENSIONS; \
173 uint32_t DST_AFTER_SCALER; \
174 uint32_t PREFETCH_SETTINS; \
175 uint32_t PREFETCH_SETTINGS; \
176 uint32_t VBLANK_PARAMETERS_0; \
177 uint32_t REF_FREQ_TO_PIX_FREQ; \
178 uint32_t VBLANK_PARAMETERS_1; \
179 uint32_t VBLANK_PARAMETERS_3; \
180 uint32_t NOM_PARAMETERS_0; \
181 uint32_t NOM_PARAMETERS_1; \
182 uint32_t NOM_PARAMETERS_4; \
183 uint32_t NOM_PARAMETERS_5; \
184 uint32_t PER_LINE_DELIVERY_PRE; \
185 uint32_t PER_LINE_DELIVERY; \
186 uint32_t PREFETCH_SETTINS_C; \
187 uint32_t PREFETCH_SETTINGS_C; \
188 uint32_t VBLANK_PARAMETERS_2; \
189 uint32_t VBLANK_PARAMETERS_4; \
190 uint32_t NOM_PARAMETERS_2; \
191 uint32_t NOM_PARAMETERS_3; \
192 uint32_t NOM_PARAMETERS_6; \
193 uint32_t NOM_PARAMETERS_7; \
194 uint32_t DCN_TTU_QOS_WM; \
195 uint32_t DCN_GLOBAL_TTU_CNTL; \
196 uint32_t DCN_SURF0_TTU_CNTL0; \
197 uint32_t DCN_SURF0_TTU_CNTL1; \
198 uint32_t DCN_SURF1_TTU_CNTL0; \
199 uint32_t DCN_SURF1_TTU_CNTL1; \
200 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB; \
201 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB; \
202 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB; \
203 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB; \
204 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB; \
205 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB; \
206 uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB; \
207 uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB; \
208 uint32_t DCN_VM_MX_L1_TLB_CNTL; \
209 uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; \
210 uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; \
211 uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB; \
212 uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB; \
213 uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB; \
214 uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB; \
215 uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR; \
216 uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR; \
217 uint32_t DCHUBBUB_SDPIF_FB_BASE; \
218 uint32_t DCHUBBUB_SDPIF_FB_OFFSET; \
219 uint32_t DCN_VM_FB_LOCATION_TOP; \
220 uint32_t DCN_VM_FB_LOCATION_BASE; \
221 uint32_t DCN_VM_FB_OFFSET; \
222 uint32_t DCN_VM_AGP_BASE; \
223 uint32_t DCN_VM_AGP_BOT; \
224 uint32_t DCN_VM_AGP_TOP; \
225 uint32_t CURSOR_SETTINS; \
226 uint32_t CURSOR_SETTINGS; \
227 uint32_t CURSOR_SURFACE_ADDRESS_HIGH; \
228 uint32_t CURSOR_SURFACE_ADDRESS; \
229 uint32_t CURSOR_SIZE; \
230 uint32_t CURSOR_CONTROL; \
231 uint32_t CURSOR_POSITION; \
232 uint32_t CURSOR_HOT_SPOT; \
233 uint32_t CURSOR_DST_OFFSET;
130 234
131 235
132struct dcn_mi_registers { 236struct dcn_mi_registers {
133 uint32_t DCHUBP_CNTL; 237 HUBP_COMMON_REG_VARIABLE_LIST
134 uint32_t HUBPREQ_DEBUG_DB;
135 uint32_t DCSURF_ADDR_CONFIG;
136 uint32_t DCSURF_TILING_CONFIG;
137 uint32_t DCSURF_SURFACE_PITCH;
138 uint32_t DCSURF_SURFACE_PITCH_C;
139 uint32_t DCSURF_SURFACE_CONFIG;
140 uint32_t DCSURF_FLIP_CONTROL;
141 uint32_t DCSURF_PRI_VIEWPORT_DIMENSION;
142 uint32_t DCSURF_PRI_VIEWPORT_START;
143 uint32_t DCSURF_SEC_VIEWPORT_DIMENSION;
144 uint32_t DCSURF_SEC_VIEWPORT_START;
145 uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C;
146 uint32_t DCSURF_PRI_VIEWPORT_START_C;
147 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH;
148 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS;
149 uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH;
150 uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS;
151 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH;
152 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS;
153 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH;
154 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS;
155 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C;
156 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C;
157 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C;
158 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C;
159 uint32_t DCSURF_SURFACE_INUSE;
160 uint32_t DCSURF_SURFACE_INUSE_HIGH;
161 uint32_t DCSURF_SURFACE_INUSE_C;
162 uint32_t DCSURF_SURFACE_INUSE_HIGH_C;
163 uint32_t DCSURF_SURFACE_EARLIEST_INUSE;
164 uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH;
165 uint32_t DCSURF_SURFACE_EARLIEST_INUSE_C;
166 uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C;
167 uint32_t DCSURF_SURFACE_CONTROL;
168 uint32_t HUBPRET_CONTROL;
169 uint32_t DCN_EXPANSION_MODE;
170 uint32_t DCHUBP_REQ_SIZE_CONFIG;
171 uint32_t DCHUBP_REQ_SIZE_CONFIG_C;
172 uint32_t BLANK_OFFSET_0;
173 uint32_t BLANK_OFFSET_1;
174 uint32_t DST_DIMENSIONS;
175 uint32_t DST_AFTER_SCALER;
176 uint32_t PREFETCH_SETTINS;
177 uint32_t PREFETCH_SETTINGS;
178 uint32_t VBLANK_PARAMETERS_0;
179 uint32_t REF_FREQ_TO_PIX_FREQ;
180 uint32_t VBLANK_PARAMETERS_1;
181 uint32_t VBLANK_PARAMETERS_3;
182 uint32_t NOM_PARAMETERS_0;
183 uint32_t NOM_PARAMETERS_1;
184 uint32_t NOM_PARAMETERS_4;
185 uint32_t NOM_PARAMETERS_5;
186 uint32_t PER_LINE_DELIVERY_PRE;
187 uint32_t PER_LINE_DELIVERY;
188 uint32_t PREFETCH_SETTINS_C;
189 uint32_t PREFETCH_SETTINGS_C;
190 uint32_t VBLANK_PARAMETERS_2;
191 uint32_t VBLANK_PARAMETERS_4;
192 uint32_t NOM_PARAMETERS_2;
193 uint32_t NOM_PARAMETERS_3;
194 uint32_t NOM_PARAMETERS_6;
195 uint32_t NOM_PARAMETERS_7;
196 uint32_t DCN_TTU_QOS_WM;
197 uint32_t DCN_GLOBAL_TTU_CNTL;
198 uint32_t DCN_SURF0_TTU_CNTL0;
199 uint32_t DCN_SURF0_TTU_CNTL1;
200 uint32_t DCN_SURF1_TTU_CNTL0;
201 uint32_t DCN_SURF1_TTU_CNTL1;
202 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB;
203 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB;
204 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB;
205 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB;
206 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB;
207 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB;
208 uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB;
209 uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;
210 uint32_t DCN_VM_MX_L1_TLB_CNTL;
211 uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;
212 uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;
213 uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB;
214 uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB;
215 uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB;
216 uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;
217 uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR;
218 uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR;
219 uint32_t DCHUBBUB_SDPIF_FB_BASE;
220 uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
221 uint32_t DCN_VM_FB_LOCATION_TOP;
222 uint32_t DCN_VM_FB_LOCATION_BASE;
223 uint32_t DCN_VM_FB_OFFSET;
224 uint32_t DCN_VM_AGP_BASE;
225 uint32_t DCN_VM_AGP_BOT;
226 uint32_t DCN_VM_AGP_TOP;
227 uint32_t CURSOR_SETTINS;
228 uint32_t CURSOR_SETTINGS;
229 uint32_t CURSOR_SURFACE_ADDRESS_HIGH;
230 uint32_t CURSOR_SURFACE_ADDRESS;
231 uint32_t CURSOR_SIZE;
232 uint32_t CURSOR_CONTROL;
233 uint32_t CURSOR_POSITION;
234 uint32_t CURSOR_HOT_SPOT;
235 uint32_t CURSOR_DST_OFFSET;
236}; 238};
237 239
238#define HUBP_SF(reg_name, field_name, post_fix)\ 240#define HUBP_SF(reg_name, field_name, post_fix)\
@@ -398,6 +400,8 @@ struct dcn_mi_registers {
398 HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh) 400 HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh)
399 401
400 402
403
404
401#define DCN_HUBP_REG_FIELD_LIST(type) \ 405#define DCN_HUBP_REG_FIELD_LIST(type) \
402 type HUBP_BLANK_EN;\ 406 type HUBP_BLANK_EN;\
403 type HUBP_TTU_DISABLE;\ 407 type HUBP_TTU_DISABLE;\
@@ -611,11 +615,11 @@ void hubp1_program_requestor(
611 struct _vcs_dpi_display_rq_regs_st *rq_regs); 615 struct _vcs_dpi_display_rq_regs_st *rq_regs);
612 616
613void hubp1_program_pixel_format( 617void hubp1_program_pixel_format(
614 struct dcn10_hubp *hubp, 618 struct hubp *hubp,
615 enum surface_pixel_format format); 619 enum surface_pixel_format format);
616 620
617void hubp1_program_size_and_rotation( 621void hubp1_program_size_and_rotation(
618 struct dcn10_hubp *hubp, 622 struct hubp *hubp,
619 enum dc_rotation_angle rotation, 623 enum dc_rotation_angle rotation,
620 enum surface_pixel_format format, 624 enum surface_pixel_format format,
621 const union plane_size *plane_size, 625 const union plane_size *plane_size,
@@ -623,7 +627,7 @@ void hubp1_program_size_and_rotation(
623 bool horizontal_mirror); 627 bool horizontal_mirror);
624 628
625void hubp1_program_tiling( 629void hubp1_program_tiling(
626 struct dcn10_hubp *hubp, 630 struct hubp *hubp,
627 const union dc_tiling_info *info, 631 const union dc_tiling_info *info,
628 const enum surface_pixel_format pixel_format); 632 const enum surface_pixel_format pixel_format);
629 633
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 12:11:33 -0400