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authorArnd Bergmann <arnd@arndb.de>2017-02-07 09:25:19 -0500
committerArnd Bergmann <arnd@arndb.de>2017-02-07 09:25:19 -0500
commit4b5f4835d16b0d8a7599e930b17e27fc6f1f3aba (patch)
treee79749ed5cf8ddafa2263f649fe418da227a4a87
parent54fe90874fd37caeb8914a1dee511920fa799c08 (diff)
parent390891d0baf82278a04835c8a62bb14dca98b96b (diff)
Merge tag 'stm32-dt-for-v4.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into next/dt
Pull "STM32 DT updates for v4.11, round 2" from Alexandre Torgue: Highlights: ---------- - ADD Timers support on STM32F429 MCU - Enable PWM1 & PWM3 on STM32F469 Disco board - Fix STM32F4_X_CLOCK macro - Use STM32F4_X_CLOCK macro in STM32 device tree - Add I2C1 support for STM32F429 MCU - Enable I2C1 on STM32F429 eval board * tag 'stm32-dt-for-v4.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: ARM: dts: stm32: Add I2C1 support for STM32429 eval board ARM: dts: stm32: Add I2C1 support for STM32F429 SoC ARM: dts: stm32: Use clock DT binding definition on stm32f429 family dt-bindings: mfd: stm32f4: Add missing binding definition dt-bindings: mfd: stm32f4: Fix STM32F4_X_CLOCK() macro ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco ARM: dts: stm32: add Timers driver for stm32f429 MCU
Diffstat
-rw-r--r--arch/arm/boot/dts/stm32429i-eval.dts8
-rw-r--r--arch/arm/boot/dts/stm32f429.dtsi371
-rw-r--r--arch/arm/boot/dts/stm32f469-disco.dts28
-rw-r--r--include/dt-bindings/mfd/stm32f4-rcc.h24
4 files changed, 388 insertions, 43 deletions
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index eedb27d33f66..3c99466989b1 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -121,7 +121,7 @@
121 usbotg_hs_phy: usbphy { 121 usbotg_hs_phy: usbphy {
122 #phy-cells = <0>; 122 #phy-cells = <0>;
123 compatible = "usb-nop-xceiv"; 123 compatible = "usb-nop-xceiv";
124 clocks = <&rcc 0 30>; 124 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>;
125 clock-names = "main_clk"; 125 clock-names = "main_clk";
126 }; 126 };
127}; 127};
@@ -141,6 +141,12 @@
141 clock-frequency = <25000000>; 141 clock-frequency = <25000000>;
142}; 142};
143 143
144&i2c1 {
145 pinctrl-0 = <&i2c1_pins>;
146 pinctrl-names = "default";
147 status = "okay";
148};
149
144&mac { 150&mac {
145 status = "okay"; 151 status = "okay";
146 pinctrl-0 = <&ethernet_mii>; 152 pinctrl-0 = <&ethernet_mii>;
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index f05a9d95ef23..ee0da970e8ad 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -49,6 +49,7 @@
49#include "armv7-m.dtsi" 49#include "armv7-m.dtsi"
50#include <dt-bindings/pinctrl/stm32f429-pinfunc.h> 50#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
51#include <dt-bindings/clock/stm32fx-clock.h> 51#include <dt-bindings/clock/stm32fx-clock.h>
52#include <dt-bindings/mfd/stm32f4-rcc.h>
52 53
53/ { 54/ {
54 clocks { 55 clocks {
@@ -82,47 +83,214 @@
82 compatible = "st,stm32-timer"; 83 compatible = "st,stm32-timer";
83 reg = <0x40000000 0x400>; 84 reg = <0x40000000 0x400>;
84 interrupts = <28>; 85 interrupts = <28>;
85 clocks = <&rcc 0 128>; 86 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
86 status = "disabled"; 87 status = "disabled";
87 }; 88 };
88 89
90 timers2: timers@40000000 {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 compatible = "st,stm32-timers";
94 reg = <0x40000000 0x400>;
95 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
96 clock-names = "int";
97 status = "disabled";
98
99 pwm {
100 compatible = "st,stm32-pwm";
101 status = "disabled";
102 };
103
104 timer@1 {
105 compatible = "st,stm32-timer-trigger";
106 reg = <1>;
107 status = "disabled";
108 };
109 };
110
89 timer3: timer@40000400 { 111 timer3: timer@40000400 {
90 compatible = "st,stm32-timer"; 112 compatible = "st,stm32-timer";
91 reg = <0x40000400 0x400>; 113 reg = <0x40000400 0x400>;
92 interrupts = <29>; 114 interrupts = <29>;
93 clocks = <&rcc 0 129>; 115 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
116 status = "disabled";
117 };
118
119 timers3: timers@40000400 {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 compatible = "st,stm32-timers";
123 reg = <0x40000400 0x400>;
124 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
125 clock-names = "int";
94 status = "disabled"; 126 status = "disabled";
127
128 pwm {
129 compatible = "st,stm32-pwm";
130 status = "disabled";
131 };
132
133 timer@2 {
134 compatible = "st,stm32-timer-trigger";
135 reg = <2>;
136 status = "disabled";
137 };
95 }; 138 };
96 139
97 timer4: timer@40000800 { 140 timer4: timer@40000800 {
98 compatible = "st,stm32-timer"; 141 compatible = "st,stm32-timer";
99 reg = <0x40000800 0x400>; 142 reg = <0x40000800 0x400>;
100 interrupts = <30>; 143 interrupts = <30>;
101 clocks = <&rcc 0 130>; 144 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
145 status = "disabled";
146 };
147
148 timers4: timers@40000800 {
149 #address-cells = <1>;
150 #size-cells = <0>;
151 compatible = "st,stm32-timers";
152 reg = <0x40000800 0x400>;
153 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
154 clock-names = "int";
102 status = "disabled"; 155 status = "disabled";
156
157 pwm {
158 compatible = "st,stm32-pwm";
159 status = "disabled";
160 };
161
162 timer@3 {
163 compatible = "st,stm32-timer-trigger";
164 reg = <3>;
165 status = "disabled";
166 };
103 }; 167 };
104 168
105 timer5: timer@40000c00 { 169 timer5: timer@40000c00 {
106 compatible = "st,stm32-timer"; 170 compatible = "st,stm32-timer";
107 reg = <0x40000c00 0x400>; 171 reg = <0x40000c00 0x400>;
108 interrupts = <50>; 172 interrupts = <50>;
109 clocks = <&rcc 0 131>; 173 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
174 };
175
176 timers5: timers@40000c00 {
177 #address-cells = <1>;
178 #size-cells = <0>;
179 compatible = "st,stm32-timers";
180 reg = <0x40000C00 0x400>;
181 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
182 clock-names = "int";
183 status = "disabled";
184
185 pwm {
186 compatible = "st,stm32-pwm";
187 status = "disabled";
188 };
189
190 timer@4 {
191 compatible = "st,stm32-timer-trigger";
192 reg = <4>;
193 status = "disabled";
194 };
110 }; 195 };
111 196
112 timer6: timer@40001000 { 197 timer6: timer@40001000 {
113 compatible = "st,stm32-timer"; 198 compatible = "st,stm32-timer";
114 reg = <0x40001000 0x400>; 199 reg = <0x40001000 0x400>;
115 interrupts = <54>; 200 interrupts = <54>;
116 clocks = <&rcc 0 132>; 201 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
202 status = "disabled";
203 };
204
205 timers6: timers@40001000 {
206 #address-cells = <1>;
207 #size-cells = <0>;
208 compatible = "st,stm32-timers";
209 reg = <0x40001000 0x400>;
210 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
211 clock-names = "int";
117 status = "disabled"; 212 status = "disabled";
213
214 timer@5 {
215 compatible = "st,stm32-timer-trigger";
216 reg = <5>;
217 status = "disabled";
218 };
118 }; 219 };
119 220
120 timer7: timer@40001400 { 221 timer7: timer@40001400 {
121 compatible = "st,stm32-timer"; 222 compatible = "st,stm32-timer";
122 reg = <0x40001400 0x400>; 223 reg = <0x40001400 0x400>;
123 interrupts = <55>; 224 interrupts = <55>;
124 clocks = <&rcc 0 133>; 225 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
226 status = "disabled";
227 };
228
229 timers7: timers@40001400 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "st,stm32-timers";
233 reg = <0x40001400 0x400>;
234 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
235 clock-names = "int";
236 status = "disabled";
237
238 timer@6 {
239 compatible = "st,stm32-timer-trigger";
240 reg = <6>;
241 status = "disabled";
242 };
243 };
244
245 timers12: timers@40001800 {
246 #address-cells = <1>;
247 #size-cells = <0>;
248 compatible = "st,stm32-timers";
249 reg = <0x40001800 0x400>;
250 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
251 clock-names = "int";
252 status = "disabled";
253
254 pwm {
255 compatible = "st,stm32-pwm";
256 status = "disabled";
257 };
258
259 timer@11 {
260 compatible = "st,stm32-timer-trigger";
261 reg = <11>;
262 status = "disabled";
263 };
264 };
265
266 timers13: timers@40001c00 {
267 #address-cells = <1>;
268 #size-cells = <0>;
269 compatible = "st,stm32-timers";
270 reg = <0x40001C00 0x400>;
271 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
272 clock-names = "int";
273 status = "disabled";
274
275 pwm {
276 compatible = "st,stm32-pwm";
277 status = "disabled";
278 };
279 };
280
281 timers14: timers@40002000 {
282 #address-cells = <1>;
283 #size-cells = <0>;
284 compatible = "st,stm32-timers";
285 reg = <0x40002000 0x400>;
286 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
287 clock-names = "int";
125 status = "disabled"; 288 status = "disabled";
289
290 pwm {
291 compatible = "st,stm32-pwm";
292 status = "disabled";
293 };
126 }; 294 };
127 295
128 rtc: rtc@40002800 { 296 rtc: rtc@40002800 {
@@ -143,7 +311,7 @@
143 compatible = "st,stm32-usart", "st,stm32-uart"; 311 compatible = "st,stm32-usart", "st,stm32-uart";
144 reg = <0x40004400 0x400>; 312 reg = <0x40004400 0x400>;
145 interrupts = <38>; 313 interrupts = <38>;
146 clocks = <&rcc 0 145>; 314 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
147 status = "disabled"; 315 status = "disabled";
148 }; 316 };
149 317
@@ -151,7 +319,7 @@
151 compatible = "st,stm32-usart", "st,stm32-uart"; 319 compatible = "st,stm32-usart", "st,stm32-uart";
152 reg = <0x40004800 0x400>; 320 reg = <0x40004800 0x400>;
153 interrupts = <39>; 321 interrupts = <39>;
154 clocks = <&rcc 0 146>; 322 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
155 status = "disabled"; 323 status = "disabled";
156 dmas = <&dma1 1 4 0x400 0x0>, 324 dmas = <&dma1 1 4 0x400 0x0>,
157 <&dma1 3 4 0x400 0x0>; 325 <&dma1 3 4 0x400 0x0>;
@@ -162,7 +330,7 @@
162 compatible = "st,stm32-uart"; 330 compatible = "st,stm32-uart";
163 reg = <0x40004c00 0x400>; 331 reg = <0x40004c00 0x400>;
164 interrupts = <52>; 332 interrupts = <52>;
165 clocks = <&rcc 0 147>; 333 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
166 status = "disabled"; 334 status = "disabled";
167 }; 335 };
168 336
@@ -170,7 +338,19 @@
170 compatible = "st,stm32-uart"; 338 compatible = "st,stm32-uart";
171 reg = <0x40005000 0x400>; 339 reg = <0x40005000 0x400>;
172 interrupts = <53>; 340 interrupts = <53>;
173 clocks = <&rcc 0 148>; 341 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
342 status = "disabled";
343 };
344
345 i2c1: i2c@40005400 {
346 compatible = "st,stm32f4-i2c";
347 reg = <0x40005400 0x400>;
348 interrupts = <31>,
349 <32>;
350 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
351 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
352 #address-cells = <1>;
353 #size-cells = <0>;
174 status = "disabled"; 354 status = "disabled";
175 }; 355 };
176 356
@@ -178,7 +358,7 @@
178 compatible = "st,stm32-usart", "st,stm32-uart"; 358 compatible = "st,stm32-usart", "st,stm32-uart";
179 reg = <0x40007800 0x400>; 359 reg = <0x40007800 0x400>;
180 interrupts = <82>; 360 interrupts = <82>;
181 clocks = <&rcc 0 158>; 361 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
182 status = "disabled"; 362 status = "disabled";
183 }; 363 };
184 364
@@ -186,15 +366,57 @@
186 compatible = "st,stm32-usart", "st,stm32-uart"; 366 compatible = "st,stm32-usart", "st,stm32-uart";
187 reg = <0x40007c00 0x400>; 367 reg = <0x40007c00 0x400>;
188 interrupts = <83>; 368 interrupts = <83>;
189 clocks = <&rcc 0 159>; 369 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
370 status = "disabled";
371 };
372
373 timers1: timers@40010000 {
374 #address-cells = <1>;
375 #size-cells = <0>;
376 compatible = "st,stm32-timers";
377 reg = <0x40010000 0x400>;
378 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
379 clock-names = "int";
380 status = "disabled";
381
382 pwm {
383 compatible = "st,stm32-pwm";
384 status = "disabled";
385 };
386
387 timer@0 {
388 compatible = "st,stm32-timer-trigger";
389 reg = <0>;
390 status = "disabled";
391 };
392 };
393
394 timers8: timers@40010400 {
395 #address-cells = <1>;
396 #size-cells = <0>;
397 compatible = "st,stm32-timers";
398 reg = <0x40010400 0x400>;
399 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
400 clock-names = "int";
190 status = "disabled"; 401 status = "disabled";
402
403 pwm {
404 compatible = "st,stm32-pwm";
405 status = "disabled";
406 };
407
408 timer@7 {
409 compatible = "st,stm32-timer-trigger";
410 reg = <7>;
411 status = "disabled";
412 };
191 }; 413 };
192 414
193 usart1: serial@40011000 { 415 usart1: serial@40011000 {
194 compatible = "st,stm32-usart", "st,stm32-uart"; 416 compatible = "st,stm32-usart", "st,stm32-uart";
195 reg = <0x40011000 0x400>; 417 reg = <0x40011000 0x400>;
196 interrupts = <37>; 418 interrupts = <37>;
197 clocks = <&rcc 0 164>; 419 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
198 status = "disabled"; 420 status = "disabled";
199 dmas = <&dma2 2 4 0x400 0x0>, 421 dmas = <&dma2 2 4 0x400 0x0>,
200 <&dma2 7 4 0x400 0x0>; 422 <&dma2 7 4 0x400 0x0>;
@@ -205,7 +427,7 @@
205 compatible = "st,stm32-usart", "st,stm32-uart"; 427 compatible = "st,stm32-usart", "st,stm32-uart";
206 reg = <0x40011400 0x400>; 428 reg = <0x40011400 0x400>;
207 interrupts = <71>; 429 interrupts = <71>;
208 clocks = <&rcc 0 165>; 430 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
209 status = "disabled"; 431 status = "disabled";
210 }; 432 };
211 433
@@ -213,7 +435,7 @@
213 compatible = "st,stm32f4-adc-core"; 435 compatible = "st,stm32f4-adc-core";
214 reg = <0x40012000 0x400>; 436 reg = <0x40012000 0x400>;
215 interrupts = <18>; 437 interrupts = <18>;
216 clocks = <&rcc 0 168>; 438 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
217 clock-names = "adc"; 439 clock-names = "adc";
218 interrupt-controller; 440 interrupt-controller;
219 #interrupt-cells = <1>; 441 #interrupt-cells = <1>;
@@ -225,7 +447,7 @@
225 compatible = "st,stm32f4-adc"; 447 compatible = "st,stm32f4-adc";
226 #io-channel-cells = <1>; 448 #io-channel-cells = <1>;
227 reg = <0x0>; 449 reg = <0x0>;
228 clocks = <&rcc 0 168>; 450 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
229 interrupt-parent = <&adc>; 451 interrupt-parent = <&adc>;
230 interrupts = <0>; 452 interrupts = <0>;
231 status = "disabled"; 453 status = "disabled";
@@ -235,7 +457,7 @@
235 compatible = "st,stm32f4-adc"; 457 compatible = "st,stm32f4-adc";
236 #io-channel-cells = <1>; 458 #io-channel-cells = <1>;
237 reg = <0x100>; 459 reg = <0x100>;
238 clocks = <&rcc 0 169>; 460 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
239 interrupt-parent = <&adc>; 461 interrupt-parent = <&adc>;
240 interrupts = <1>; 462 interrupts = <1>;
241 status = "disabled"; 463 status = "disabled";
@@ -245,7 +467,7 @@
245 compatible = "st,stm32f4-adc"; 467 compatible = "st,stm32f4-adc";
246 #io-channel-cells = <1>; 468 #io-channel-cells = <1>;
247 reg = <0x200>; 469 reg = <0x200>;
248 clocks = <&rcc 0 170>; 470 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
249 interrupt-parent = <&adc>; 471 interrupt-parent = <&adc>;
250 interrupts = <2>; 472 interrupts = <2>;
251 status = "disabled"; 473 status = "disabled";
@@ -265,6 +487,57 @@
265 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; 487 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
266 }; 488 };
267 489
490 timers9: timers@40014000 {
491 #address-cells = <1>;
492 #size-cells = <0>;
493 compatible = "st,stm32-timers";
494 reg = <0x40014000 0x400>;
495 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
496 clock-names = "int";
497 status = "disabled";
498
499 pwm {
500 compatible = "st,stm32-pwm";
501 status = "disabled";
502 };
503
504 timer@8 {
505 compatible = "st,stm32-timer-trigger";
506 reg = <8>;
507 status = "disabled";
508 };
509 };
510
511 timers10: timers@40014400 {
512 #address-cells = <1>;
513 #size-cells = <0>;
514 compatible = "st,stm32-timers";
515 reg = <0x40014400 0x400>;
516 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
517 clock-names = "int";
518 status = "disabled";
519
520 pwm {
521 compatible = "st,stm32-pwm";
522 status = "disabled";
523 };
524 };
525
526 timers11: timers@40014800 {
527 #address-cells = <1>;
528 #size-cells = <0>;
529 compatible = "st,stm32-timers";
530 reg = <0x40014800 0x400>;
531 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
532 clock-names = "int";
533 status = "disabled";
534
535 pwm {
536 compatible = "st,stm32-pwm";
537 status = "disabled";
538 };
539 };
540
268 pwrcfg: power-config@40007000 { 541 pwrcfg: power-config@40007000 {
269 compatible = "syscon"; 542 compatible = "syscon";
270 reg = <0x40007000 0x400>; 543 reg = <0x40007000 0x400>;
@@ -283,7 +556,7 @@
283 gpio-controller; 556 gpio-controller;
284 #gpio-cells = <2>; 557 #gpio-cells = <2>;
285 reg = <0x0 0x400>; 558 reg = <0x0 0x400>;
286 clocks = <&rcc 0 0>; 559 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
287 st,bank-name = "GPIOA"; 560 st,bank-name = "GPIOA";
288 }; 561 };
289 562
@@ -291,7 +564,7 @@
291 gpio-controller; 564 gpio-controller;
292 #gpio-cells = <2>; 565 #gpio-cells = <2>;
293 reg = <0x400 0x400>; 566 reg = <0x400 0x400>;
294 clocks = <&rcc 0 1>; 567 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
295 st,bank-name = "GPIOB"; 568 st,bank-name = "GPIOB";
296 }; 569 };
297 570
@@ -299,7 +572,7 @@
299 gpio-controller; 572 gpio-controller;
300 #gpio-cells = <2>; 573 #gpio-cells = <2>;
301 reg = <0x800 0x400>; 574 reg = <0x800 0x400>;
302 clocks = <&rcc 0 2>; 575 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
303 st,bank-name = "GPIOC"; 576 st,bank-name = "GPIOC";
304 }; 577 };
305 578
@@ -307,7 +580,7 @@
307 gpio-controller; 580 gpio-controller;
308 #gpio-cells = <2>; 581 #gpio-cells = <2>;
309 reg = <0xc00 0x400>; 582 reg = <0xc00 0x400>;
310 clocks = <&rcc 0 3>; 583 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
311 st,bank-name = "GPIOD"; 584 st,bank-name = "GPIOD";
312 }; 585 };
313 586
@@ -315,7 +588,7 @@
315 gpio-controller; 588 gpio-controller;
316 #gpio-cells = <2>; 589 #gpio-cells = <2>;
317 reg = <0x1000 0x400>; 590 reg = <0x1000 0x400>;
318 clocks = <&rcc 0 4>; 591 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
319 st,bank-name = "GPIOE"; 592 st,bank-name = "GPIOE";
320 }; 593 };
321 594
@@ -323,7 +596,7 @@
323 gpio-controller; 596 gpio-controller;
324 #gpio-cells = <2>; 597 #gpio-cells = <2>;
325 reg = <0x1400 0x400>; 598 reg = <0x1400 0x400>;
326 clocks = <&rcc 0 5>; 599 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
327 st,bank-name = "GPIOF"; 600 st,bank-name = "GPIOF";
328 }; 601 };
329 602
@@ -331,7 +604,7 @@
331 gpio-controller; 604 gpio-controller;
332 #gpio-cells = <2>; 605 #gpio-cells = <2>;
333 reg = <0x1800 0x400>; 606 reg = <0x1800 0x400>;
334 clocks = <&rcc 0 6>; 607 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
335 st,bank-name = "GPIOG"; 608 st,bank-name = "GPIOG";
336 }; 609 };
337 610
@@ -339,7 +612,7 @@
339 gpio-controller; 612 gpio-controller;
340 #gpio-cells = <2>; 613 #gpio-cells = <2>;
341 reg = <0x1c00 0x400>; 614 reg = <0x1c00 0x400>;
342 clocks = <&rcc 0 7>; 615 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
343 st,bank-name = "GPIOH"; 616 st,bank-name = "GPIOH";
344 }; 617 };
345 618
@@ -347,7 +620,7 @@
347 gpio-controller; 620 gpio-controller;
348 #gpio-cells = <2>; 621 #gpio-cells = <2>;
349 reg = <0x2000 0x400>; 622 reg = <0x2000 0x400>;
350 clocks = <&rcc 0 8>; 623 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
351 st,bank-name = "GPIOI"; 624 st,bank-name = "GPIOI";
352 }; 625 };
353 626
@@ -355,7 +628,7 @@
355 gpio-controller; 628 gpio-controller;
356 #gpio-cells = <2>; 629 #gpio-cells = <2>;
357 reg = <0x2400 0x400>; 630 reg = <0x2400 0x400>;
358 clocks = <&rcc 0 9>; 631 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
359 st,bank-name = "GPIOJ"; 632 st,bank-name = "GPIOJ";
360 }; 633 };
361 634
@@ -363,7 +636,7 @@
363 gpio-controller; 636 gpio-controller;
364 #gpio-cells = <2>; 637 #gpio-cells = <2>;
365 reg = <0x2800 0x400>; 638 reg = <0x2800 0x400>;
366 clocks = <&rcc 0 10>; 639 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
367 st,bank-name = "GPIOK"; 640 st,bank-name = "GPIOK";
368 }; 641 };
369 642
@@ -438,6 +711,31 @@
438 pinmux = <STM32F429_PF10_FUNC_ANALOG>; 711 pinmux = <STM32F429_PF10_FUNC_ANALOG>;
439 }; 712 };
440 }; 713 };
714
715 pwm1_pins: pwm@1 {
716 pins {
717 pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
718 <STM32F429_PB13_FUNC_TIM1_CH1N>,
719 <STM32F429_PB12_FUNC_TIM1_BKIN>;
720 };
721 };
722
723 pwm3_pins: pwm@3 {
724 pins {
725 pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
726 <STM32F429_PB5_FUNC_TIM3_CH2>;
727 };
728 };
729
730 i2c1_pins: i2c1@0 {
731 pins {
732 pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>,
733 <STM32F429_PB6_FUNC_I2C1_SCL>;
734 bias-disable;
735 drive-open-drain;
736 slew-rate = <3>;
737 };
738 };
441 }; 739 };
442 740
443 rcc: rcc@40023810 { 741 rcc: rcc@40023810 {
@@ -462,7 +760,7 @@
462 <16>, 760 <16>,
463 <17>, 761 <17>,
464 <47>; 762 <47>;
465 clocks = <&rcc 0 21>; 763 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
466 #dma-cells = <4>; 764 #dma-cells = <4>;
467 }; 765 };
468 766
@@ -477,7 +775,7 @@
477 <68>, 775 <68>,
478 <69>, 776 <69>,
479 <70>; 777 <70>;
480 clocks = <&rcc 0 22>; 778 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
481 #dma-cells = <4>; 779 #dma-cells = <4>;
482 st,mem2mem; 780 st,mem2mem;
483 }; 781 };
@@ -489,7 +787,9 @@
489 interrupts = <61>; 787 interrupts = <61>;
490 interrupt-names = "macirq"; 788 interrupt-names = "macirq";
491 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; 789 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
492 clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>; 790 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
791 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
792 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
493 st,syscon = <&syscfg 0x4>; 793 st,syscon = <&syscfg 0x4>;
494 snps,pbl = <8>; 794 snps,pbl = <8>;
495 snps,mixed-burst; 795 snps,mixed-burst;
@@ -500,7 +800,7 @@
500 compatible = "snps,dwc2"; 800 compatible = "snps,dwc2";
501 reg = <0x40040000 0x40000>; 801 reg = <0x40040000 0x40000>;
502 interrupts = <77>; 802 interrupts = <77>;
503 clocks = <&rcc 0 29>; 803 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
504 clock-names = "otg"; 804 clock-names = "otg";
505 status = "disabled"; 805 status = "disabled";
506 }; 806 };
@@ -509,12 +809,13 @@
509 compatible = "st,stm32-rng"; 809 compatible = "st,stm32-rng";
510 reg = <0x50060800 0x400>; 810 reg = <0x50060800 0x400>;
511 interrupts = <80>; 811 interrupts = <80>;
512 clocks = <&rcc 0 38>; 812 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
813
513 }; 814 };
514 }; 815 };
515}; 816};
516 817
517&systick { 818&systick {
518 clocks = <&rcc 1 0>; 819 clocks = <&rcc 1 SYSTICK>;
519 status = "okay"; 820 status = "okay";
520}; 821};
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
index f52b9f6cf566..0dd56ef574fa 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -82,6 +82,34 @@
82 status = "okay"; 82 status = "okay";
83}; 83};
84 84
85&timers1 {
86 status = "okay";
87
88 pwm {
89 pinctrl-0 = <&pwm1_pins>;
90 pinctrl-names = "default";
91 status = "okay";
92 };
93
94 timer@0 {
95 status = "okay";
96 };
97};
98
99&timers3 {
100 status = "okay";
101
102 pwm {
103 pinctrl-0 = <&pwm3_pins>;
104 pinctrl-names = "default";
105 status = "okay";
106 };
107
108 timer@2 {
109 status = "okay";
110 };
111};
112
85&usart3 { 113&usart3 {
86 pinctrl-0 = <&usart3_pins_a>; 114 pinctrl-0 = <&usart3_pins_a>;
87 pinctrl-names = "default"; 115 pinctrl-names = "default";
diff --git a/include/dt-bindings/mfd/stm32f4-rcc.h b/include/dt-bindings/mfd/stm32f4-rcc.h
index e98942dc0d44..082a81c94298 100644
--- a/include/dt-bindings/mfd/stm32f4-rcc.h
+++ b/include/dt-bindings/mfd/stm32f4-rcc.h
@@ -18,14 +18,20 @@
18#define STM32F4_RCC_AHB1_GPIOJ 9 18#define STM32F4_RCC_AHB1_GPIOJ 9
19#define STM32F4_RCC_AHB1_GPIOK 10 19#define STM32F4_RCC_AHB1_GPIOK 10
20#define STM32F4_RCC_AHB1_CRC 12 20#define STM32F4_RCC_AHB1_CRC 12
21#define STM32F4_RCC_AHB1_BKPSRAM 18
22#define STM32F4_RCC_AHB1_CCMDATARAM 20
21#define STM32F4_RCC_AHB1_DMA1 21 23#define STM32F4_RCC_AHB1_DMA1 21
22#define STM32F4_RCC_AHB1_DMA2 22 24#define STM32F4_RCC_AHB1_DMA2 22
23#define STM32F4_RCC_AHB1_DMA2D 23 25#define STM32F4_RCC_AHB1_DMA2D 23
24#define STM32F4_RCC_AHB1_ETHMAC 25 26#define STM32F4_RCC_AHB1_ETHMAC 25
25#define STM32F4_RCC_AHB1_OTGHS 29 27#define STM32F4_RCC_AHB1_ETHMACTX 26
28#define STM32F4_RCC_AHB1_ETHMACRX 27
29#define STM32F4_RCC_AHB1_ETHMACPTP 28
30#define STM32F4_RCC_AHB1_OTGHS 29
31#define STM32F4_RCC_AHB1_OTGHSULPI 30
26 32
27#define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) 33#define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8))
28#define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit + (0x30 * 8)) 34#define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit)
29 35
30 36
31/* AHB2 */ 37/* AHB2 */
@@ -36,13 +42,14 @@
36#define STM32F4_RCC_AHB2_OTGFS 7 42#define STM32F4_RCC_AHB2_OTGFS 7
37 43
38#define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) 44#define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8))
39#define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + (0x34 * 8)) 45#define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20)
40 46
41/* AHB3 */ 47/* AHB3 */
42#define STM32F4_RCC_AHB3_FMC 0 48#define STM32F4_RCC_AHB3_FMC 0
49#define STM32F4_RCC_AHB3_QSPI 1
43 50
44#define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) 51#define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8))
45#define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + (0x38 * 8)) 52#define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40)
46 53
47/* APB1 */ 54/* APB1 */
48#define STM32F4_RCC_APB1_TIM2 0 55#define STM32F4_RCC_APB1_TIM2 0
@@ -72,14 +79,16 @@
72#define STM32F4_RCC_APB1_UART8 31 79#define STM32F4_RCC_APB1_UART8 31
73 80
74#define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) 81#define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8))
75#define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + (0x40 * 8)) 82#define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80)
76 83
77/* APB2 */ 84/* APB2 */
78#define STM32F4_RCC_APB2_TIM1 0 85#define STM32F4_RCC_APB2_TIM1 0
79#define STM32F4_RCC_APB2_TIM8 1 86#define STM32F4_RCC_APB2_TIM8 1
80#define STM32F4_RCC_APB2_USART1 4 87#define STM32F4_RCC_APB2_USART1 4
81#define STM32F4_RCC_APB2_USART6 5 88#define STM32F4_RCC_APB2_USART6 5
82#define STM32F4_RCC_APB2_ADC 8 89#define STM32F4_RCC_APB2_ADC1 8
90#define STM32F4_RCC_APB2_ADC2 9
91#define STM32F4_RCC_APB2_ADC3 10
83#define STM32F4_RCC_APB2_SDIO 11 92#define STM32F4_RCC_APB2_SDIO 11
84#define STM32F4_RCC_APB2_SPI1 12 93#define STM32F4_RCC_APB2_SPI1 12
85#define STM32F4_RCC_APB2_SPI4 13 94#define STM32F4_RCC_APB2_SPI4 13
@@ -91,8 +100,9 @@
91#define STM32F4_RCC_APB2_SPI6 21 100#define STM32F4_RCC_APB2_SPI6 21
92#define STM32F4_RCC_APB2_SAI1 22 101#define STM32F4_RCC_APB2_SAI1 22
93#define STM32F4_RCC_APB2_LTDC 26 102#define STM32F4_RCC_APB2_LTDC 26
103#define STM32F4_RCC_APB2_DSI 27
94 104
95#define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) 105#define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8))
96#define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + (0x44 * 8)) 106#define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0)
97 107
98#endif /* _DT_BINDINGS_MFD_STM32F4_RCC_H */ 108#endif /* _DT_BINDINGS_MFD_STM32F4_RCC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-25 01:40:01 -0400