diff options
author | Heiko Stuebner <heiko@sntech.de> | 2016-02-25 19:58:19 -0500 |
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committer | Heiko Stuebner <heiko@sntech.de> | 2016-02-25 19:58:19 -0500 |
commit | 4b524663a23bc0203f69ef80598e18b393724454 (patch) | |
tree | b3230b19a60a95212c7df6a62bc82ba6dcbefc00 | |
parent | fc6d875ecb83cd03afad4486c97a9355e00c8944 (diff) | |
parent | 2d2671ea4b35454b30a69744ce258489920e4d2b (diff) |
Merge branch 'v4.6-shared/clkids' into v4.6-clk/next
-rw-r--r-- | include/dt-bindings/clock/rk3228-cru.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h index a78dd891e24a..5d43ed9b05ad 100644 --- a/include/dt-bindings/clock/rk3228-cru.h +++ b/include/dt-bindings/clock/rk3228-cru.h | |||
@@ -29,6 +29,7 @@ | |||
29 | #define SCLK_SDMMC 68 | 29 | #define SCLK_SDMMC 68 |
30 | #define SCLK_SDIO 69 | 30 | #define SCLK_SDIO 69 |
31 | #define SCLK_EMMC 71 | 31 | #define SCLK_EMMC 71 |
32 | #define SCLK_TSADC 72 | ||
32 | #define SCLK_UART0 77 | 33 | #define SCLK_UART0 77 |
33 | #define SCLK_UART1 78 | 34 | #define SCLK_UART1 78 |
34 | #define SCLK_UART2 79 | 35 | #define SCLK_UART2 79 |
@@ -49,10 +50,17 @@ | |||
49 | #define SCLK_SDMMC_SAMPLE 118 | 50 | #define SCLK_SDMMC_SAMPLE 118 |
50 | #define SCLK_SDIO_SAMPLE 119 | 51 | #define SCLK_SDIO_SAMPLE 119 |
51 | #define SCLK_EMMC_SAMPLE 121 | 52 | #define SCLK_EMMC_SAMPLE 121 |
53 | #define SCLK_VOP 122 | ||
54 | #define SCLK_HDMI_HDCP 123 | ||
55 | |||
56 | /* dclk gates */ | ||
57 | #define DCLK_VOP 190 | ||
58 | #define DCLK_HDMI_PHY 191 | ||
52 | 59 | ||
53 | /* aclk gates */ | 60 | /* aclk gates */ |
54 | #define ACLK_DMAC 194 | 61 | #define ACLK_DMAC 194 |
55 | #define ACLK_PERI 210 | 62 | #define ACLK_PERI 210 |
63 | #define ACLK_VOP 211 | ||
56 | 64 | ||
57 | /* pclk gates */ | 65 | /* pclk gates */ |
58 | #define PCLK_GPIO0 320 | 66 | #define PCLK_GPIO0 320 |
@@ -68,11 +76,15 @@ | |||
68 | #define PCLK_UART0 341 | 76 | #define PCLK_UART0 341 |
69 | #define PCLK_UART1 342 | 77 | #define PCLK_UART1 342 |
70 | #define PCLK_UART2 343 | 78 | #define PCLK_UART2 343 |
79 | #define PCLK_TSADC 344 | ||
71 | #define PCLK_PWM 350 | 80 | #define PCLK_PWM 350 |
72 | #define PCLK_TIMER 353 | 81 | #define PCLK_TIMER 353 |
73 | #define PCLK_PERI 363 | 82 | #define PCLK_PERI 363 |
83 | #define PCLK_HDMI_CTRL 364 | ||
84 | #define PCLK_HDMI_PHY 365 | ||
74 | 85 | ||
75 | /* hclk gates */ | 86 | /* hclk gates */ |
87 | #define HCLK_VOP 452 | ||
76 | #define HCLK_NANDC 453 | 88 | #define HCLK_NANDC 453 |
77 | #define HCLK_SDMMC 456 | 89 | #define HCLK_SDMMC 456 |
78 | #define HCLK_SDIO 457 | 90 | #define HCLK_SDIO 457 |