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authorOlof Johansson <olof@lixom.net>2015-04-03 17:54:13 -0400
committerOlof Johansson <olof@lixom.net>2015-04-03 17:54:13 -0400
commit4b3be93dd095af7488b0aee6e53c0e74a6130303 (patch)
tree4dec2a7be6baeea03b9fc3c2c5ec4ef2a05d63a3
parentccca5d7d0844f9d97a985dc159056cf6d2e5d9eb (diff)
parent292a3546b9eb20bf5a292f4e55dd1a027424669f (diff)
Merge tag 'mvebu-dt-4.1-3' of git://git.infradead.org/linux-mvebu into next/dt
Merge "ARM: mvebu: dt changes for v4.1 (round 3)" from Gregory Clement: mvebu dt changes for v4.1 (part #3) These changes have no influence on the kernel behavior (except removing a warning message), but they allow to have a better representation of the hardware. - conform L2CC node with ePAPR specification by adding cache-level - remove cpuclk resources overlapping coredivclk registers on Armada XP * tag 'mvebu-dt-4.1-3' of git://git.infradead.org/linux-mvebu: ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level ARM: mvebu: clk: remove cpuclk resources overlapping coredivclk registers on Armada XP Signed-off-by: Olof Johansson <olof@lixom.net>
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi1
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi3
2 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 50f259b20f94..00b50db57c9c 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -129,6 +129,7 @@
129 compatible = "marvell,aurora-outer-cache"; 129 compatible = "marvell,aurora-outer-cache";
130 reg = <0x08000 0x1000>; 130 reg = <0x08000 0x1000>;
131 cache-id-part = <0x100>; 131 cache-id-part = <0x100>;
132 cache-level = <2>;
132 cache-unified; 133 cache-unified;
133 wt-override; 134 wt-override;
134 }; 135 };
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index ff47345e19ed..013d63f69e36 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -79,6 +79,7 @@
79 compatible = "marvell,aurora-system-cache"; 79 compatible = "marvell,aurora-system-cache";
80 reg = <0x08000 0x1000>; 80 reg = <0x08000 0x1000>;
81 cache-id-part = <0x100>; 81 cache-id-part = <0x100>;
82 cache-level = <2>;
82 cache-unified; 83 cache-unified;
83 wt-override; 84 wt-override;
84 }; 85 };
@@ -150,7 +151,7 @@
150 cpuclk: clock-complex@18700 { 151 cpuclk: clock-complex@18700 {
151 #clock-cells = <1>; 152 #clock-cells = <1>;
152 compatible = "marvell,armada-xp-cpu-clock"; 153 compatible = "marvell,armada-xp-cpu-clock";
153 reg = <0x18700 0xA0>, <0x1c054 0x10>; 154 reg = <0x18700 0x24>, <0x1c054 0x10>;
154 clocks = <&coreclk 1>; 155 clocks = <&coreclk 1>;
155 }; 156 };
156 157