diff options
| author | Xiong Zhang <xiong.y.zhang@intel.com> | 2019-04-10 00:16:34 -0400 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2019-04-25 03:29:38 -0400 |
| commit | 4a6eccbcb9ea88cf0408115e9d130ce7062ee6fd (patch) | |
| tree | a19abd7c66ea84c0eb513e98a91c9dfa813f9ebd | |
| parent | 447811a686e8da7325516a78069ccfbd139ef1a7 (diff) | |
drm/i915/gvt: Change fb_info->size from pages to bytes
fb_info->size is in pages, but some function need bytes when it
is as a parameter. Such as:
a. intel_gvt_ggtt_validate_range(), according to function definition
b. vifio_device_gfx_plane_info->size, according to the comment of
its definition
So change fb_info->size into bytes.
v2: Keep fb_info->size in real size instead of assinging casted page
size(zhenyu)
v3: obj->size should be page aligned and delete redundant check(zhenyu)
Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>
Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/dmabuf.c | 17 |
1 files changed, 6 insertions, 11 deletions
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c index 4e1e425189ba..c104f041d0f4 100644 --- a/drivers/gpu/drm/i915/gvt/dmabuf.c +++ b/drivers/gpu/drm/i915/gvt/dmabuf.c | |||
| @@ -45,6 +45,7 @@ static int vgpu_gem_get_pages( | |||
| 45 | int i, ret; | 45 | int i, ret; |
| 46 | gen8_pte_t __iomem *gtt_entries; | 46 | gen8_pte_t __iomem *gtt_entries; |
| 47 | struct intel_vgpu_fb_info *fb_info; | 47 | struct intel_vgpu_fb_info *fb_info; |
| 48 | u32 page_num; | ||
| 48 | 49 | ||
| 49 | fb_info = (struct intel_vgpu_fb_info *)obj->gvt_info; | 50 | fb_info = (struct intel_vgpu_fb_info *)obj->gvt_info; |
| 50 | if (WARN_ON(!fb_info)) | 51 | if (WARN_ON(!fb_info)) |
| @@ -54,14 +55,15 @@ static int vgpu_gem_get_pages( | |||
| 54 | if (unlikely(!st)) | 55 | if (unlikely(!st)) |
| 55 | return -ENOMEM; | 56 | return -ENOMEM; |
| 56 | 57 | ||
| 57 | ret = sg_alloc_table(st, fb_info->size, GFP_KERNEL); | 58 | page_num = obj->base.size >> PAGE_SHIFT; |
| 59 | ret = sg_alloc_table(st, page_num, GFP_KERNEL); | ||
| 58 | if (ret) { | 60 | if (ret) { |
| 59 | kfree(st); | 61 | kfree(st); |
| 60 | return ret; | 62 | return ret; |
| 61 | } | 63 | } |
| 62 | gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + | 64 | gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + |
| 63 | (fb_info->start >> PAGE_SHIFT); | 65 | (fb_info->start >> PAGE_SHIFT); |
| 64 | for_each_sg(st->sgl, sg, fb_info->size, i) { | 66 | for_each_sg(st->sgl, sg, page_num, i) { |
| 65 | sg->offset = 0; | 67 | sg->offset = 0; |
| 66 | sg->length = PAGE_SIZE; | 68 | sg->length = PAGE_SIZE; |
| 67 | sg_dma_address(sg) = | 69 | sg_dma_address(sg) = |
| @@ -158,7 +160,7 @@ static struct drm_i915_gem_object *vgpu_create_gem(struct drm_device *dev, | |||
| 158 | return NULL; | 160 | return NULL; |
| 159 | 161 | ||
| 160 | drm_gem_private_object_init(dev, &obj->base, | 162 | drm_gem_private_object_init(dev, &obj->base, |
| 161 | info->size << PAGE_SHIFT); | 163 | roundup(info->size, PAGE_SIZE)); |
| 162 | i915_gem_object_init(obj, &intel_vgpu_gem_ops); | 164 | i915_gem_object_init(obj, &intel_vgpu_gem_ops); |
| 163 | 165 | ||
| 164 | obj->read_domains = I915_GEM_DOMAIN_GTT; | 166 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
| @@ -206,7 +208,6 @@ static int vgpu_get_plane_info(struct drm_device *dev, | |||
| 206 | struct intel_vgpu_fb_info *info, | 208 | struct intel_vgpu_fb_info *info, |
| 207 | int plane_id) | 209 | int plane_id) |
| 208 | { | 210 | { |
| 209 | struct drm_i915_private *dev_priv = to_i915(dev); | ||
| 210 | struct intel_vgpu_primary_plane_format p; | 211 | struct intel_vgpu_primary_plane_format p; |
| 211 | struct intel_vgpu_cursor_plane_format c; | 212 | struct intel_vgpu_cursor_plane_format c; |
| 212 | int ret, tile_height = 1; | 213 | int ret, tile_height = 1; |
| @@ -267,8 +268,7 @@ static int vgpu_get_plane_info(struct drm_device *dev, | |||
| 267 | return -EINVAL; | 268 | return -EINVAL; |
| 268 | } | 269 | } |
| 269 | 270 | ||
| 270 | info->size = (info->stride * roundup(info->height, tile_height) | 271 | info->size = info->stride * roundup(info->height, tile_height); |
| 271 | + PAGE_SIZE - 1) >> PAGE_SHIFT; | ||
| 272 | if (info->size == 0) { | 272 | if (info->size == 0) { |
| 273 | gvt_vgpu_err("fb size is zero\n"); | 273 | gvt_vgpu_err("fb size is zero\n"); |
| 274 | return -EINVAL; | 274 | return -EINVAL; |
| @@ -278,11 +278,6 @@ static int vgpu_get_plane_info(struct drm_device *dev, | |||
| 278 | gvt_vgpu_err("Not aligned fb address:0x%llx\n", info->start); | 278 | gvt_vgpu_err("Not aligned fb address:0x%llx\n", info->start); |
| 279 | return -EFAULT; | 279 | return -EFAULT; |
| 280 | } | 280 | } |
| 281 | if (((info->start >> PAGE_SHIFT) + info->size) > | ||
| 282 | ggtt_total_entries(&dev_priv->ggtt)) { | ||
| 283 | gvt_vgpu_err("Invalid GTT offset or size\n"); | ||
| 284 | return -EFAULT; | ||
| 285 | } | ||
| 286 | 281 | ||
| 287 | if (!intel_gvt_ggtt_validate_range(vgpu, info->start, info->size)) { | 282 | if (!intel_gvt_ggtt_validate_range(vgpu, info->start, info->size)) { |
| 288 | gvt_vgpu_err("invalid gma addr\n"); | 283 | gvt_vgpu_err("invalid gma addr\n"); |
