Merge tag 'gic-fixes-4.5-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent

Pull GIC fixes from Marc for 4.5-rc4:

- Two fixes addressing cascaded GICv1/GICv2 (affinity setting, EOImode)
- One fix addressing possible missed interrupts on GICv3

2 files changed, 7 insertions, 7 deletions

diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index 2731d3b25ed2..8ec88e5b290f 100644
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -103,6 +103,7 @@ static inline u64 gic_read_iar_common(void)
         u64 irqstat;
 
         asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
+        dsb(sy);
         return irqstat;
 }
 
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 911758c056c1..8f9ebf714e2b 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -384,9 +384,6 @@ static struct irq_chip gic_chip = {
         .irq_unmask             = gic_unmask_irq,
         .irq_eoi                = gic_eoi_irq,
         .irq_set_type           = gic_set_type,
-#ifdef CONFIG_SMP
-        .irq_set_affinity       = gic_set_affinity,
-#endif
         .irq_get_irqchip_state  = gic_irq_get_irqchip_state,
         .irq_set_irqchip_state  = gic_irq_set_irqchip_state,
         .flags                  = IRQCHIP_SET_TYPE_MASKED |
@@ -400,9 +397,6 @@ static struct irq_chip gic_eoimode1_chip = {
         .irq_unmask             = gic_unmask_irq,
         .irq_eoi                = gic_eoimode1_eoi_irq,
         .irq_set_type           = gic_set_type,
-#ifdef CONFIG_SMP
-        .irq_set_affinity       = gic_set_affinity,
-#endif
         .irq_get_irqchip_state  = gic_irq_get_irqchip_state,
         .irq_set_irqchip_state  = gic_irq_set_irqchip_state,
         .irq_set_vcpu_affinity  = gic_irq_set_vcpu_affinity,
@@ -443,7 +437,7 @@ static void gic_cpu_if_up(struct gic_chip_data *gic)
         u32 bypass = 0;
         u32 mode = 0;
 
-        if (static_key_true(&supports_deactivate))
+        if (gic == &gic_data[0] && static_key_true(&supports_deactivate))
                 mode = GIC_CPU_CTRL_EOImodeNS;
 
         /*
@@ -1039,6 +1033,11 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
                 gic->chip.name = kasprintf(GFP_KERNEL, "GIC-%d", gic_nr);
         }
 
+#ifdef CONFIG_SMP
+        if (gic_nr == 0)
+                gic->chip.irq_set_affinity = gic_set_affinity;
+#endif
+
 #ifdef CONFIG_GIC_NON_BANKED
         if (percpu_offset) { /* Frankein-GIC without banked registers... */
                 unsigned int cpu;