diff options
author | Jiri Pirko <jiri@mellanox.com> | 2016-04-08 13:11:24 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2016-04-08 15:38:43 -0400 |
commit | 497e8592c6d22772d0ad100c1f08e601dc417ed5 (patch) | |
tree | 2d43bb4d02f9a24008e947fd021370c0635f9260 | |
parent | b2f10571b96414986f7293b06847d202f2d1d0ca (diff) |
mlxsw: reg: Share direction enum between SBPR, SBCM, SBPM
Same field, same values, so share the same enum.
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Reviewed-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | drivers/net/ethernet/mellanox/mlxsw/reg.h | 23 | ||||
-rw-r--r-- | drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c | 20 |
2 files changed, 17 insertions, 26 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index 28f5b99e585a..19bdc826e3cd 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h | |||
@@ -3476,9 +3476,10 @@ static const struct mlxsw_reg_info mlxsw_reg_sbpr = { | |||
3476 | .len = MLXSW_REG_SBPR_LEN, | 3476 | .len = MLXSW_REG_SBPR_LEN, |
3477 | }; | 3477 | }; |
3478 | 3478 | ||
3479 | enum mlxsw_reg_sbpr_dir { | 3479 | /* shared direstion enum for SBPR, SBCM, SBPM */ |
3480 | MLXSW_REG_SBPR_DIR_INGRESS, | 3480 | enum mlxsw_reg_sbxx_dir { |
3481 | MLXSW_REG_SBPR_DIR_EGRESS, | 3481 | MLXSW_REG_SBXX_DIR_INGRESS, |
3482 | MLXSW_REG_SBXX_DIR_EGRESS, | ||
3482 | }; | 3483 | }; |
3483 | 3484 | ||
3484 | /* reg_sbpr_dir | 3485 | /* reg_sbpr_dir |
@@ -3511,7 +3512,7 @@ enum mlxsw_reg_sbpr_mode { | |||
3511 | MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); | 3512 | MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); |
3512 | 3513 | ||
3513 | static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, | 3514 | static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, |
3514 | enum mlxsw_reg_sbpr_dir dir, | 3515 | enum mlxsw_reg_sbxx_dir dir, |
3515 | enum mlxsw_reg_sbpr_mode mode, u32 size) | 3516 | enum mlxsw_reg_sbpr_mode mode, u32 size) |
3516 | { | 3517 | { |
3517 | MLXSW_REG_ZERO(sbpr, payload); | 3518 | MLXSW_REG_ZERO(sbpr, payload); |
@@ -3553,11 +3554,6 @@ MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); | |||
3553 | */ | 3554 | */ |
3554 | MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); | 3555 | MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); |
3555 | 3556 | ||
3556 | enum mlxsw_reg_sbcm_dir { | ||
3557 | MLXSW_REG_SBCM_DIR_INGRESS, | ||
3558 | MLXSW_REG_SBCM_DIR_EGRESS, | ||
3559 | }; | ||
3560 | |||
3561 | /* reg_sbcm_dir | 3557 | /* reg_sbcm_dir |
3562 | * Direction. | 3558 | * Direction. |
3563 | * Access: Index | 3559 | * Access: Index |
@@ -3590,7 +3586,7 @@ MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); | |||
3590 | MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); | 3586 | MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); |
3591 | 3587 | ||
3592 | static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, | 3588 | static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, |
3593 | enum mlxsw_reg_sbcm_dir dir, | 3589 | enum mlxsw_reg_sbxx_dir dir, |
3594 | u32 min_buff, u32 max_buff, u8 pool) | 3590 | u32 min_buff, u32 max_buff, u8 pool) |
3595 | { | 3591 | { |
3596 | MLXSW_REG_ZERO(sbcm, payload); | 3592 | MLXSW_REG_ZERO(sbcm, payload); |
@@ -3630,11 +3626,6 @@ MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); | |||
3630 | */ | 3626 | */ |
3631 | MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); | 3627 | MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); |
3632 | 3628 | ||
3633 | enum mlxsw_reg_sbpm_dir { | ||
3634 | MLXSW_REG_SBPM_DIR_INGRESS, | ||
3635 | MLXSW_REG_SBPM_DIR_EGRESS, | ||
3636 | }; | ||
3637 | |||
3638 | /* reg_sbpm_dir | 3629 | /* reg_sbpm_dir |
3639 | * Direction. | 3630 | * Direction. |
3640 | * Access: Index | 3631 | * Access: Index |
@@ -3661,7 +3652,7 @@ MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); | |||
3661 | MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); | 3652 | MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); |
3662 | 3653 | ||
3663 | static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, | 3654 | static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, |
3664 | enum mlxsw_reg_sbpm_dir dir, | 3655 | enum mlxsw_reg_sbxx_dir dir, |
3665 | u32 min_buff, u32 max_buff) | 3656 | u32 min_buff, u32 max_buff) |
3666 | { | 3657 | { |
3667 | MLXSW_REG_ZERO(sbpm, payload); | 3658 | MLXSW_REG_ZERO(sbpm, payload); |
diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c index 97c8d537be5b..f58b1d3a619a 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c | |||
@@ -110,7 +110,7 @@ static int mlxsw_sp_port_headroom_init(struct mlxsw_sp_port *mlxsw_sp_port) | |||
110 | 110 | ||
111 | struct mlxsw_sp_sb_pool { | 111 | struct mlxsw_sp_sb_pool { |
112 | u8 pool; | 112 | u8 pool; |
113 | enum mlxsw_reg_sbpr_dir dir; | 113 | enum mlxsw_reg_sbxx_dir dir; |
114 | enum mlxsw_reg_sbpr_mode mode; | 114 | enum mlxsw_reg_sbpr_mode mode; |
115 | u32 size; | 115 | u32 size; |
116 | }; | 116 | }; |
@@ -129,11 +129,11 @@ struct mlxsw_sp_sb_pool { | |||
129 | } | 129 | } |
130 | 130 | ||
131 | #define MLXSW_SP_SB_POOL_INGRESS(_pool, _size) \ | 131 | #define MLXSW_SP_SB_POOL_INGRESS(_pool, _size) \ |
132 | MLXSW_SP_SB_POOL(_pool, MLXSW_REG_SBPR_DIR_INGRESS, \ | 132 | MLXSW_SP_SB_POOL(_pool, MLXSW_REG_SBXX_DIR_INGRESS, \ |
133 | MLXSW_REG_SBPR_MODE_DYNAMIC, _size) | 133 | MLXSW_REG_SBPR_MODE_DYNAMIC, _size) |
134 | 134 | ||
135 | #define MLXSW_SP_SB_POOL_EGRESS(_pool, _size) \ | 135 | #define MLXSW_SP_SB_POOL_EGRESS(_pool, _size) \ |
136 | MLXSW_SP_SB_POOL(_pool, MLXSW_REG_SBPR_DIR_EGRESS, \ | 136 | MLXSW_SP_SB_POOL(_pool, MLXSW_REG_SBXX_DIR_EGRESS, \ |
137 | MLXSW_REG_SBPR_MODE_DYNAMIC, _size) | 137 | MLXSW_REG_SBPR_MODE_DYNAMIC, _size) |
138 | 138 | ||
139 | static const struct mlxsw_sp_sb_pool mlxsw_sp_sb_pools[] = { | 139 | static const struct mlxsw_sp_sb_pool mlxsw_sp_sb_pools[] = { |
@@ -173,7 +173,7 @@ struct mlxsw_sp_sb_cm { | |||
173 | u8 pg; | 173 | u8 pg; |
174 | u8 tc; | 174 | u8 tc; |
175 | } u; | 175 | } u; |
176 | enum mlxsw_reg_sbcm_dir dir; | 176 | enum mlxsw_reg_sbxx_dir dir; |
177 | u32 min_buff; | 177 | u32 min_buff; |
178 | u32 max_buff; | 178 | u32 max_buff; |
179 | u8 pool; | 179 | u8 pool; |
@@ -189,15 +189,15 @@ struct mlxsw_sp_sb_cm { | |||
189 | } | 189 | } |
190 | 190 | ||
191 | #define MLXSW_SP_SB_CM_INGRESS(_pg, _min_buff, _max_buff) \ | 191 | #define MLXSW_SP_SB_CM_INGRESS(_pg, _min_buff, _max_buff) \ |
192 | MLXSW_SP_SB_CM(_pg, MLXSW_REG_SBCM_DIR_INGRESS, \ | 192 | MLXSW_SP_SB_CM(_pg, MLXSW_REG_SBXX_DIR_INGRESS, \ |
193 | _min_buff, _max_buff, 0) | 193 | _min_buff, _max_buff, 0) |
194 | 194 | ||
195 | #define MLXSW_SP_SB_CM_EGRESS(_tc, _min_buff, _max_buff) \ | 195 | #define MLXSW_SP_SB_CM_EGRESS(_tc, _min_buff, _max_buff) \ |
196 | MLXSW_SP_SB_CM(_tc, MLXSW_REG_SBCM_DIR_EGRESS, \ | 196 | MLXSW_SP_SB_CM(_tc, MLXSW_REG_SBXX_DIR_EGRESS, \ |
197 | _min_buff, _max_buff, 0) | 197 | _min_buff, _max_buff, 0) |
198 | 198 | ||
199 | #define MLXSW_SP_CPU_PORT_SB_CM_EGRESS(_tc) \ | 199 | #define MLXSW_SP_CPU_PORT_SB_CM_EGRESS(_tc) \ |
200 | MLXSW_SP_SB_CM(_tc, MLXSW_REG_SBCM_DIR_EGRESS, 104, 2, 3) | 200 | MLXSW_SP_SB_CM(_tc, MLXSW_REG_SBXX_DIR_EGRESS, 104, 2, 3) |
201 | 201 | ||
202 | static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms[] = { | 202 | static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms[] = { |
203 | MLXSW_SP_SB_CM_INGRESS(0, MLXSW_SP_BYTES_TO_CELLS(10000), 8), | 203 | MLXSW_SP_SB_CM_INGRESS(0, MLXSW_SP_BYTES_TO_CELLS(10000), 8), |
@@ -304,7 +304,7 @@ static int mlxsw_sp_cpu_port_sb_cms_init(struct mlxsw_sp *mlxsw_sp) | |||
304 | 304 | ||
305 | struct mlxsw_sp_sb_pm { | 305 | struct mlxsw_sp_sb_pm { |
306 | u8 pool; | 306 | u8 pool; |
307 | enum mlxsw_reg_sbpm_dir dir; | 307 | enum mlxsw_reg_sbxx_dir dir; |
308 | u32 min_buff; | 308 | u32 min_buff; |
309 | u32 max_buff; | 309 | u32 max_buff; |
310 | }; | 310 | }; |
@@ -318,11 +318,11 @@ struct mlxsw_sp_sb_pm { | |||
318 | } | 318 | } |
319 | 319 | ||
320 | #define MLXSW_SP_SB_PM_INGRESS(_pool, _min_buff, _max_buff) \ | 320 | #define MLXSW_SP_SB_PM_INGRESS(_pool, _min_buff, _max_buff) \ |
321 | MLXSW_SP_SB_PM(_pool, MLXSW_REG_SBPM_DIR_INGRESS, \ | 321 | MLXSW_SP_SB_PM(_pool, MLXSW_REG_SBXX_DIR_INGRESS, \ |
322 | _min_buff, _max_buff) | 322 | _min_buff, _max_buff) |
323 | 323 | ||
324 | #define MLXSW_SP_SB_PM_EGRESS(_pool, _min_buff, _max_buff) \ | 324 | #define MLXSW_SP_SB_PM_EGRESS(_pool, _min_buff, _max_buff) \ |
325 | MLXSW_SP_SB_PM(_pool, MLXSW_REG_SBPM_DIR_EGRESS, \ | 325 | MLXSW_SP_SB_PM(_pool, MLXSW_REG_SBXX_DIR_EGRESS, \ |
326 | _min_buff, _max_buff) | 326 | _min_buff, _max_buff) |
327 | 327 | ||
328 | static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms[] = { | 328 | static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms[] = { |