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authorCorentin Labbe <clabbe.montjoie@gmail.com>2017-10-31 04:19:12 -0400
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-11-02 04:02:13 -0400
commit4904337fe34fa7fc529d6f4d9ee8b96fe7db310a (patch)
treee80a123e7e08ef138c03d37590d7e6fe3fafcd55
parent776245ae02f63ba2b94596b892c597676e190e78 (diff)
ARM: dts: sunxi: Restore EMAC changes (boards)
The original dwmac-sun8i DT bindings have some issue on how to handle integrated PHY and was reverted in last RC of 4.13. But now we have a solution so we need to get back that was reverted. This patch restore all boards DT about dwmac-sun8i This reverts partially commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes") Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-rw-r--r--arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts9
-rw-r--r--arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts19
-rw-r--r--arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts29
-rw-r--r--arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts7
-rw-r--r--arch/arm/boot/dts/sun8i-h3-orangepi-2.dts8
-rw-r--r--arch/arm/boot/dts/sun8i-h3-orangepi-one.dts8
-rw-r--r--arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts5
-rw-r--r--arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts8
-rw-r--r--arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts22
-rw-r--r--arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts16
10 files changed, 131 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
index b1502df7b509..6713d0f2b3f4 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -56,6 +56,8 @@
56 56
57 aliases { 57 aliases {
58 serial0 = &uart0; 58 serial0 = &uart0;
59 /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
60 ethernet0 = &emac;
59 ethernet1 = &xr819; 61 ethernet1 = &xr819;
60 }; 62 };
61 63
@@ -102,6 +104,13 @@
102 status = "okay"; 104 status = "okay";
103}; 105};
104 106
107&emac {
108 phy-handle = <&int_mii_phy>;
109 phy-mode = "mii";
110 allwinner,leds-active-low;
111 status = "okay";
112};
113
105&mmc0 { 114&mmc0 {
106 pinctrl-names = "default"; 115 pinctrl-names = "default";
107 pinctrl-0 = <&mmc0_pins_a>; 116 pinctrl-0 = <&mmc0_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index e1dba9ffa94b..f2292deaa590 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -52,6 +52,7 @@
52 compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3"; 52 compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
53 53
54 aliases { 54 aliases {
55 ethernet0 = &emac;
55 serial0 = &uart0; 56 serial0 = &uart0;
56 serial1 = &uart1; 57 serial1 = &uart1;
57 }; 58 };
@@ -111,6 +112,24 @@
111 status = "okay"; 112 status = "okay";
112}; 113};
113 114
115&emac {
116 pinctrl-names = "default";
117 pinctrl-0 = <&emac_rgmii_pins>;
118 phy-supply = <&reg_gmac_3v3>;
119 phy-handle = <&ext_rgmii_phy>;
120 phy-mode = "rgmii";
121
122 allwinner,leds-active-low;
123 status = "okay";
124};
125
126&external_mdio {
127 ext_rgmii_phy: ethernet-phy@1 {
128 compatible = "ethernet-phy-ieee802.3-c22";
129 reg = <0>;
130 };
131};
132
114&ir { 133&ir {
115 pinctrl-names = "default"; 134 pinctrl-names = "default";
116 pinctrl-0 = <&ir_pins_a>; 135 pinctrl-0 = <&ir_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
index 73766d38ee6c..0a8b79cf5954 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
@@ -51,6 +51,16 @@
51 ethernet1 = &sdio_wifi; 51 ethernet1 = &sdio_wifi;
52 }; 52 };
53 53
54 reg_gmac_3v3: gmac-3v3 {
55 compatible = "regulator-fixed";
56 regulator-name = "gmac-3v3";
57 regulator-min-microvolt = <3300000>;
58 regulator-max-microvolt = <3300000>;
59 startup-delay-us = <100000>;
60 enable-active-high;
61 gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
62 };
63
54 wifi_pwrseq: wifi_pwrseq { 64 wifi_pwrseq: wifi_pwrseq {
55 compatible = "mmc-pwrseq-simple"; 65 compatible = "mmc-pwrseq-simple";
56 pinctrl-names = "default"; 66 pinctrl-names = "default";
@@ -66,6 +76,25 @@
66 status = "okay"; 76 status = "okay";
67}; 77};
68 78
79&emac {
80 pinctrl-names = "default";
81 pinctrl-0 = <&emac_rgmii_pins>;
82 phy-supply = <&reg_gmac_3v3>;
83 phy-handle = <&ext_rgmii_phy>;
84 phy-mode = "rgmii";
85
86 allwinner,leds-active-low;
87
88 status = "okay";
89};
90
91&external_mdio {
92 ext_rgmii_phy: ethernet-phy@1 {
93 compatible = "ethernet-phy-ieee802.3-c22";
94 reg = <7>;
95 };
96};
97
69&ir { 98&ir {
70 pinctrl-names = "default"; 99 pinctrl-names = "default";
71 pinctrl-0 = <&ir_pins_a>; 100 pinctrl-0 = <&ir_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
index 8d2cc6e9a03f..78f6c24952dd 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
@@ -46,3 +46,10 @@
46 model = "FriendlyARM NanoPi NEO"; 46 model = "FriendlyARM NanoPi NEO";
47 compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; 47 compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
48}; 48};
49
50&emac {
51 phy-handle = <&int_mii_phy>;
52 phy-mode = "mii";
53 allwinner,leds-active-low;
54 status = "okay";
55};
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index 1bf51802f5aa..b20be95b49d5 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -54,6 +54,7 @@
54 aliases { 54 aliases {
55 serial0 = &uart0; 55 serial0 = &uart0;
56 /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ 56 /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
57 ethernet0 = &emac;
57 ethernet1 = &rtl8189; 58 ethernet1 = &rtl8189;
58 }; 59 };
59 60
@@ -117,6 +118,13 @@
117 status = "okay"; 118 status = "okay";
118}; 119};
119 120
121&emac {
122 phy-handle = <&int_mii_phy>;
123 phy-mode = "mii";
124 allwinner,leds-active-low;
125 status = "okay";
126};
127
120&ir { 128&ir {
121 pinctrl-names = "default"; 129 pinctrl-names = "default";
122 pinctrl-0 = <&ir_pins_a>; 130 pinctrl-0 = <&ir_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index a1c6ff6fd05d..82e5d28cd698 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -52,6 +52,7 @@
52 compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; 52 compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
53 53
54 aliases { 54 aliases {
55 ethernet0 = &emac;
55 serial0 = &uart0; 56 serial0 = &uart0;
56 }; 57 };
57 58
@@ -97,6 +98,13 @@
97 status = "okay"; 98 status = "okay";
98}; 99};
99 100
101&emac {
102 phy-handle = <&int_mii_phy>;
103 phy-mode = "mii";
104 allwinner,leds-active-low;
105 status = "okay";
106};
107
100&mmc0 { 108&mmc0 {
101 pinctrl-names = "default"; 109 pinctrl-names = "default";
102 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; 110 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
index 8b93f5c781a7..a10281b455f5 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
@@ -53,6 +53,11 @@
53 }; 53 };
54}; 54};
55 55
56&emac {
57 /* LEDs changed to active high on the plus */
58 /delete-property/ allwinner,leds-active-low;
59};
60
56&mmc1 { 61&mmc1 {
57 pinctrl-names = "default"; 62 pinctrl-names = "default";
58 pinctrl-0 = <&mmc1_pins_a>; 63 pinctrl-0 = <&mmc1_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index ea4e0029c0d4..d22546df1b82 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -52,6 +52,7 @@
52 compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; 52 compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
53 53
54 aliases { 54 aliases {
55 ethernet0 = &emac;
55 serial0 = &uart0; 56 serial0 = &uart0;
56 }; 57 };
57 58
@@ -113,6 +114,13 @@
113 status = "okay"; 114 status = "okay";
114}; 115};
115 116
117&emac {
118 phy-handle = <&int_mii_phy>;
119 phy-mode = "mii";
120 allwinner,leds-active-low;
121 status = "okay";
122};
123
116&ir { 124&ir {
117 pinctrl-names = "default"; 125 pinctrl-names = "default";
118 pinctrl-0 = <&ir_pins_a>; 126 pinctrl-0 = <&ir_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
index 72ca01b93f1b..cbc499b04de4 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
@@ -47,6 +47,10 @@
47 model = "Xunlong Orange Pi Plus / Plus 2"; 47 model = "Xunlong Orange Pi Plus / Plus 2";
48 compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; 48 compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
49 49
50 aliases {
51 ethernet0 = &emac;
52 };
53
50 reg_gmac_3v3: gmac-3v3 { 54 reg_gmac_3v3: gmac-3v3 {
51 compatible = "regulator-fixed"; 55 compatible = "regulator-fixed";
52 regulator-name = "gmac-3v3"; 56 regulator-name = "gmac-3v3";
@@ -74,6 +78,24 @@
74 status = "okay"; 78 status = "okay";
75}; 79};
76 80
81&emac {
82 pinctrl-names = "default";
83 pinctrl-0 = <&emac_rgmii_pins>;
84 phy-supply = <&reg_gmac_3v3>;
85 phy-handle = <&ext_rgmii_phy>;
86 phy-mode = "rgmii";
87
88 allwinner,leds-active-low;
89 status = "okay";
90};
91
92&external_mdio {
93 ext_rgmii_phy: ethernet-phy@1 {
94 compatible = "ethernet-phy-ieee802.3-c22";
95 reg = <0>;
96 };
97};
98
77&mmc2 { 99&mmc2 {
78 pinctrl-names = "default"; 100 pinctrl-names = "default";
79 pinctrl-0 = <&mmc2_8bit_pins>; 101 pinctrl-0 = <&mmc2_8bit_pins>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
index 97920b12a944..6dbf7b2e0c13 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
@@ -61,3 +61,19 @@
61 gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ 61 gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
62 }; 62 };
63}; 63};
64
65&emac {
66 pinctrl-names = "default";
67 pinctrl-0 = <&emac_rgmii_pins>;
68 phy-supply = <&reg_gmac_3v3>;
69 phy-handle = <&ext_rgmii_phy>;
70 phy-mode = "rgmii";
71 status = "okay";
72};
73
74&external_mdio {
75 ext_rgmii_phy: ethernet-phy@1 {
76 compatible = "ethernet-phy-ieee802.3-c22";
77 reg = <1>;
78 };
79};