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authorBrian Norris <briannorris@chromium.org>2017-03-20 19:53:42 -0400
committerHeiko Stuebner <heiko@sntech.de>2017-03-22 06:54:31 -0400
commit48f4d9796d990850f6339b61eeeac9ca7fdb3695 (patch)
tree2dd31c178855eacb025ccf38e75f3dbe8585599e
parent70968d63a1bf52a421f930b4bc55489449168b3c (diff)
arm64: dts: rockchip: add Gru/Kevin DTS
Kevin is part of a family of boards called Gru. As best as possible, the properties shared by the Gru family are placed in rk3399-gru.dtsi, while Kevin-specific bits are in rk3399-gru-kevin.dts. This does not add full support for the base Gru board. Working and tested (to some extent): * EC support -- including keyboard, battery, PWM, and probably more * UART / console * Thermal * Touchscreen * Touchpad * Digitizer (regulator still WIP) * PCIe / Wifi * Bluetooth / Webcam * SD card * eMMC * USB2 on TypeC - This works much of the time, but USB3 devices may or may not detect properly. Waiting on proper extcon support for USB3 over TypeC. - Depends on XHCI/DWC3 fixes for ARM64 that still haven't landed * Backlight Not working: * CPUFreq -- relies on special OVP support for our PWM regulator circuits * EC / extcon support -- and with it, USB3/TypeC/DP * DRM -- won't even build on ARM64, so all display, eDP, etc. is not enabled Not tested: * Audio Signed-off-by: Brian Norris <briannorris@chromium.org> [shared gru/kevin parts on a gru device] Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> [with a bit of reordering] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-rw-r--r--arch/arm64/boot/dts/rockchip/Makefile1
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts302
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi964
3 files changed, 1267 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 3a862894ea44..b82f7b61ab6f 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb
4dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb 4dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb
5dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb 5dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
6dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb 6dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
7dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
7 8
8always := $(dtb-y) 9always := $(dtb-y)
9subdir-y := $(dts-dirs) 10subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
new file mode 100644
index 000000000000..fd24071320be
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
@@ -0,0 +1,302 @@
1/*
2 * Google Gru-Kevin Rev 6+ board device tree source
3 *
4 * Copyright 2016-2017 Google, Inc
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45/dts-v1/;
46#include "rk3399-gru.dtsi"
47#include <include/dt-bindings/input/linux-event-codes.h>
48
49/*
50 * Kevin-specific things
51 *
52 * Things in this section should use names from Kevin schematic since no
53 * equivalent exists in Gru schematic. If referring to signals that exist
54 * in Gru we use the Gru names, though. Confusing enough for you?
55 */
56/ {
57 model = "Google Kevin";
58 compatible = "google,kevin-rev15", "google,kevin-rev14",
59 "google,kevin-rev13", "google,kevin-rev12",
60 "google,kevin-rev11", "google,kevin-rev10",
61 "google,kevin-rev9", "google,kevin-rev8",
62 "google,kevin-rev7", "google,kevin-rev6",
63 "google,kevin", "google,gru", "rockchip,rk3399";
64
65 /* Power tree */
66
67 p3_3v_dig: p3-3v-dig {
68 compatible = "regulator-fixed";
69 regulator-name = "p3.3v_dig";
70 pinctrl-names = "default";
71 pinctrl-0 = <&cpu3_pen_pwr_en>;
72
73 enable-active-high;
74 gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
75 vin-supply = <&pp3300>;
76 };
77
78 backlight: backlight {
79 compatible = "pwm-backlight";
80 pwms = <&cros_ec_pwm 1>;
81 brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
82 17 18 19 20 21 22 23 24 25 26 27 28 29 30
83 31 32 33 34 35 36 37 38 39 40 41 42 43 44
84 45 46 47 48 49 50 51 52 53 54 55 56 57 58
85 59 60 61 62 63 64 65 66 67 68 69 70 71 72
86 73 74 75 76 77 78 79 80 81 82 83 84 85 86
87 87 88 89 90 91 92 93 94 95 96 97 98 99 100>;
88 default-brightness-level = <51>;
89 enable-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
90 power-supply = <&pp3300_disp>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&bl_en>;
93 pwm-delay-us = <10000>;
94 };
95
96 thermistor_ppvar_bigcpu: thermistor-ppvar-bigcpu {
97 compatible = "murata,ncp15wb473";
98 pullup-uv = <1800000>;
99 pullup-ohm = <25500>;
100 pulldown-ohm = <0>;
101 io-channels = <&saradc 2>;
102 #thermal-sensor-cells = <0>;
103 };
104
105 thermistor_ppvar_litcpu: thermistor-ppvar-litcpu {
106 compatible = "murata,ncp15wb473";
107 pullup-uv = <1800000>;
108 pullup-ohm = <25500>;
109 pulldown-ohm = <0>;
110 io-channels = <&saradc 3>;
111 #thermal-sensor-cells = <0>;
112 };
113};
114
115&gpio_keys {
116 pinctrl-names = "default";
117 pinctrl-0 = <&bt_host_wake_l>, <&cpu1_pen_eject>;
118
119 pen-insert {
120 label = "Pen Insert";
121 /* Insert = low, eject = high */
122 gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
123 linux,code = <SW_PEN_INSERTED>;
124 linux,input-type = <EV_SW>;
125 wakeup-source;
126 };
127};
128
129&thermal_zones {
130 bigcpu_reg_thermal: bigcpu-reg-thermal {
131 polling-delay-passive = <100>; /* milliseconds */
132 polling-delay = <1000>; /* milliseconds */
133 thermal-sensors = <&thermistor_ppvar_bigcpu 0>;
134 sustainable-power = <4000>;
135
136 ppvar_bigcpu_trips: trips {
137 ppvar_bigcpu_on: ppvar-bigcpu-on {
138 temperature = <40000>; /* millicelsius */
139 hysteresis = <2000>; /* millicelsius */
140 type = "passive";
141 };
142
143 ppvar_bigcpu_alert: ppvar-bigcpu-alert {
144 temperature = <50000>; /* millicelsius */
145 hysteresis = <2000>; /* millicelsius */
146 type = "passive";
147 };
148
149 ppvar_bigcpu_crit: ppvar-bigcpu-crit {
150 temperature = <90000>; /* millicelsius */
151 hysteresis = <0>; /* millicelsius */
152 type = "critical";
153 };
154 };
155
156 cooling-maps {
157 map0 {
158 trip = <&ppvar_bigcpu_alert>;
159 cooling-device =
160 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
161 contribution = <4096>;
162 };
163 map1 {
164 trip = <&ppvar_bigcpu_alert>;
165 cooling-device =
166 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
167 contribution = <1024>;
168 };
169 };
170 };
171
172 litcpu_reg_thermal: litcpu-reg-thermal {
173 polling-delay-passive = <100>; /* milliseconds */
174 polling-delay = <1000>; /* milliseconds */
175 thermal-sensors = <&thermistor_ppvar_litcpu 0>;
176 sustainable-power = <4000>;
177
178 ppvar_litcpu_trips: trips {
179 ppvar_litcpu_on: ppvar-litcpu-on {
180 temperature = <40000>; /* millicelsius */
181 hysteresis = <2000>; /* millicelsius */
182 type = "passive";
183 };
184
185 ppvar_litcpu_alert: ppvar-litcpu-alert {
186 temperature = <50000>; /* millicelsius */
187 hysteresis = <2000>; /* millicelsius */
188 type = "passive";
189 };
190
191 ppvar_litcpu_crit: ppvar-litcpu-crit {
192 temperature = <90000>; /* millicelsius */
193 hysteresis = <0>; /* millicelsius */
194 type = "critical";
195 };
196 };
197 };
198};
199
200ap_i2c_tpm: &i2c0 {
201 status = "okay";
202
203 clock-frequency = <400000>;
204
205 /* These are relatively safe rise/fall times. */
206 i2c-scl-falling-time-ns = <50>;
207 i2c-scl-rising-time-ns = <300>;
208
209 tpm: tpm@20 {
210 compatible = "infineon,slb9645tt";
211 reg = <0x20>;
212 powered-while-suspended;
213 };
214};
215
216ap_i2c_dig: &i2c2 {
217 status = "okay";
218
219 clock-frequency = <400000>;
220
221 /* These are relatively safe rise/fall times. */
222 i2c-scl-falling-time-ns = <50>;
223 i2c-scl-rising-time-ns = <300>;
224
225 digitizer: digitizer@9 {
226 compatible = "hid-over-i2c";
227 reg = <0x9>;
228 pinctrl-names = "default";
229 pinctrl-0 = <&cpu1_dig_irq_l &cpu1_dig_pdct_l>;
230
231 interrupt-parent = <&gpio2>;
232 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
233
234 hid-descr-addr = <0x1>;
235 };
236};
237
238/* Adjustments to things in the gru baseboard */
239
240&ap_i2c_tp {
241 trackpad@4a {
242 compatible = "atmel,atmel_mxt_tp";
243 reg = <0x4a>;
244 pinctrl-names = "default";
245 pinctrl-0 = <&trackpad_int_l>;
246 interrupt-parent = <&gpio1>;
247 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
248 wakeup-source;
249 };
250};
251
252&ap_i2c_ts {
253 touchscreen@4b {
254 compatible = "atmel,atmel_mxt_ts";
255 reg = <0x4b>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&touch_int_l>;
258 interrupt-parent = <&gpio3>;
259 interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
260 };
261};
262
263&saradc {
264 status = "okay";
265 vref-supply = <&pp1800_ap_io>;
266};
267
268&mvl_wifi {
269 marvell,wakeup-pin = <14>; /* GPIO_14 on Marvell */
270};
271
272&pinctrl {
273 digitizer {
274 /* Has external pullup */
275 cpu1_dig_irq_l: cpu1-dig-irq-l {
276 rockchip,pins = <2 4 RK_FUNC_GPIO &pcfg_pull_none>;
277 };
278
279 /* Has external pullup */
280 cpu1_dig_pdct_l: cpu1-dig-pdct-l {
281 rockchip,pins = <2 5 RK_FUNC_GPIO &pcfg_pull_none>;
282 };
283 };
284
285 discrete-regulators {
286 cpu3_pen_pwr_en: cpu3-pen-pwr-en {
287 rockchip,pins = <4 30 RK_FUNC_GPIO &pcfg_pull_none>;
288 };
289 };
290
291 pen {
292 cpu1_pen_eject: cpu1-pen-eject {
293 rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_up>;
294 };
295 };
296
297 wifi {
298 wlan_host_wake_l: wlan-host-wake-l {
299 rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_none>;
300 };
301 };
302};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
new file mode 100644
index 000000000000..1a57014a7b59
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
@@ -0,0 +1,964 @@
1/*
2 * Google Gru (and derivatives) board device tree source
3 *
4 * Copyright 2016-2017 Google, Inc
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include <dt-bindings/input/input.h>
46#include "rk3399.dtsi"
47
48/ {
49 chosen {
50 stdout-path = "serial2:115200n8";
51 };
52
53 /*
54 * Power Tree
55 *
56 * In general an attempt is made to include all rails called out by
57 * the schematic as long as those rails interact in some way with
58 * the AP. AKA:
59 * - Rails that only connect to the EC (or devices that the EC talks to)
60 * are not included.
61 * - Rails _are_ included if the rails go to the AP even if the AP
62 * doesn't currently care about them / they are always on. The idea
63 * here is that it makes it easier to map to the schematic or extend
64 * later.
65 *
66 * If two rails are substantially the same from the AP's point of
67 * view, though, we won't create a full fixed regulator. We'll just
68 * put the child rail as an alias of the parent rail. Sometimes rails
69 * look the same to the AP because one of these is true:
70 * - The EC controls the enable and the EC always enables a rail as
71 * long as the AP is running.
72 * - The rails are actually connected to each other by a jumper and
73 * the distinction is just there to add clarity/flexibility to the
74 * schematic.
75 */
76
77 ppvar_sys: ppvar-sys {
78 compatible = "regulator-fixed";
79 regulator-name = "ppvar_sys";
80 regulator-always-on;
81 regulator-boot-on;
82 };
83
84 pp900_ap: pp900-ap {
85 compatible = "regulator-fixed";
86 regulator-name = "pp900_ap";
87
88 /* EC turns on w/ pp900_ap_en; always on for AP */
89 regulator-always-on;
90 regulator-boot-on;
91 regulator-min-microvolt = <900000>;
92 regulator-max-microvolt = <900000>;
93
94 vin-supply = <&ppvar_sys>;
95 };
96
97 pp1200_lpddr: pp1200-lpddr {
98 compatible = "regulator-fixed";
99 regulator-name = "pp1200_lpddr";
100
101 /* EC turns on w/ lpddr_pwr_en; always on for AP */
102 regulator-always-on;
103 regulator-boot-on;
104 regulator-min-microvolt = <1200000>;
105 regulator-max-microvolt = <1200000>;
106
107 vin-supply = <&ppvar_sys>;
108 };
109
110 pp1800: pp1800 {
111 compatible = "regulator-fixed";
112 regulator-name = "pp1800";
113
114 /* Always on when ppvar_sys shows power good */
115 regulator-always-on;
116 regulator-boot-on;
117 regulator-min-microvolt = <1800000>;
118 regulator-max-microvolt = <1800000>;
119
120 vin-supply = <&ppvar_sys>;
121 };
122
123 pp3000: pp3000 {
124 compatible = "regulator-fixed";
125 regulator-name = "pp3000";
126 pinctrl-names = "default";
127 pinctrl-0 = <&pp3000_en>;
128
129 enable-active-high;
130 gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
131
132 regulator-always-on;
133 regulator-boot-on;
134 regulator-min-microvolt = <3000000>;
135 regulator-max-microvolt = <3000000>;
136
137 vin-supply = <&ppvar_sys>;
138 };
139
140 pp3300: pp3300 {
141 compatible = "regulator-fixed";
142 regulator-name = "pp3300";
143
144 /* Always on; plain and simple */
145 regulator-always-on;
146 regulator-boot-on;
147 regulator-min-microvolt = <3300000>;
148 regulator-max-microvolt = <3300000>;
149
150 vin-supply = <&ppvar_sys>;
151 };
152
153 pp5000: pp5000 {
154 compatible = "regulator-fixed";
155 regulator-name = "pp5000";
156
157 /* EC turns on w/ pp5000_en; always on for AP */
158 regulator-always-on;
159 regulator-boot-on;
160 regulator-min-microvolt = <5000000>;
161 regulator-max-microvolt = <5000000>;
162
163 vin-supply = <&ppvar_sys>;
164 };
165
166 /* Schematics call this PPVAR even though it's fixed */
167 ppvar_logic: ppvar-logic {
168 compatible = "regulator-fixed";
169 regulator-name = "ppvar_logic";
170
171 /* EC turns on w/ ppvar_logic_en; always on for AP */
172 regulator-always-on;
173 regulator-boot-on;
174 regulator-min-microvolt = <900000>;
175 regulator-max-microvolt = <900000>;
176
177 vin-supply = <&ppvar_sys>;
178 };
179
180 /* EC turns on w/ pp900_ddrpll_en */
181 pp900_ddrpll: pp900-ap {
182 };
183
184 /* EC turns on w/ pp900_pcie_en */
185 pp900_pcie: pp900-ap {
186 };
187
188 /* EC turns on w/ pp900_pll_en */
189 pp900_pll: pp900-ap {
190 };
191
192 /* EC turns on w/ pp900_pmu_en */
193 pp900_pmu: pp900-ap {
194 };
195
196 /* EC turns on w/ pp900_usb_en */
197 pp900_usb: pp900-ap {
198 };
199
200 /* EC turns on w/ pp1800_s0_en_l */
201 pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 {
202 };
203
204 /* EC turns on w/ pp1800_avdd_en_l */
205 pp1800_avdd: pp1800 {
206 };
207
208 /* EC turns on w/ pp1800_lid_en_l */
209 pp1800_lid: pp1800_mic: pp1800 {
210 };
211
212 /* EC turns on w/ lpddr_pwr_en */
213 pp1800_lpddr: pp1800 {
214 };
215
216 /* EC turns on w/ pp1800_pmu_en_l */
217 pp1800_pmu: pp1800 {
218 };
219
220 /* EC turns on w/ pp1800_usb_en_l */
221 pp1800_usb: pp1800 {
222 };
223
224 pp1500_ap_io: pp1500-ap-io {
225 compatible = "regulator-fixed";
226 regulator-name = "pp1500_ap_io";
227 pinctrl-names = "default";
228 pinctrl-0 = <&pp1500_en>;
229
230 enable-active-high;
231 gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>;
232
233 regulator-always-on;
234 regulator-boot-on;
235 regulator-min-microvolt = <1500000>;
236 regulator-max-microvolt = <1500000>;
237
238 vin-supply = <&pp1800>;
239 };
240
241 pp1800_audio: pp1800-audio {
242 compatible = "regulator-fixed";
243 regulator-name = "pp1800_audio";
244 pinctrl-names = "default";
245 pinctrl-0 = <&pp1800_audio_en>;
246
247 enable-active-high;
248 gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>;
249
250 regulator-always-on;
251 regulator-boot-on;
252
253 vin-supply = <&pp1800>;
254 };
255
256 /* gpio is shared with pp3300_wifi_bt */
257 pp1800_pcie: pp1800-pcie {
258 compatible = "regulator-fixed";
259 regulator-name = "pp1800_pcie";
260 pinctrl-names = "default";
261 pinctrl-0 = <&wlan_module_pd_l>;
262
263 enable-active-high;
264 gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
265
266 /*
267 * Need to wait 1ms + ramp-up time before we can power on WiFi.
268 * This has been approximated as 8ms total.
269 */
270 regulator-enable-ramp-delay = <8000>;
271
272 vin-supply = <&pp1800>;
273 };
274
275 /*
276 * This is a bit of a hack. The WiFi module should be reset at least
277 * 1ms after its regulators have ramped up (max rampup time is ~7ms).
278 * With some stretching of the imagination, we can call the 1.8V
279 * regulator a supply.
280 */
281 wlan_pd_n: wlan-pd-n {
282 compatible = "regulator-fixed";
283 regulator-name = "wlan_pd_n";
284
285 /* Note the wlan_module_reset_l pinctrl */
286 enable-active-high;
287 gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
288
289 vin-supply = <&pp1800_pcie>;
290 };
291
292 /* Always on; plain and simple */
293 pp3000_ap: pp3000_emmc: pp3000 {
294 };
295
296 pp3000_sd_slot: pp3000-sd-slot {
297 compatible = "regulator-fixed";
298 regulator-name = "pp3000_sd_slot";
299 pinctrl-names = "default";
300 pinctrl-0 = <&sd_slot_pwr_en>;
301
302 enable-active-high;
303 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
304
305 vin-supply = <&pp3000>;
306 };
307
308 /*
309 * Technically, this is a small abuse of 'regulator-gpio'; this
310 * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are
311 * always on though, so it is sufficient to simply control the mux
312 * here.
313 */
314 ppvar_sd_card_io: ppvar-sd-card-io {
315 compatible = "regulator-gpio";
316 regulator-name = "ppvar_sd_card_io";
317 pinctrl-names = "default";
318 pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>;
319
320 enable-active-high;
321 enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
322 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
323 states = <1800000 0x1
324 3000000 0x0>;
325
326 regulator-min-microvolt = <1800000>;
327 regulator-max-microvolt = <3000000>;
328 };
329
330 /* EC turns on w/ pp3300_trackpad_en_l */
331 pp3300_trackpad: pp3300-trackpad {
332 };
333
334 /* EC turns on w/ pp3300_usb_en_l */
335 pp3300_usb: pp3300 {
336 };
337
338 pp3300_disp: pp3300-disp {
339 compatible = "regulator-fixed";
340 regulator-name = "pp3300_disp";
341 pinctrl-names = "default";
342 pinctrl-0 = <&pp3300_disp_en>;
343
344 enable-active-high;
345 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
346
347 startup-delay-us = <2000>;
348 vin-supply = <&pp3300>;
349 };
350
351 /* gpio is shared with pp1800_pcie and pinctrl is set there */
352 pp3300_wifi_bt: pp3300-wifi-bt {
353 compatible = "regulator-fixed";
354 regulator-name = "pp3300_wifi_bt";
355
356 enable-active-high;
357 gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
358
359 vin-supply = <&pp3300>;
360 };
361
362 /* EC turns on w/ usb_a_en */
363 pp5000_usb_a_vbus: pp5000 {
364 };
365
366 gpio_keys: gpio-keys {
367 compatible = "gpio-keys";
368 pinctrl-names = "default";
369 pinctrl-0 = <&bt_host_wake_l>;
370
371 wake-on-bt {
372 label = "Wake-on-Bluetooth";
373 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
374 linux,code = <KEY_WAKEUP>;
375 wakeup-source;
376 };
377 };
378
379 max98357a: max98357a {
380 compatible = "maxim,max98357a";
381 pinctrl-names = "default";
382 pinctrl-0 = <&sdmode_en>;
383 sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
384 sdmode-delay = <2>;
385 #sound-dai-cells = <0>;
386 status = "okay";
387 };
388
389 sound {
390 compatible = "rockchip,rk3399-gru-sound";
391 rockchip,cpu = <&i2s0 &i2s2>;
392 rockchip,codec = <&max98357a &headsetcodec &codec>;
393 };
394};
395
396&cru {
397 assigned-clocks =
398 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
399 <&cru PLL_NPLL>,
400 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
401 <&cru PCLK_PERIHP>,
402 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
403 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
404 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
405 assigned-clock-rates =
406 <600000000>, <800000000>,
407 <1000000000>,
408 <150000000>, <75000000>,
409 <37500000>,
410 <100000000>, <100000000>,
411 <50000000>, <800000000>,
412 <100000000>, <50000000>;
413};
414
415&emmc_phy {
416 status = "okay";
417};
418
419ap_i2c_mic: &i2c1 {
420 status = "okay";
421
422 clock-frequency = <400000>;
423
424 /* These are relatively safe rise/fall times */
425 i2c-scl-falling-time-ns = <50>;
426 i2c-scl-rising-time-ns = <300>;
427
428 headsetcodec: rt5514@57 {
429 compatible = "realtek,rt5514";
430 reg = <0x57>;
431 interrupt-parent = <&gpio1>;
432 interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
433 pinctrl-names = "default";
434 pinctrl-0 = <&mic_int>;
435 realtek,dmic-init-delay = <20>;
436 wakeup-source;
437 };
438};
439
440ap_i2c_ts: &i2c3 {
441 status = "okay";
442
443 clock-frequency = <400000>;
444
445 /* These are relatively safe rise/fall times */
446 i2c-scl-falling-time-ns = <50>;
447 i2c-scl-rising-time-ns = <300>;
448};
449
450ap_i2c_tp: &i2c5 {
451 status = "okay";
452
453 clock-frequency = <400000>;
454
455 /* These are relatively safe rise/fall times */
456 i2c-scl-falling-time-ns = <50>;
457 i2c-scl-rising-time-ns = <300>;
458
459 /*
460 * Note strange pullup enable. Apparently this avoids leakage but
461 * still allows us to get nice 4.7K pullups for high speed i2c
462 * transfers. Basically we want the pullup on whenever the ap is
463 * alive, so the "en" pin just gets set to output high.
464 */
465 pinctrl-0 = <&i2c5_xfer &ap_i2c_tp_pu_en>;
466};
467
468ap_i2c_audio: &i2c8 {
469 status = "okay";
470
471 clock-frequency = <400000>;
472
473 /* These are relatively safe rise/fall times */
474 i2c-scl-falling-time-ns = <50>;
475 i2c-scl-rising-time-ns = <300>;
476
477 codec: da7219@1a {
478 compatible = "dlg,da7219";
479 reg = <0x1a>;
480 interrupt-parent = <&gpio1>;
481 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
482 clocks = <&cru SCLK_I2S_8CH_OUT>;
483 clock-names = "mclk";
484 dlg,micbias-lvl = <2600>;
485 dlg,mic-amp-in-sel = "diff";
486 pinctrl-names = "default";
487 pinctrl-0 = <&headset_int_l>;
488 VDD-supply = <&pp1800>;
489 VDDMIC-supply = <&pp3300>;
490 VDDIO-supply = <&pp1800>;
491
492 da7219_aad {
493 dlg,adc-1bit-rpt = <1>;
494 dlg,btn-avg = <4>;
495 dlg,btn-cfg = <50>;
496 dlg,mic-det-thr = <500>;
497 dlg,jack-ins-deb = <20>;
498 dlg,jack-det-rate = "32ms_64ms";
499 dlg,jack-rem-deb = <1>;
500
501 dlg,a-d-btn-thr = <0xa>;
502 dlg,d-b-btn-thr = <0x16>;
503 dlg,b-c-btn-thr = <0x21>;
504 dlg,c-mic-btn-thr = <0x3E>;
505 };
506 };
507};
508
509&i2s0 {
510 status = "okay";
511};
512
513&i2s2 {
514 status = "okay";
515};
516
517&io_domains {
518 status = "okay";
519
520 audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */
521 bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */
522 gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */
523 sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */
524};
525
526&pcie0 {
527 status = "okay";
528
529 ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>;
532 vpcie3v3-supply = <&pp3300_wifi_bt>;
533 vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */
534 vpcie0v9-supply = <&pp900_pcie>;
535
536 pci_rootport: pcie@0,0 {
537 reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>;
538 #address-cells = <3>;
539 #size-cells = <2>;
540 ranges;
541
542 mvl_wifi: wifi@0,0 {
543 compatible = "pci1b4b,2b42";
544 reg = <0x83010000 0x0 0x00000000 0x0 0x00100000
545 0x83010000 0x0 0x00100000 0x0 0x00100000>;
546 interrupt-parent = <&gpio0>;
547 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
548 pinctrl-names = "default";
549 pinctrl-0 = <&wlan_host_wake_l>;
550 wakeup-source;
551 };
552 };
553};
554
555&pcie_phy {
556 status = "okay";
557};
558
559&pmu_io_domains {
560 status = "okay";
561
562 pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */
563};
564
565&pwm0 {
566 status = "okay";
567};
568
569&pwm1 {
570 status = "okay";
571};
572
573&pwm2 {
574 status = "okay";
575};
576
577&pwm3 {
578 status = "okay";
579};
580
581&sdhci {
582 /*
583 * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the
584 * same (or nearly the same) performance for all eMMC that are intended
585 * to be used.
586 */
587 assigned-clock-rates = <150000000>;
588
589 bus-width = <8>;
590 mmc-hs400-1_8v;
591 mmc-hs400-enhanced-strobe;
592 non-removable;
593 status = "okay";
594};
595
596&sdmmc {
597 status = "okay";
598
599 /*
600 * Note: configure "sdmmc_cd" as card detect even though it's actually
601 * hooked to ground. Because we specified "cd-gpios" below dw_mmc
602 * should be ignoring card detect anyway. Specifying the pin as
603 * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag)
604 * turned on that the system will still make sure the port is
605 * configured as SDMMC and not JTAG.
606 */
607 pinctrl-names = "default";
608 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_gpio
609 &sdmmc_bus4>;
610
611 bus-width = <4>;
612 cap-mmc-highspeed;
613 cap-sd-highspeed;
614 cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
615 disable-wp;
616 sd-uhs-sdr12;
617 sd-uhs-sdr25;
618 sd-uhs-sdr50;
619 sd-uhs-sdr104;
620 vmmc-supply = <&pp3000_sd_slot>;
621 vqmmc-supply = <&ppvar_sd_card_io>;
622};
623
624&spi1 {
625 status = "okay";
626
627 pinctrl-names = "default", "sleep";
628 pinctrl-1 = <&spi1_sleep>;
629
630 spiflash@0 {
631 compatible = "jedec,spi-nor";
632 reg = <0>;
633
634 /* May run faster once verified. */
635 spi-max-frequency = <10000000>;
636 };
637};
638
639&spi2 {
640 status = "okay";
641
642 wacky_spi_audio: spi2@0 {
643 compatible = "realtek,rt5514";
644 reg = <0>;
645
646 /* May run faster once verified. */
647 spi-max-frequency = <10000000>;
648 };
649};
650
651&spi5 {
652 status = "okay";
653
654 cros_ec: ec@0 {
655 compatible = "google,cros-ec-spi";
656 reg = <0>;
657 interrupt-parent = <&gpio0>;
658 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
659 pinctrl-names = "default";
660 pinctrl-0 = <&ec_ap_int_l>;
661 spi-max-frequency = <3000000>;
662
663 i2c_tunnel: i2c-tunnel {
664 compatible = "google,cros-ec-i2c-tunnel";
665 google,remote-bus = <4>;
666 #address-cells = <1>;
667 #size-cells = <0>;
668 };
669
670 cros_ec_pwm: ec-pwm {
671 compatible = "google,cros-ec-pwm";
672 #pwm-cells = <1>;
673 };
674 };
675};
676
677&tsadc {
678 status = "okay";
679
680 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
681 rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
682};
683
684&u2phy0 {
685 status = "okay";
686};
687
688&u2phy1 {
689 status = "okay";
690};
691
692&u2phy0_host {
693 status = "okay";
694};
695
696&u2phy1_host {
697 status = "okay";
698};
699
700&u2phy0_otg {
701 status = "okay";
702};
703
704&u2phy1_otg {
705 status = "okay";
706};
707
708&uart2 {
709 status = "okay";
710};
711
712&usb_host0_ehci {
713 status = "okay";
714};
715
716&usb_host0_ohci {
717 status = "okay";
718};
719
720&usb_host1_ehci {
721 status = "okay";
722};
723
724&usb_host1_ohci {
725 status = "okay";
726};
727
728&usbdrd3_0 {
729 status = "okay";
730};
731
732&usbdrd_dwc3_0 {
733 status = "okay";
734 dr_mode = "host";
735};
736
737&usbdrd3_1 {
738 status = "okay";
739};
740
741&usbdrd_dwc3_1 {
742 status = "okay";
743 dr_mode = "host";
744};
745
746#include <arm/cros-ec-keyboard.dtsi>
747#include <arm/cros-ec-sbs.dtsi>
748
749&pinctrl {
750 /*
751 * pinctrl settings for pins that have no real owners.
752 *
753 * At the moment settings are identical for S0 and S3, but if we later
754 * need to configure things differently for S3 we'll adjust here.
755 */
756 pinctrl-names = "default";
757 pinctrl-0 = <
758 &ap_pwroff /* AP will auto-assert this when in S3 */
759 &clk_32k /* This pin is always 32k on gru boards */
760
761 /*
762 * We want this driven low ASAP; firmware should help us, but
763 * we can help ourselves too.
764 */
765 &wlan_module_reset_l
766 >;
767
768 pcfg_output_low: pcfg-output-low {
769 output-low;
770 };
771
772 pcfg_output_high: pcfg-output-high {
773 output-high;
774 };
775
776 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
777 bias-disable;
778 drive-strength = <8>;
779 };
780
781 backlight-enable {
782 bl_en: bl-en {
783 rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_none>;
784 };
785 };
786
787 cros-ec {
788 ec_ap_int_l: ec-ap-int-l {
789 rockchip,pins = <RK_GPIO0 1 RK_FUNC_GPIO &pcfg_pull_up>;
790 };
791 };
792
793 discrete-regulators {
794 pp1500_en: pp1500-en {
795 rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO
796 &pcfg_pull_none>;
797 };
798
799 pp1800_audio_en: pp1800-audio-en {
800 rockchip,pins = <RK_GPIO0 2 RK_FUNC_GPIO
801 &pcfg_pull_down>;
802 };
803
804 pp3300_disp_en: pp3300-disp-en {
805 rockchip,pins = <RK_GPIO4 27 RK_FUNC_GPIO
806 &pcfg_pull_none>;
807 };
808
809 pp3000_en: pp3000-en {
810 rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO
811 &pcfg_pull_none>;
812 };
813
814 sd_io_pwr_en: sd-io-pwr-en {
815 rockchip,pins = <RK_GPIO2 2 RK_FUNC_GPIO
816 &pcfg_pull_none>;
817 };
818
819 sd_pwr_1800_sel: sd-pwr-1800-sel {
820 rockchip,pins = <RK_GPIO2 28 RK_FUNC_GPIO
821 &pcfg_pull_none>;
822 };
823
824 sd_slot_pwr_en: sd-slot-pwr-en {
825 rockchip,pins = <RK_GPIO4 29 RK_FUNC_GPIO
826 &pcfg_pull_none>;
827 };
828
829 wlan_module_pd_l: wlan-module-pd-l {
830 rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO
831 &pcfg_pull_down>;
832 };
833 };
834
835 codec {
836 /* Has external pullup */
837 headset_int_l: headset-int-l {
838 rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_none>;
839 };
840
841 mic_int: mic-int {
842 rockchip,pins = <1 13 RK_FUNC_GPIO &pcfg_pull_down>;
843 };
844 };
845
846 max98357a {
847 sdmode_en: sdmode-en {
848 rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_down>;
849 };
850 };
851
852 pcie {
853 pcie_clkreqn_cpm: pci-clkreqn-cpm {
854 /*
855 * Since our pcie doesn't support ClockPM(CPM), we want
856 * to hack this as gpio, so the EP could be able to
857 * de-assert it along and make ClockPM(CPM) work.
858 */
859 rockchip,pins = <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
860 };
861 };
862
863 sdmmc {
864 /*
865 * We run sdmmc at max speed; bump up drive strength.
866 * We also have external pulls, so disable the internal ones.
867 */
868 sdmmc_bus4: sdmmc-bus4 {
869 rockchip,pins =
870 <4 8 RK_FUNC_1 &pcfg_pull_none_8ma>,
871 <4 9 RK_FUNC_1 &pcfg_pull_none_8ma>,
872 <4 10 RK_FUNC_1 &pcfg_pull_none_8ma>,
873 <4 11 RK_FUNC_1 &pcfg_pull_none_8ma>;
874 };
875
876 sdmmc_clk: sdmmc-clk {
877 rockchip,pins =
878 <4 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
879 };
880
881 sdmmc_cmd: sdmmc-cmd {
882 rockchip,pins =
883 <4 13 RK_FUNC_1 &pcfg_pull_none_8ma>;
884 };
885
886 /*
887 * In our case the official card detect is hooked to ground
888 * to avoid getting access to JTAG just by sticking something
889 * in the SD card slot (see the force_jtag bit in the TRM).
890 *
891 * We still configure it as card detect because it doesn't
892 * hurt and dw_mmc will ignore it. We make sure to disable
893 * the pull though so we don't burn needless power.
894 */
895 sdmmc_cd: sdmcc-cd {
896 rockchip,pins =
897 <0 7 RK_FUNC_1 &pcfg_pull_none>;
898 };
899
900 /* This is where we actually hook up CD; has external pull */
901 sdmmc_cd_gpio: sdmmc-cd-gpio {
902 rockchip,pins = <4 24 RK_FUNC_GPIO &pcfg_pull_none>;
903 };
904 };
905
906 spi1 {
907 spi1_sleep: spi1-sleep {
908 /*
909 * Pull down SPI1 CLK/CS/RX/TX during suspend, to
910 * prevent leakage.
911 */
912 rockchip,pins = <1 9 RK_FUNC_GPIO &pcfg_pull_down>,
913 <1 10 RK_FUNC_GPIO &pcfg_pull_down>,
914 <1 7 RK_FUNC_GPIO &pcfg_pull_down>,
915 <1 8 RK_FUNC_GPIO &pcfg_pull_down>;
916 };
917 };
918
919 touchscreen {
920 touch_int_l: touch-int-l {
921 rockchip,pins = <3 13 RK_FUNC_GPIO &pcfg_pull_up>;
922 };
923
924 touch_reset_l: touch-reset-l {
925 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_pull_none>;
926 };
927 };
928
929 trackpad {
930 ap_i2c_tp_pu_en: ap-i2c-tp-pu-en {
931 rockchip,pins = <3 12 RK_FUNC_GPIO &pcfg_output_high>;
932 };
933
934 trackpad_int_l: trackpad-int-l {
935 rockchip,pins = <1 4 RK_FUNC_GPIO &pcfg_pull_up>;
936 };
937 };
938
939 wifi {
940 wifi_perst_l: wifi-perst-l {
941 rockchip,pins = <2 27 RK_FUNC_GPIO &pcfg_pull_none>;
942 };
943
944 wlan_module_reset_l: wlan-module-reset-l {
945 /*
946 * We want this driven low ASAP (As {Soon,Strongly} As
947 * Possible), to avoid leakage through the powered-down
948 * WiFi.
949 */
950 rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_output_low>;
951 };
952
953 bt_host_wake_l: bt-host-wake-l {
954 /* Kevin has an external pull up, but Gru does not */
955 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>;
956 };
957 };
958
959 write-protect {
960 ap_fw_wp: ap-fw-wp {
961 rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>;
962 };
963 };
964};