Merge tag 'drm-fixes-2018-06-29' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
 "Nothing too major this round:

   - small set of mali-dp fixes

   - single meson fix

   - a bunch of amdgpu fixes (one makes non-4k page sizes not be a bad
     experience)"

* tag 'drm-fixes-2018-06-29' of git://anongit.freedesktop.org/drm/drm:
  drm/amd/display: release spinlock before committing updates to stream
  drm/amdgpu:Support new VCN FW version naming convention
  drm/amdgpu: fix UBSAN: Undefined behaviour for amdgpu_fence.c
  drm/meson: Fix an un-handled error path in 'meson_drv_bind_master()'
  drm/amdgpu: GPU vs CPU page size fixes in amdgpu_vm_bo_split_mapping
  drm/amdgpu: Count disabled CRTCs in commit tail earlier
  drm/mali-dp: Rectify the width and height passed to rotmem_required()
  drm/arm/malidp: Preserve LAYER_FORMAT contents when setting format
  drm: mali-dp: Enable Global SE interrupts mask for DP500
  drm/arm/malidp: Ensure that the crtcs are shutdown before removing any encoder/connector

8 files changed, 59 insertions, 27 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 39ec6b8890a1..e74d620d9699 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -376,7 +376,7 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
         struct amdgpu_device *adev = ring->adev;
         uint64_t index;
 
-        if (ring != &adev->uvd.inst[ring->me].ring) {
+        if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) {
                 ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
                 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
         } else {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 127e87b470ff..1b4ad9b2a755 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -52,7 +52,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
         unsigned long bo_size;
         const char *fw_name;
         const struct common_firmware_header *hdr;
-        unsigned version_major, version_minor, family_id;
+        unsigned char fw_check;
         int r;
 
         INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
@@ -83,12 +83,33 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
 
         hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
         adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
-        family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
-        version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
-        version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
-        DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n",
-                version_major, version_minor, family_id);
 
+        /* Bit 20-23, it is encode major and non-zero for new naming convention.
+         * This field is part of version minor and DRM_DISABLED_FLAG in old naming
+         * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG
+         * is zero in old naming convention, this field is always zero so far.
+         * These four bits are used to tell which naming convention is present.
+         */
+        fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf;
+        if (fw_check) {
+                unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev;
+
+                fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff;
+                enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff;
+                enc_major = fw_check;
+                dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf;
+                vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf;
+                DRM_INFO("Found VCN firmware Version ENC: %hu.%hu DEC: %hu VEP: %hu Revision: %hu\n",
+                        enc_major, enc_minor, dec_ver, vep, fw_rev);
+        } else {
+                unsigned int version_major, version_minor, family_id;
+
+                family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
+                version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
+                version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
+                DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n",
+                        version_major, version_minor, family_id);
+        }
 
         bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
                   +  AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index b0eb2f537392..edf16b2b957a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1463,7 +1463,9 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
                         uint64_t count;
 
                         max_entries = min(max_entries, 16ull * 1024ull);
-                        for (count = 1; count < max_entries; ++count) {
+                        for (count = 1;
+                             count < max_entries / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
+                             ++count) {
                                 uint64_t idx = pfn + count;
 
                                 if (pages_addr[idx] !=
@@ -1476,7 +1478,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
                                 dma_addr = pages_addr;
                         } else {
                                 addr = pages_addr[pfn];
-                                max_entries = count;
+                                max_entries = count * (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
                         }
 
                 } else if (flags & AMDGPU_PTE_VALID) {
@@ -1491,7 +1493,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
                 if (r)
                         return r;
 
-                pfn += last - start + 1;
+                pfn += (last - start + 1) / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
                 if (nodes && nodes->size == pfn) {
                         pfn = 0;
                         ++nodes;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f9add85157e7..3a8d6356afc2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3928,10 +3928,11 @@ static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
         if (acrtc->base.state->event)
                 prepare_flip_isr(acrtc);
 
+        spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
+
         surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
         surface_updates->flip_addr = &addr;
 
-
         dc_commit_updates_for_stream(adev->dm.dc,
                                              surface_updates,
                                              1,
@@ -3944,9 +3945,6 @@ static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
                          __func__,
                          addr.address.grph.addr.high_part,
                          addr.address.grph.addr.low_part);
-
-
-        spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 }
 
 /*
@@ -4206,6 +4204,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
         struct drm_connector *connector;
         struct drm_connector_state *old_con_state, *new_con_state;
         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
+        int crtc_disable_count = 0;
 
         drm_atomic_helper_update_legacy_modeset_state(dev, state);
 
@@ -4410,6 +4409,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
                 bool modeset_needed;
 
+                if (old_crtc_state->active && !new_crtc_state->active)
+                        crtc_disable_count++;
+
                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
                 modeset_needed = modeset_required(
@@ -4463,11 +4465,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
          * so we can put the GPU into runtime suspend if we're not driving any
          * displays anymore
          */
+        for (i = 0; i < crtc_disable_count; i++)
+                pm_runtime_put_autosuspend(dev->dev);
         pm_runtime_mark_last_busy(dev->dev);
-        for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
-                if (old_crtc_state->active && !new_crtc_state->active)
-                        pm_runtime_put_autosuspend(dev->dev);
-        }
 }
 
 
diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c
index 8d20faa198cf..0a788d76ed5f 100644
--- a/drivers/gpu/drm/arm/malidp_drv.c
+++ b/drivers/gpu/drm/arm/malidp_drv.c
@@ -278,7 +278,6 @@ static int malidp_init(struct drm_device *drm)
 
 static void malidp_fini(struct drm_device *drm)
 {
-        drm_atomic_helper_shutdown(drm);
         drm_mode_config_cleanup(drm);
 }
 
@@ -646,6 +645,7 @@ vblank_fail:
         malidp_de_irq_fini(drm);
         drm->irq_enabled = false;
 irq_init_fail:
+        drm_atomic_helper_shutdown(drm);
         component_unbind_all(dev, drm);
 bind_fail:
         of_node_put(malidp->crtc.port);
@@ -681,6 +681,7 @@ static void malidp_unbind(struct device *dev)
         malidp_se_irq_fini(drm);
         malidp_de_irq_fini(drm);
         drm->irq_enabled = false;
+        drm_atomic_helper_shutdown(drm);
         component_unbind_all(dev, drm);
         of_node_put(malidp->crtc.port);
         malidp->crtc.port = NULL;
diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c
index d789b46dc817..069783e715f1 100644
--- a/drivers/gpu/drm/arm/malidp_hw.c
+++ b/drivers/gpu/drm/arm/malidp_hw.c
@@ -634,7 +634,8 @@ const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES] = {
                                 .vsync_irq = MALIDP500_DE_IRQ_VSYNC,
                         },
                         .se_irq_map = {
-                                .irq_mask = MALIDP500_SE_IRQ_CONF_MODE,
+                                .irq_mask = MALIDP500_SE_IRQ_CONF_MODE |
+                                            MALIDP500_SE_IRQ_GLOBAL,
                                 .vsync_irq = 0,
                         },
                         .dc_irq_map = {
diff --git a/drivers/gpu/drm/arm/malidp_planes.c b/drivers/gpu/drm/arm/malidp_planes.c
index 7a44897c50fe..29409a65d864 100644
--- a/drivers/gpu/drm/arm/malidp_planes.c
+++ b/drivers/gpu/drm/arm/malidp_planes.c
@@ -23,6 +23,7 @@
 
 /* Layer specific register offsets */
 #define MALIDP_LAYER_FORMAT             0x000
+#define   LAYER_FORMAT_MASK             0x3f
 #define MALIDP_LAYER_CONTROL            0x004
 #define   LAYER_ENABLE                  (1 << 0)
 #define   LAYER_FLOWCFG_MASK            7
@@ -235,8 +236,8 @@ static int malidp_de_plane_check(struct drm_plane *plane,
         if (state->rotation & MALIDP_ROTATED_MASK) {
                 int val;
 
-                val = mp->hwdev->hw->rotmem_required(mp->hwdev, state->crtc_h,
-                                                     state->crtc_w,
+                val = mp->hwdev->hw->rotmem_required(mp->hwdev, state->crtc_w,
+                                                     state->crtc_h,
                                                      fb->format->format);
                 if (val < 0)
                         return val;
@@ -337,7 +338,9 @@ static void malidp_de_plane_update(struct drm_plane *plane,
         dest_w = plane->state->crtc_w;
         dest_h = plane->state->crtc_h;
 
-        malidp_hw_write(mp->hwdev, ms->format, mp->layer->base);
+        val = malidp_hw_read(mp->hwdev, mp->layer->base);
+        val = (val & ~LAYER_FORMAT_MASK) | ms->format;
+        malidp_hw_write(mp->hwdev, val, mp->layer->base);
 
         for (i = 0; i < ms->n_planes; i++) {
                 /* calculate the offset for the layer's plane registers */
diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c
index 32b1a6cdecfc..d3443125e661 100644
--- a/drivers/gpu/drm/meson/meson_drv.c
+++ b/drivers/gpu/drm/meson/meson_drv.c
@@ -197,8 +197,10 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
         priv->io_base = regs;
 
         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi");
-        if (!res)
-                return -EINVAL;
+        if (!res) {
+                ret = -EINVAL;
+                goto free_drm;
+        }
         /* Simply ioremap since it may be a shared register zone */
         regs = devm_ioremap(dev, res->start, resource_size(res));
         if (!regs) {
@@ -215,8 +217,10 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
         }
 
         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dmc");
-        if (!res)
-                return -EINVAL;
+        if (!res) {
+                ret = -EINVAL;
+                goto free_drm;
+        }
         /* Simply ioremap since it may be a shared register zone */
         regs = devm_ioremap(dev, res->start, resource_size(res));
         if (!regs) {