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authorLinus Torvalds <torvalds@linux-foundation.org>2016-12-15 18:58:28 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2016-12-15 18:58:28 -0500
commit482c3e8835e9e9b325aad295c21bd9e965a11006 (patch)
tree26eda74bc8740c373100e2601d4dcb1036c01c9b
parent786a72d79140028537382fa63bea63d5640c27d6 (diff)
parent09a566514c49b730ac5099549c014180f00be250 (diff)
Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Arnd Bergmann: "A couple of interesting new SoC platforms are now supported, these are the respective DTS sources: - Samsung Exynos5433 mobile phone platform, including an (almost) fully supported phone reference board. - Hisilicon Hip07 server platform and D05 board, the latest iteration of their product line, now with 64 Cortex-A72 cores across two sockets. - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product line, used in Android tablets and ultra-cheap development boards - NXP LS1046A Communication processor, improving on the earlier LS1043A with faster CPU cores - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810) mobile phone SoCs - Early support for the Nvidia Tegra Tegra186 SoC - Amlogic S905D is a minor variant of their existing Android consumer product line - Rockchip PX5 automotive platform, a close relative of their popular rk3368 Android tablet chips Aside from the respective evaluation platforms for the above chips, there are only a few consumer devices and boards added this time: - Huawei Nexus 6P (Angler) mobile phone - LG Nexus 5x (Bullhead) mobile phone - Nexbox A1 and A95X Android TV boxes - Pine64 development board based on Allwinner A64 - Globalscale Marvell ESPRESSOBin community board based on Armada 3700 - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board For the existing platforms, we get bug fixes and new peripheral support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom, Rockchip, Berlin, and ZTE" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits) arm64: dts: fix build errors from missing dependencies ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ARM64: dts: meson-gxl: Add support for Nexbox A95X ARM64: dts: meson-gxm: Add support for the Nexbox A1 ARM: dts: artpec: add pcie support arm64: dts: berlin4ct-dmp: add missing unit name to /memory node arm64: dts: berlin4ct-stb: add missing unit name to /memory node arm64: dts: berlin4ct: add missing unit name to /soc node arm64: dts: qcom: msm8916: Add ddr support to sdhc1 arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 ARM: dts: Add xo to sdhc clock node on qcom platforms ARM64: dts: Add support for Meson GXM dt-bindings: add rockchip RK1108 Evaluation board arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1 arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310 arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/amlogic.txt19
-rw-r--r--Documentation/devicetree/bindings/arm/bcm/brcm,ns2.txt (renamed from Documentation/devicetree/bindings/arm/bcm/ns2.txt)0
-rw-r--r--Documentation/devicetree/bindings/arm/fsl.txt34
-rw-r--r--Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt4
-rw-r--r--Documentation/devicetree/bindings/arm/qcom.txt2
-rw-r--r--Documentation/devicetree/bindings/arm/rockchip.txt12
-rw-r--r--Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt2
-rw-r--r--Documentation/devicetree/bindings/arm/shmobile.txt4
-rw-r--r--Documentation/devicetree/bindings/arm/sunxi.txt1
-rw-r--r--Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt2
-rw-r--r--Documentation/devicetree/bindings/clock/qoriq-clock.txt3
-rw-r--r--Documentation/devicetree/bindings/i2c/trivial-devices.txt2
-rw-r--r--Documentation/devicetree/bindings/media/renesas,fcp.txt8
-rw-r--r--Documentation/devicetree/bindings/vendor-prefixes.txt2
-rw-r--r--MAINTAINERS1
-rw-r--r--arch/arm64/boot/dts/Makefile1
-rw-r--r--arch/arm64/boot/dts/allwinner/Makefile5
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts50
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts74
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi261
-rw-r--r--arch/arm64/boot/dts/amlogic/Makefile8
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi190
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gx.dtsi360
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts231
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts119
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi129
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi106
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi901
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxl-nexbox-a95x.dts205
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts77
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts58
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi48
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts69
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi54
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxl.dtsi301
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts169
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts77
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxm-s912-q201.dts58
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxm.dtsi114
-rw-r--r--arch/arm64/boot/dts/arm/juno-base.dtsi80
-rw-r--r--arch/arm64/boot/dts/arm/juno-r1.dts6
-rw-r--r--arch/arm64/boot/dts/arm/juno-r2.dts6
-rw-r--r--arch/arm64/boot/dts/arm/juno.dts6
-rw-r--r--arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts8
-rw-r--r--arch/arm64/boot/dts/broadcom/bcm2837.dtsi8
l---------arch/arm64/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi1
-rw-r--r--arch/arm64/boot/dts/broadcom/ns2-svk.dts38
-rw-r--r--arch/arm64/boot/dts/broadcom/ns2.dtsi62
-rw-r--r--arch/arm64/boot/dts/exynos/Makefile5
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi804
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-tm2.dts1049
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts41
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi23
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi22
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi296
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433.dtsi1462
-rw-r--r--arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi20
-rw-r--r--arch/arm64/boot/dts/exynos/exynos7.dtsi87
-rw-r--r--arch/arm64/boot/dts/freescale/Makefile2
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts2
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts2
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi78
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts212
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts150
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi515
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts2
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts2
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts2
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi116
-rw-r--r--arch/arm64/boot/dts/hisilicon/Makefile1
-rw-r--r--arch/arm64/boot/dts/hisilicon/hip06-d03.dts8
-rw-r--r--arch/arm64/boot/dts/hisilicon/hip06.dtsi23
-rw-r--r--arch/arm64/boot/dts/hisilicon/hip07-d05.dts66
-rw-r--r--arch/arm64/boot/dts/hisilicon/hip07.dtsi1059
-rw-r--r--arch/arm64/boot/dts/marvell/Makefile1
-rw-r--r--arch/arm64/boot/dts/marvell/armada-3720-db.dts2
-rw-r--r--arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts82
-rw-r--r--arch/arm64/boot/dts/marvell/armada-37xx.dtsi2
-rw-r--r--arch/arm64/boot/dts/marvell/armada-ap806.dtsi2
-rw-r--r--arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi2
-rw-r--r--arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi2
-rw-r--r--arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts2
-rw-r--r--arch/arm64/boot/dts/marvell/berlin4ct-stb.dts2
-rw-r--r--arch/arm64/boot/dts/marvell/berlin4ct.dtsi2
-rw-r--r--arch/arm64/boot/dts/nvidia/Makefile1
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts8
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi64
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra186.dtsi398
-rw-r--r--arch/arm64/boot/dts/qcom/Makefile7
-rw-r--r--arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi73
-rw-r--r--arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi15
-rw-r--r--arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi2
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916.dtsi73
-rw-r--r--arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts41
-rw-r--r--arch/arm64/boot/dts/qcom/msm8992-pins.dtsi38
-rw-r--r--arch/arm64/boot/dts/qcom/msm8992.dtsi184
-rw-r--r--arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts40
-rw-r--r--arch/arm64/boot/dts/qcom/msm8994-pins.dtsi38
-rw-r--r--arch/arm64/boot/dts/qcom/msm8994.dtsi216
-rw-r--r--arch/arm64/boot/dts/qcom/msm8996.dtsi91
-rw-r--r--arch/arm64/boot/dts/qcom/pm8916.dtsi45
-rw-r--r--arch/arm64/boot/dts/qcom/pm8994.dtsi1
-rw-r--r--arch/arm64/boot/dts/renesas/Makefile2
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts53
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts85
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795.dtsi29
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts189
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts160
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796.dtsi255
-rw-r--r--arch/arm64/boot/dts/rockchip/Makefile1
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts2
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts314
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3368.dtsi18
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-evb.dts40
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399.dtsi55
-rw-r--r--arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi59
-rw-r--r--arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi111
-rw-r--r--arch/arm64/boot/dts/zte/zx296718.dtsi24
118 files changed, 12147 insertions, 709 deletions
diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt
index fcc6f6c10803..9b2b41ab6817 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.txt
+++ b/Documentation/devicetree/bindings/arm/amlogic.txt
@@ -17,6 +17,18 @@ Boards with the Amlogic Meson GXBaby SoC shall have the following properties:
17 Required root node property: 17 Required root node property:
18 compatible: "amlogic,meson-gxbb"; 18 compatible: "amlogic,meson-gxbb";
19 19
20Boards with the Amlogic Meson GXL S905X SoC shall have the following properties:
21 Required root node property:
22 compatible: "amlogic,s905x", "amlogic,meson-gxl";
23
24Boards with the Amlogic Meson GXL S905D SoC shall have the following properties:
25 Required root node property:
26 compatible: "amlogic,s905d", "amlogic,meson-gxl";
27
28Boards with the Amlogic Meson GXM S912 SoC shall have the following properties:
29 Required root node property:
30 compatible: "amlogic,s912", "amlogic,meson-gxm";
31
20Board compatible values: 32Board compatible values:
21 - "geniatech,atv1200" (Meson6) 33 - "geniatech,atv1200" (Meson6)
22 - "minix,neo-x8" (Meson8) 34 - "minix,neo-x8" (Meson8)
@@ -28,3 +40,10 @@ Board compatible values:
28 - "hardkernel,odroid-c2" (Meson gxbb) 40 - "hardkernel,odroid-c2" (Meson gxbb)
29 - "amlogic,p200" (Meson gxbb) 41 - "amlogic,p200" (Meson gxbb)
30 - "amlogic,p201" (Meson gxbb) 42 - "amlogic,p201" (Meson gxbb)
43 - "amlogic,p212" (Meson gxl s905x)
44 - "amlogic,p230" (Meson gxl s905d)
45 - "amlogic,p231" (Meson gxl s905d)
46 - "amlogic,q200" (Meson gxm s912)
47 - "amlogic,q201" (Meson gxm s912)
48 - "nexbox,a95x" (Meson gxbb or Meson gxl s905x)
49 - "nexbox,a1" (Meson gxm s912)
diff --git a/Documentation/devicetree/bindings/arm/bcm/ns2.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,ns2.txt
index 35f056f4a1c3..35f056f4a1c3 100644
--- a/Documentation/devicetree/bindings/arm/bcm/ns2.txt
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,ns2.txt
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index dbbc0952021c..d6ee9c6e1dbb 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -97,7 +97,7 @@ Freescale LS1021A Platform Device Tree Bindings
97Required root node compatible properties: 97Required root node compatible properties:
98 - compatible = "fsl,ls1021a"; 98 - compatible = "fsl,ls1021a";
99 99
100Freescale LS1021A SoC-specific Device Tree Bindings 100Freescale SoC-specific Device Tree Bindings
101------------------------------------------- 101-------------------------------------------
102 102
103Freescale SCFG 103Freescale SCFG
@@ -105,7 +105,11 @@ Freescale SCFG
105configuration and status registers for the chip. Such as getting PEX port 105configuration and status registers for the chip. Such as getting PEX port
106status. 106status.
107 Required properties: 107 Required properties:
108 - compatible: should be "fsl,ls1021a-scfg" 108 - compatible: Should contain a chip-specific compatible string,
109 Chip-specific strings are of the form "fsl,<chip>-scfg",
110 The following <chip>s are known to be supported:
111 ls1021a, ls1043a, ls1046a, ls2080a.
112
109 - reg: should contain base address and length of SCFG memory-mapped registers 113 - reg: should contain base address and length of SCFG memory-mapped registers
110 114
111Example: 115Example:
@@ -119,7 +123,11 @@ Freescale DCFG
119configuration and status for the device. Such as setting the secondary 123configuration and status for the device. Such as setting the secondary
120core start address and release the secondary core from holdoff and startup. 124core start address and release the secondary core from holdoff and startup.
121 Required properties: 125 Required properties:
122 - compatible: should be "fsl,ls1021a-dcfg" 126 - compatible: Should contain a chip-specific compatible string,
127 Chip-specific strings are of the form "fsl,<chip>-dcfg",
128 The following <chip>s are known to be supported:
129 ls1021a, ls1043a, ls1046a, ls2080a.
130
123 - reg : should contain base address and length of DCFG memory-mapped registers 131 - reg : should contain base address and length of DCFG memory-mapped registers
124 132
125Example: 133Example:
@@ -131,6 +139,10 @@ Example:
131Freescale ARMv8 based Layerscape SoC family Device Tree Bindings 139Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
132---------------------------------------------------------------- 140----------------------------------------------------------------
133 141
142LS1043A SoC
143Required root node properties:
144 - compatible = "fsl,ls1043a";
145
134LS1043A ARMv8 based RDB Board 146LS1043A ARMv8 based RDB Board
135Required root node properties: 147Required root node properties:
136 - compatible = "fsl,ls1043a-rdb", "fsl,ls1043a"; 148 - compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
@@ -139,6 +151,22 @@ LS1043A ARMv8 based QDS Board
139Required root node properties: 151Required root node properties:
140 - compatible = "fsl,ls1043a-qds", "fsl,ls1043a"; 152 - compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
141 153
154LS1046A SoC
155Required root node properties:
156 - compatible = "fsl,ls1046a";
157
158LS1046A ARMv8 based QDS Board
159Required root node properties:
160 - compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
161
162LS1046A ARMv8 based RDB Board
163Required root node properties:
164 - compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
165
166LS2080A SoC
167Required root node properties:
168 - compatible = "fsl,ls2080a";
169
142LS2080A ARMv8 based Simulator model 170LS2080A ARMv8 based Simulator model
143Required root node properties: 171Required root node properties:
144 - compatible = "fsl,ls2080a-simu", "fsl,ls2080a"; 172 - compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 3f81575aa6be..7df79a715611 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -28,6 +28,10 @@ HiP06 D03 Board
28Required root node properties: 28Required root node properties:
29 - compatible = "hisilicon,hip06-d03"; 29 - compatible = "hisilicon,hip06-d03";
30 30
31HiP07 D05 Board
32Required root node properties:
33 - compatible = "hisilicon,hip07-d05";
34
31Hisilicon system controller 35Hisilicon system controller
32 36
33Required properties: 37Required properties:
diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt
index 43abf4e0a0a5..028d16e72186 100644
--- a/Documentation/devicetree/bindings/arm/qcom.txt
+++ b/Documentation/devicetree/bindings/arm/qcom.txt
@@ -21,6 +21,8 @@ The 'SoC' element must be one of the following strings:
21 apq8096 21 apq8096
22 msm8916 22 msm8916
23 msm8974 23 msm8974
24 msm8992
25 msm8994
24 msm8996 26 msm8996
25 mdm9615 27 mdm9615
26 28
diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
index e921f3efac64..cc4ace6397ab 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.txt
+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
@@ -103,6 +103,18 @@ Rockchip platforms device tree bindings
103 Required root node properties: 103 Required root node properties:
104 - compatible = "mqmaker,miqi", "rockchip,rk3288"; 104 - compatible = "mqmaker,miqi", "rockchip,rk3288";
105 105
106- Rockchip PX3 Evaluation board:
107 Required root node properties:
108 - compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
109
110- Rockchip PX5 Evaluation board:
111 Required root node properties:
112 - compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
113
114- Rockchip RK1108 Evaluation board
115 Required root node properties:
116 - compatible = "rockchip,rk1108-evb", "rockchip,rk1108";
117
106- Rockchip RK3368 evb: 118- Rockchip RK3368 evb:
107 Required root node properties: 119 Required root node properties:
108 - compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368"; 120 - compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368";
diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
index 5160fa5f7b5c..3c551894f621 100644
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
@@ -15,6 +15,8 @@ Required root node properties:
15 - "samsung,xyref5260" - for Exynos5260-based Samsung board. 15 - "samsung,xyref5260" - for Exynos5260-based Samsung board.
16 - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board. 16 - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board.
17 - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board. 17 - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board.
18 - "samsung,tm2" - for Exynos5433-based Samsung TM2 board.
19 - "samsung,tm2e" - for Exynos5433-based Samsung TM2E board.
18 - "samsung,sd5v1" - for Exynos5440-based Samsung board. 20 - "samsung,sd5v1" - for Exynos5440-based Samsung board.
19 - "samsung,ssdk5440" - for Exynos5440-based Samsung board. 21 - "samsung,ssdk5440" - for Exynos5440-based Samsung board.
20 22
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 3c7acf22957a..5d8229d74a5f 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -53,7 +53,7 @@ Boards:
53 compatible = "renesas,genmai", "renesas,r7s72100" 53 compatible = "renesas,genmai", "renesas,r7s72100"
54 - Gose (RTP0RC7793SEB00010S) 54 - Gose (RTP0RC7793SEB00010S)
55 compatible = "renesas,gose", "renesas,r8a7793" 55 compatible = "renesas,gose", "renesas,r8a7793"
56 - H3ULCB (RTP0RC7795SKB00010S) 56 - H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKB00010S)
57 compatible = "renesas,h3ulcb", "renesas,r8a7795"; 57 compatible = "renesas,h3ulcb", "renesas,r8a7795";
58 - Henninger 58 - Henninger
59 compatible = "renesas,henninger", "renesas,r8a7791" 59 compatible = "renesas,henninger", "renesas,r8a7791"
@@ -65,6 +65,8 @@ Boards:
65 compatible = "renesas,kzm9g", "renesas,sh73a0" 65 compatible = "renesas,kzm9g", "renesas,sh73a0"
66 - Lager (RTP0RC7790SEB00010S) 66 - Lager (RTP0RC7790SEB00010S)
67 compatible = "renesas,lager", "renesas,r8a7790" 67 compatible = "renesas,lager", "renesas,r8a7790"
68 - M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKB00010S)
69 compatible = "renesas,m3ulcb", "renesas,r8a7796";
68 - Marzen (R0P7779A00010S) 70 - Marzen (R0P7779A00010S)
69 compatible = "renesas,marzen", "renesas,r8a7779" 71 compatible = "renesas,marzen", "renesas,r8a7779"
70 - Porter (M2-LCDP) 72 - Porter (M2-LCDP)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
index 3975d0a0e4c2..4d6467cc2aa2 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -14,4 +14,5 @@ using one of the following compatible strings:
14 allwinner,sun8i-a83t 14 allwinner,sun8i-a83t
15 allwinner,sun8i-h3 15 allwinner,sun8i-h3
16 allwinner,sun9i-a80 16 allwinner,sun9i-a80
17 allwinner,sun50i-a64
17 nextthing,gr8 18 nextthing,gr8
diff --git a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
index 032a7606b862..fc33ca01e9ba 100644
--- a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
@@ -3,7 +3,7 @@ Binding for Freescale QorIQ AHCI SATA Controller
3Required properties: 3Required properties:
4 - reg: Physical base address and size of the controller's register area. 4 - reg: Physical base address and size of the controller's register area.
5 - compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where 5 - compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
6 chip could be ls1021a, ls2080a, ls1043a etc. 6 chip could be ls1021a, ls1043a, ls1046a, ls2080a etc.
7 - clocks: Input clock specifier. Refer to common clock bindings. 7 - clocks: Input clock specifier. Refer to common clock bindings.
8 - interrupts: Interrupt specifier. Refer to interrupt binding. 8 - interrupts: Interrupt specifier. Refer to interrupt binding.
9 9
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index 16a3ec433119..df9cb5ac5f72 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -32,6 +32,9 @@ Required properties:
32 * "fsl,b4420-clockgen" 32 * "fsl,b4420-clockgen"
33 * "fsl,b4860-clockgen" 33 * "fsl,b4860-clockgen"
34 * "fsl,ls1021a-clockgen" 34 * "fsl,ls1021a-clockgen"
35 * "fsl,ls1043a-clockgen"
36 * "fsl,ls1046a-clockgen"
37 * "fsl,ls2080a-clockgen"
35 Chassis-version clock strings include: 38 Chassis-version clock strings include:
36 * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks 39 * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
37 * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks 40 * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
index df720ca00fcf..ff86fdcbd353 100644
--- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt
+++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
@@ -138,6 +138,8 @@ nuvoton,npct501 i2c trusted platform module (TPM)
138nuvoton,npct601 i2c trusted platform module (TPM2) 138nuvoton,npct601 i2c trusted platform module (TPM2)
139nxp,pca9556 Octal SMBus and I2C registered interface 139nxp,pca9556 Octal SMBus and I2C registered interface
140nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset 140nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset
141nxp,pcf2127 Real-time clock
142nxp,pcf2129 Real-time clock
141nxp,pcf8563 Real-time clock/calendar 143nxp,pcf8563 Real-time clock/calendar
142nxp,pcf85063 Tiny Real-Time Clock 144nxp,pcf85063 Tiny Real-Time Clock
143oki,ml86v7667 OKI ML86V7667 video decoder 145oki,ml86v7667 OKI ML86V7667 video decoder
diff --git a/Documentation/devicetree/bindings/media/renesas,fcp.txt b/Documentation/devicetree/bindings/media/renesas,fcp.txt
index 27f9b8e459ac..3ec91803ba58 100644
--- a/Documentation/devicetree/bindings/media/renesas,fcp.txt
+++ b/Documentation/devicetree/bindings/media/renesas,fcp.txt
@@ -11,15 +11,9 @@ are paired with. These DT bindings currently support the FCPV and FCPF.
11 11
12 - compatible: Must be one or more of the following 12 - compatible: Must be one or more of the following
13 13
14 - "renesas,r8a7795-fcpv" for R8A7795 (R-Car H3) compatible 'FCP for VSP'
15 - "renesas,r8a7795-fcpf" for R8A7795 (R-Car H3) compatible 'FCP for FDP'
16 - "renesas,fcpv" for generic compatible 'FCP for VSP' 14 - "renesas,fcpv" for generic compatible 'FCP for VSP'
17 - "renesas,fcpf" for generic compatible 'FCP for FDP' 15 - "renesas,fcpf" for generic compatible 'FCP for FDP'
18 16
19 When compatible with the generic version, nodes must list the
20 SoC-specific version corresponding to the platform first, followed by the
21 family-specific and/or generic versions.
22
23 - reg: the register base and size for the device registers 17 - reg: the register base and size for the device registers
24 - clocks: Reference to the functional clock 18 - clocks: Reference to the functional clock
25 19
@@ -32,7 +26,7 @@ Device node example
32------------------- 26-------------------
33 27
34 fcpvd1: fcp@fea2f000 { 28 fcpvd1: fcp@fea2f000 {
35 compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; 29 compatible = "renesas,fcpv";
36 reg = <0 0xfea2f000 0 0x200>; 30 reg = <0 0xfea2f000 0 0x200>;
37 clocks = <&cpg CPG_MOD 602>; 31 clocks = <&cpg CPG_MOD 602>;
38 power-domains = <&sysc R8A7795_PD_A3VP>; 32 power-domains = <&sysc R8A7795_PD_A3VP>;
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 448c831753f8..16d3b5e7f5d1 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -197,6 +197,7 @@ neonode Neonode Inc.
197netgear NETGEAR 197netgear NETGEAR
198netlogic Broadcom Corporation (formerly NetLogic Microsystems) 198netlogic Broadcom Corporation (formerly NetLogic Microsystems)
199netxeon Shenzhen Netxeon Technology CO., LTD 199netxeon Shenzhen Netxeon Technology CO., LTD
200nexbox Nexbox
200newhaven Newhaven Display International 201newhaven Newhaven Display International
201ni National Instruments 202ni National Instruments
202nintendo Nintendo 203nintendo Nintendo
@@ -222,6 +223,7 @@ parade Parade Technologies Inc.
222pericom Pericom Technology Inc. 223pericom Pericom Technology Inc.
223phytec PHYTEC Messtechnik GmbH 224phytec PHYTEC Messtechnik GmbH
224picochip Picochip Ltd 225picochip Picochip Ltd
226pine64 Pine64
225pixcir PIXCIR MICROELECTRONICS Co., Ltd 227pixcir PIXCIR MICROELECTRONICS Co., Ltd
226plathome Plat'Home Co., Ltd. 228plathome Plat'Home Co., Ltd.
227plda PLDA 229plda PLDA
diff --git a/MAINTAINERS b/MAINTAINERS
index 3d7cf9910775..b5f5d5b47774 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1042,6 +1042,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1042S: Maintained 1042S: Maintained
1043N: sun[x456789]i 1043N: sun[x456789]i
1044F: arch/arm/boot/dts/ntc-gr8* 1044F: arch/arm/boot/dts/ntc-gr8*
1045F: arch/arm64/boot/dts/allwinner/
1045 1046
1046ARM/Allwinner SoC Clock Support 1047ARM/Allwinner SoC Clock Support
1047M: Emilio López <emilio@elopez.com.ar> 1048M: Emilio López <emilio@elopez.com.ar>
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 6684f97c2722..080232b0270e 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,4 +1,5 @@
1dts-dirs += al 1dts-dirs += al
2dts-dirs += allwinner
2dts-dirs += altera 3dts-dirs += altera
3dts-dirs += amd 4dts-dirs += amd
4dts-dirs += amlogic 5dts-dirs += amlogic
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
new file mode 100644
index 000000000000..1e29a5ae8282
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -0,0 +1,5 @@
1dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
2
3always := $(dtb-y)
4subdir-y := $(dts-dirs)
5clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
new file mode 100644
index 000000000000..790d14daaa6a
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
@@ -0,0 +1,50 @@
1/*
2 * Copyright (c) 2016 ARM Ltd.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "sun50i-a64-pine64.dts"
44
45/ {
46 model = "Pine64+";
47 compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
48
49 /* TODO: Camera, Ethernet PHY, touchscreen, etc. */
50};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
new file mode 100644
index 000000000000..47095909d9d6
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -0,0 +1,74 @@
1/*
2 * Copyright (c) 2016 ARM Ltd.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/dts-v1/;
44
45#include "sun50i-a64.dtsi"
46
47/ {
48 model = "Pine64";
49 compatible = "pine64,pine64", "allwinner,sun50i-a64";
50
51 aliases {
52 serial0 = &uart0;
53 };
54
55 chosen {
56 stdout-path = "serial0:115200n8";
57 };
58};
59
60&uart0 {
61 pinctrl-names = "default";
62 pinctrl-0 = <&uart0_pins_a>;
63 status = "okay";
64};
65
66&i2c1 {
67 pinctrl-names = "default";
68 pinctrl-0 = <&i2c1_pins>;
69 status = "okay";
70};
71
72&i2c1_pins {
73 bias-pull-up;
74};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
new file mode 100644
index 000000000000..e0dcab8eb035
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -0,0 +1,261 @@
1/*
2 * Copyright (C) 2016 ARM Ltd.
3 * based on the Allwinner H3 dtsi:
4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include <dt-bindings/interrupt-controller/arm-gic.h>
46#include <dt-bindings/pinctrl/sun4i-a10.h>
47
48/ {
49 interrupt-parent = <&gic>;
50 #address-cells = <1>;
51 #size-cells = <1>;
52
53 cpus {
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 cpu0: cpu@0 {
58 compatible = "arm,cortex-a53", "arm,armv8";
59 device_type = "cpu";
60 reg = <0>;
61 enable-method = "psci";
62 };
63
64 cpu1: cpu@1 {
65 compatible = "arm,cortex-a53", "arm,armv8";
66 device_type = "cpu";
67 reg = <1>;
68 enable-method = "psci";
69 };
70
71 cpu2: cpu@2 {
72 compatible = "arm,cortex-a53", "arm,armv8";
73 device_type = "cpu";
74 reg = <2>;
75 enable-method = "psci";
76 };
77
78 cpu3: cpu@3 {
79 compatible = "arm,cortex-a53", "arm,armv8";
80 device_type = "cpu";
81 reg = <3>;
82 enable-method = "psci";
83 };
84 };
85
86 osc24M: osc24M_clk {
87 #clock-cells = <0>;
88 compatible = "fixed-clock";
89 clock-frequency = <24000000>;
90 clock-output-names = "osc24M";
91 };
92
93 osc32k: osc32k_clk {
94 #clock-cells = <0>;
95 compatible = "fixed-clock";
96 clock-frequency = <32768>;
97 clock-output-names = "osc32k";
98 };
99
100 psci {
101 compatible = "arm,psci-0.2";
102 method = "smc";
103 };
104
105 timer {
106 compatible = "arm,armv8-timer";
107 interrupts = <GIC_PPI 13
108 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
109 <GIC_PPI 14
110 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
111 <GIC_PPI 11
112 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
113 <GIC_PPI 10
114 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
115 };
116
117 soc {
118 compatible = "simple-bus";
119 #address-cells = <1>;
120 #size-cells = <1>;
121 ranges;
122
123 ccu: clock@01c20000 {
124 compatible = "allwinner,sun50i-a64-ccu";
125 reg = <0x01c20000 0x400>;
126 clocks = <&osc24M>, <&osc32k>;
127 clock-names = "hosc", "losc";
128 #clock-cells = <1>;
129 #reset-cells = <1>;
130 };
131
132 pio: pinctrl@1c20800 {
133 compatible = "allwinner,sun50i-a64-pinctrl";
134 reg = <0x01c20800 0x400>;
135 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
136 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
138 clocks = <&ccu 58>;
139 gpio-controller;
140 #gpio-cells = <3>;
141 interrupt-controller;
142 #interrupt-cells = <3>;
143
144 i2c1_pins: i2c1_pins {
145 pins = "PH2", "PH3";
146 function = "i2c1";
147 };
148
149 uart0_pins_a: uart0@0 {
150 pins = "PB8", "PB9";
151 function = "uart0";
152 };
153 };
154
155 uart0: serial@1c28000 {
156 compatible = "snps,dw-apb-uart";
157 reg = <0x01c28000 0x400>;
158 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
159 reg-shift = <2>;
160 reg-io-width = <4>;
161 clocks = <&ccu 67>;
162 resets = <&ccu 46>;
163 status = "disabled";
164 };
165
166 uart1: serial@1c28400 {
167 compatible = "snps,dw-apb-uart";
168 reg = <0x01c28400 0x400>;
169 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
170 reg-shift = <2>;
171 reg-io-width = <4>;
172 clocks = <&ccu 68>;
173 resets = <&ccu 47>;
174 status = "disabled";
175 };
176
177 uart2: serial@1c28800 {
178 compatible = "snps,dw-apb-uart";
179 reg = <0x01c28800 0x400>;
180 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
181 reg-shift = <2>;
182 reg-io-width = <4>;
183 clocks = <&ccu 69>;
184 resets = <&ccu 48>;
185 status = "disabled";
186 };
187
188 uart3: serial@1c28c00 {
189 compatible = "snps,dw-apb-uart";
190 reg = <0x01c28c00 0x400>;
191 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
192 reg-shift = <2>;
193 reg-io-width = <4>;
194 clocks = <&ccu 70>;
195 resets = <&ccu 49>;
196 status = "disabled";
197 };
198
199 uart4: serial@1c29000 {
200 compatible = "snps,dw-apb-uart";
201 reg = <0x01c29000 0x400>;
202 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
203 reg-shift = <2>;
204 reg-io-width = <4>;
205 clocks = <&ccu 71>;
206 resets = <&ccu 50>;
207 status = "disabled";
208 };
209
210 i2c0: i2c@1c2ac00 {
211 compatible = "allwinner,sun6i-a31-i2c";
212 reg = <0x01c2ac00 0x400>;
213 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&ccu 63>;
215 resets = <&ccu 42>;
216 status = "disabled";
217 #address-cells = <1>;
218 #size-cells = <0>;
219 };
220
221 i2c1: i2c@1c2b000 {
222 compatible = "allwinner,sun6i-a31-i2c";
223 reg = <0x01c2b000 0x400>;
224 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&ccu 64>;
226 resets = <&ccu 43>;
227 status = "disabled";
228 #address-cells = <1>;
229 #size-cells = <0>;
230 };
231
232 i2c2: i2c@1c2b400 {
233 compatible = "allwinner,sun6i-a31-i2c";
234 reg = <0x01c2b400 0x400>;
235 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&ccu 65>;
237 resets = <&ccu 44>;
238 status = "disabled";
239 #address-cells = <1>;
240 #size-cells = <0>;
241 };
242
243 gic: interrupt-controller@1c81000 {
244 compatible = "arm,gic-400";
245 reg = <0x01c81000 0x1000>,
246 <0x01c82000 0x2000>,
247 <0x01c84000 0x2000>,
248 <0x01c86000 0x2000>;
249 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
250 interrupt-controller;
251 #interrupt-cells = <3>;
252 };
253
254 rtc: rtc@1f00000 {
255 compatible = "allwinner,sun6i-a31-rtc";
256 reg = <0x01f00000 0x54>;
257 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
259 };
260 };
261};
diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index 47ec703cb230..0d7bfbf7d922 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -1,9 +1,17 @@
1dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb
1dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb 2dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb
2dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p200.dtb 3dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p200.dtb
3dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p201.dtb 4dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p201.dtb
4dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb 5dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb
5dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb 6dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb
6dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb 7dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb
8dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb
9dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
10dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb
11dtb-$(CONFIG_ARCH_MESON) += meson-gxl-nexbox-a95x.dtb
12dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q200.dtb
13dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q201.dtb
14dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb
7 15
8always := $(dtb-y) 16always := $(dtb-y)
9subdir-y := $(dts-dirs) 17subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
new file mode 100644
index 000000000000..7a078bef04cd
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
@@ -0,0 +1,190 @@
1/*
2 * Copyright (c) 2016 Endless Computers, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44/* Common DTSI for same Amlogic Q200/Q201 and P230/P231 boards using either
45 * the pin-compatible S912 (GXM) or S905D (GXL) SoCs.
46 */
47
48/ {
49 aliases {
50 serial0 = &uart_AO;
51 };
52
53 chosen {
54 stdout-path = "serial0:115200n8";
55 };
56
57 memory@0 {
58 device_type = "memory";
59 reg = <0x0 0x0 0x0 0x80000000>;
60 };
61
62 vddio_boot: regulator-vddio_boot {
63 compatible = "regulator-fixed";
64 regulator-name = "VDDIO_BOOT";
65 regulator-min-microvolt = <1800000>;
66 regulator-max-microvolt = <1800000>;
67 };
68
69 vddao_3v3: regulator-vddao_3v3 {
70 compatible = "regulator-fixed";
71 regulator-name = "VDDAO_3V3";
72 regulator-min-microvolt = <3300000>;
73 regulator-max-microvolt = <3300000>;
74 };
75
76 vcc_3v3: regulator-vcc_3v3 {
77 compatible = "regulator-fixed";
78 regulator-name = "VCC_3V3";
79 regulator-min-microvolt = <3300000>;
80 regulator-max-microvolt = <3300000>;
81 };
82
83 emmc_pwrseq: emmc-pwrseq {
84 compatible = "mmc-pwrseq-emmc";
85 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
86 };
87
88 wifi32k: wifi32k {
89 compatible = "pwm-clock";
90 #clock-cells = <0>;
91 clock-frequency = <32768>;
92 pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
93 };
94
95 sdio_pwrseq: sdio-pwrseq {
96 compatible = "mmc-pwrseq-simple";
97 reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
98 clocks = <&wifi32k>;
99 clock-names = "ext_clock";
100 };
101};
102
103/* This UART is brought out to the DB9 connector */
104&uart_AO {
105 status = "okay";
106 pinctrl-0 = <&uart_ao_a_pins>;
107 pinctrl-names = "default";
108};
109
110&ir {
111 status = "okay";
112 pinctrl-0 = <&remote_input_ao_pins>;
113 pinctrl-names = "default";
114};
115
116/* Wireless SDIO Module */
117&sd_emmc_a {
118 status = "okay";
119 pinctrl-0 = <&sdio_pins>;
120 pinctrl-names = "default";
121 #address-cells = <1>;
122 #size-cells = <0>;
123
124 bus-width = <4>;
125 cap-sd-highspeed;
126 max-frequency = <100000000>;
127
128 non-removable;
129 disable-wp;
130
131 mmc-pwrseq = <&sdio_pwrseq>;
132
133 vmmc-supply = <&vddao_3v3>;
134 vqmmc-supply = <&vddio_boot>;
135
136 brcmf: bcrmf@1 {
137 reg = <1>;
138 compatible = "brcm,bcm4329-fmac";
139 };
140};
141
142/* SD card */
143&sd_emmc_b {
144 status = "okay";
145 pinctrl-0 = <&sdcard_pins>;
146 pinctrl-names = "default";
147
148 bus-width = <4>;
149 cap-sd-highspeed;
150 max-frequency = <100000000>;
151 disable-wp;
152
153 cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
154 cd-inverted;
155
156 vmmc-supply = <&vddao_3v3>;
157 vqmmc-supply = <&vddio_boot>;
158};
159
160/* eMMC */
161&sd_emmc_c {
162 status = "okay";
163 pinctrl-0 = <&emmc_pins>;
164 pinctrl-names = "default";
165
166 bus-width = <8>;
167 cap-sd-highspeed;
168 cap-mmc-highspeed;
169 max-frequency = <200000000>;
170 non-removable;
171 disable-wp;
172 mmc-ddr-1_8v;
173 mmc-hs200-1_8v;
174
175 mmc-pwrseq = <&emmc_pwrseq>;
176 vmmc-supply = <&vcc_3v3>;
177 vqmmc-supply = <&vddio_boot>;
178};
179
180&pwm_ef {
181 status = "okay";
182 pinctrl-0 = <&pwm_e_pins>;
183 pinctrl-names = "default";
184 clocks = <&clkc CLKID_FCLK_DIV4>;
185 clock-names = "clkin0";
186};
187
188&ethmac {
189 status = "okay";
190};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
new file mode 100644
index 000000000000..fc033c0d2a0f
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -0,0 +1,360 @@
1/*
2 * Copyright (c) 2016 Andreas Färber
3 *
4 * Copyright (c) 2016 BayLibre, SAS.
5 * Author: Neil Armstrong <narmstrong@baylibre.com>
6 *
7 * Copyright (c) 2016 Endless Computers, Inc.
8 * Author: Carlo Caione <carlo@endlessm.com>
9 *
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
12 * licensing only applies to this file, and not this project as a
13 * whole.
14 *
15 * a) This library is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of the
18 * License, or (at your option) any later version.
19 *
20 * This library is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * Or, alternatively,
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use,
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
47 */
48
49#include <dt-bindings/gpio/gpio.h>
50#include <dt-bindings/interrupt-controller/irq.h>
51#include <dt-bindings/interrupt-controller/arm-gic.h>
52
53/ {
54 interrupt-parent = <&gic>;
55 #address-cells = <2>;
56 #size-cells = <2>;
57
58 cpus {
59 #address-cells = <0x2>;
60 #size-cells = <0x0>;
61
62 cpu0: cpu@0 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a53", "arm,armv8";
65 reg = <0x0 0x0>;
66 enable-method = "psci";
67 next-level-cache = <&l2>;
68 };
69
70 cpu1: cpu@1 {
71 device_type = "cpu";
72 compatible = "arm,cortex-a53", "arm,armv8";
73 reg = <0x0 0x1>;
74 enable-method = "psci";
75 next-level-cache = <&l2>;
76 };
77
78 cpu2: cpu@2 {
79 device_type = "cpu";
80 compatible = "arm,cortex-a53", "arm,armv8";
81 reg = <0x0 0x2>;
82 enable-method = "psci";
83 next-level-cache = <&l2>;
84 };
85
86 cpu3: cpu@3 {
87 device_type = "cpu";
88 compatible = "arm,cortex-a53", "arm,armv8";
89 reg = <0x0 0x3>;
90 enable-method = "psci";
91 next-level-cache = <&l2>;
92 };
93
94 l2: l2-cache0 {
95 compatible = "cache";
96 };
97 };
98
99 arm-pmu {
100 compatible = "arm,cortex-a53-pmu";
101 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
105 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
106 };
107
108 psci {
109 compatible = "arm,psci-0.2";
110 method = "smc";
111 };
112
113 timer {
114 compatible = "arm,armv8-timer";
115 interrupts = <GIC_PPI 13
116 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
117 <GIC_PPI 14
118 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
119 <GIC_PPI 11
120 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
121 <GIC_PPI 10
122 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
123 };
124
125 xtal: xtal-clk {
126 compatible = "fixed-clock";
127 clock-frequency = <24000000>;
128 clock-output-names = "xtal";
129 #clock-cells = <0>;
130 };
131
132 firmware {
133 sm: secure-monitor {
134 compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
135 };
136 };
137
138 efuse: efuse {
139 compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
140 #address-cells = <1>;
141 #size-cells = <1>;
142
143 sn: sn@14 {
144 reg = <0x14 0x10>;
145 };
146
147 eth_mac: eth_mac@34 {
148 reg = <0x34 0x10>;
149 };
150
151 bid: bid@46 {
152 reg = <0x46 0x30>;
153 };
154 };
155
156 soc {
157 compatible = "simple-bus";
158 #address-cells = <2>;
159 #size-cells = <2>;
160 ranges;
161
162 cbus: cbus@c1100000 {
163 compatible = "simple-bus";
164 reg = <0x0 0xc1100000 0x0 0x100000>;
165 #address-cells = <2>;
166 #size-cells = <2>;
167 ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
168
169 reset: reset-controller@4404 {
170 compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
171 reg = <0x0 0x04404 0x0 0x20>;
172 #reset-cells = <1>;
173 };
174
175 uart_A: serial@84c0 {
176 compatible = "amlogic,meson-uart";
177 reg = <0x0 0x84c0 0x0 0x14>;
178 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
179 clocks = <&xtal>;
180 status = "disabled";
181 };
182
183 uart_B: serial@84dc {
184 compatible = "amlogic,meson-uart";
185 reg = <0x0 0x84dc 0x0 0x14>;
186 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
187 clocks = <&xtal>;
188 status = "disabled";
189 };
190
191 i2c_A: i2c@8500 {
192 compatible = "amlogic,meson-gxbb-i2c";
193 reg = <0x0 0x08500 0x0 0x20>;
194 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
195 #address-cells = <1>;
196 #size-cells = <0>;
197 status = "disabled";
198 };
199
200 pwm_ab: pwm@8550 {
201 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
202 reg = <0x0 0x08550 0x0 0x10>;
203 #pwm-cells = <3>;
204 status = "disabled";
205 };
206
207 pwm_cd: pwm@8650 {
208 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
209 reg = <0x0 0x08650 0x0 0x10>;
210 #pwm-cells = <3>;
211 status = "disabled";
212 };
213
214 pwm_ef: pwm@86c0 {
215 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
216 reg = <0x0 0x086c0 0x0 0x10>;
217 #pwm-cells = <3>;
218 status = "disabled";
219 };
220
221 uart_C: serial@8700 {
222 compatible = "amlogic,meson-uart";
223 reg = <0x0 0x8700 0x0 0x14>;
224 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
225 clocks = <&xtal>;
226 status = "disabled";
227 };
228
229 i2c_B: i2c@87c0 {
230 compatible = "amlogic,meson-gxbb-i2c";
231 reg = <0x0 0x087c0 0x0 0x20>;
232 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
233 #address-cells = <1>;
234 #size-cells = <0>;
235 status = "disabled";
236 };
237
238 i2c_C: i2c@87e0 {
239 compatible = "amlogic,meson-gxbb-i2c";
240 reg = <0x0 0x087e0 0x0 0x20>;
241 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
242 #address-cells = <1>;
243 #size-cells = <0>;
244 status = "disabled";
245 };
246
247 watchdog@98d0 {
248 compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt";
249 reg = <0x0 0x098d0 0x0 0x10>;
250 clocks = <&xtal>;
251 };
252 };
253
254 gic: interrupt-controller@c4301000 {
255 compatible = "arm,gic-400";
256 reg = <0x0 0xc4301000 0 0x1000>,
257 <0x0 0xc4302000 0 0x2000>,
258 <0x0 0xc4304000 0 0x2000>,
259 <0x0 0xc4306000 0 0x2000>;
260 interrupt-controller;
261 interrupts = <GIC_PPI 9
262 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
263 #interrupt-cells = <3>;
264 #address-cells = <0>;
265 };
266
267 aobus: aobus@c8100000 {
268 compatible = "simple-bus";
269 reg = <0x0 0xc8100000 0x0 0x100000>;
270 #address-cells = <2>;
271 #size-cells = <2>;
272 ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
273
274 uart_AO: serial@4c0 {
275 compatible = "amlogic,meson-uart";
276 reg = <0x0 0x004c0 0x0 0x14>;
277 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
278 clocks = <&xtal>;
279 status = "disabled";
280 };
281
282 ir: ir@580 {
283 compatible = "amlogic,meson-gxbb-ir";
284 reg = <0x0 0x00580 0x0 0x40>;
285 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
286 status = "disabled";
287 };
288 };
289
290 periphs: periphs@c8834000 {
291 compatible = "simple-bus";
292 reg = <0x0 0xc8834000 0x0 0x2000>;
293 #address-cells = <2>;
294 #size-cells = <2>;
295 ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
296
297 rng {
298 compatible = "amlogic,meson-rng";
299 reg = <0x0 0x0 0x0 0x4>;
300 };
301 };
302
303
304 hiubus: hiubus@c883c000 {
305 compatible = "simple-bus";
306 reg = <0x0 0xc883c000 0x0 0x2000>;
307 #address-cells = <2>;
308 #size-cells = <2>;
309 ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
310
311 mailbox: mailbox@404 {
312 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
313 reg = <0 0x404 0 0x4c>;
314 interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
315 <0 209 IRQ_TYPE_EDGE_RISING>,
316 <0 210 IRQ_TYPE_EDGE_RISING>;
317 #mbox-cells = <1>;
318 };
319 };
320
321 ethmac: ethernet@c9410000 {
322 compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac";
323 reg = <0x0 0xc9410000 0x0 0x10000
324 0x0 0xc8834540 0x0 0x4>;
325 interrupts = <0 8 1>;
326 interrupt-names = "macirq";
327 phy-mode = "rgmii";
328 status = "disabled";
329 };
330
331 apb: apb@d0000000 {
332 compatible = "simple-bus";
333 reg = <0x0 0xd0000000 0x0 0x200000>;
334 #address-cells = <2>;
335 #size-cells = <2>;
336 ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
337
338 sd_emmc_a: mmc@70000 {
339 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
340 reg = <0x0 0x70000 0x0 0x2000>;
341 interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
342 status = "disabled";
343 };
344
345 sd_emmc_b: mmc@72000 {
346 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
347 reg = <0x0 0x72000 0x0 0x2000>;
348 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
349 status = "disabled";
350 };
351
352 sd_emmc_c: mmc@74000 {
353 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
354 reg = <0x0 0x74000 0x0 0x2000>;
355 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
356 status = "disabled";
357 };
358 };
359 };
360};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
new file mode 100644
index 000000000000..969682092e0f
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
@@ -0,0 +1,231 @@
1/*
2 * Copyright (c) 2016 Andreas Färber
3 * Copyright (c) 2016 BayLibre, Inc.
4 * Author: Neil Armstrong <narmstrong@kernel.org>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45/dts-v1/;
46
47#include "meson-gxbb.dtsi"
48#include <dt-bindings/gpio/gpio.h>
49#include <dt-bindings/input/input.h>
50
51/ {
52 compatible = "nexbox,a95x", "amlogic,meson-gxbb";
53 model = "NEXBOX A95X";
54
55 aliases {
56 serial0 = &uart_AO;
57 };
58
59 chosen {
60 stdout-path = "serial0:115200n8";
61 };
62
63 memory@0 {
64 device_type = "memory";
65 reg = <0x0 0x0 0x0 0x40000000>;
66 };
67
68 leds {
69 compatible = "gpio-leds";
70 blue {
71 label = "a95x:system-status";
72 gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>;
73 linux,default-trigger = "heartbeat";
74 default-state = "off";
75 };
76 };
77
78 gpio-keys-polled {
79 compatible = "gpio-keys-polled";
80 #address-cells = <1>;
81 #size-cells = <0>;
82 poll-interval = <100>;
83
84 button@0 {
85 label = "reset";
86 linux,code = <KEY_RESTART>;
87 gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
88 };
89 };
90
91 vddio_card: gpio-regulator {
92 compatible = "regulator-gpio";
93
94 regulator-name = "VDDIO_CARD";
95 regulator-min-microvolt = <1800000>;
96 regulator-max-microvolt = <3300000>;
97
98 gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
99 gpios-states = <1>;
100
101 /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */
102 states = <1800000 0
103 3300000 1>;
104 };
105
106 vddio_boot: regulator-vddio_boot {
107 compatible = "regulator-fixed";
108 regulator-name = "VDDIO_BOOT";
109 regulator-min-microvolt = <1800000>;
110 regulator-max-microvolt = <1800000>;
111 };
112
113 vddao_3v3: regulator-vddao_3v3 {
114 compatible = "regulator-fixed";
115 regulator-name = "VDDAO_3V3";
116 regulator-min-microvolt = <3300000>;
117 regulator-max-microvolt = <3300000>;
118 };
119
120 vcc_3v3: regulator-vcc_3v3 {
121 compatible = "regulator-fixed";
122 regulator-name = "VCC_3V3";
123 regulator-min-microvolt = <3300000>;
124 regulator-max-microvolt = <3300000>;
125 };
126
127 emmc_pwrseq: emmc-pwrseq {
128 compatible = "mmc-pwrseq-emmc";
129 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
130 };
131
132 wifi32k: wifi32k {
133 compatible = "pwm-clock";
134 #clock-cells = <0>;
135 clock-frequency = <32768>;
136 pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
137 };
138
139 sdio_pwrseq: sdio-pwrseq {
140 compatible = "mmc-pwrseq-simple";
141 reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
142 clocks = <&wifi32k>;
143 clock-names = "ext_clock";
144 };
145};
146
147&uart_AO {
148 status = "okay";
149 pinctrl-0 = <&uart_ao_a_pins>;
150 pinctrl-names = "default";
151};
152
153&ethmac {
154 status = "okay";
155 pinctrl-0 = <&eth_rmii_pins>;
156 pinctrl-names = "default";
157 phy-mode = "rmii";
158};
159
160&ir {
161 status = "okay";
162 pinctrl-0 = <&remote_input_ao_pins>;
163 pinctrl-names = "default";
164};
165
166/* Wireless SDIO Module */
167&sd_emmc_a {
168 status = "okay";
169 pinctrl-0 = <&sdio_pins>;
170 pinctrl-names = "default";
171 #address-cells = <1>;
172 #size-cells = <0>;
173
174 bus-width = <4>;
175 cap-sd-highspeed;
176 max-frequency = <100000000>;
177
178 non-removable;
179 disable-wp;
180
181 mmc-pwrseq = <&sdio_pwrseq>;
182
183 vmmc-supply = <&vddao_3v3>;
184 vqmmc-supply = <&vddio_boot>;
185};
186
187/* SD card */
188&sd_emmc_b {
189 status = "okay";
190 pinctrl-0 = <&sdcard_pins>;
191 pinctrl-names = "default";
192
193 bus-width = <4>;
194 cap-sd-highspeed;
195 max-frequency = <100000000>;
196 disable-wp;
197
198 cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
199 cd-inverted;
200
201 vmmc-supply = <&vddao_3v3>;
202 vqmmc-supply = <&vddio_card>;
203};
204
205/* eMMC */
206&sd_emmc_c {
207 status = "okay";
208 pinctrl-0 = <&emmc_pins>;
209 pinctrl-names = "default";
210
211 bus-width = <8>;
212 cap-sd-highspeed;
213 cap-mmc-highspeed;
214 max-frequency = <200000000>;
215 non-removable;
216 disable-wp;
217 mmc-ddr-1_8v;
218 mmc-hs200-1_8v;
219
220 mmc-pwrseq = <&emmc_pwrseq>;
221 vmmc-supply = <&vcc_3v3>;
222 vqmmc-supply = <&vddio_boot>;
223};
224
225&pwm_ef {
226 status = "okay";
227 pinctrl-0 = <&pwm_e_pins>;
228 pinctrl-names = "default";
229 clocks = <&clkc CLKID_FCLK_DIV4>;
230 clock-names = "clkin0";
231};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
index e6e3491d48a5..238fbeacd330 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
@@ -64,6 +64,18 @@
64 reg = <0x0 0x0 0x0 0x80000000>; 64 reg = <0x0 0x0 0x0 0x80000000>;
65 }; 65 };
66 66
67 usb_otg_pwr: regulator-usb-pwrs {
68 compatible = "regulator-fixed";
69
70 regulator-name = "USB_OTG_PWR";
71
72 regulator-min-microvolt = <5000000>;
73 regulator-max-microvolt = <5000000>;
74
75 gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
76 enable-active-high;
77 };
78
67 leds { 79 leds {
68 compatible = "gpio-leds"; 80 compatible = "gpio-leds";
69 blue { 81 blue {
@@ -73,6 +85,56 @@
73 default-state = "off"; 85 default-state = "off";
74 }; 86 };
75 }; 87 };
88
89 tflash_vdd: regulator-tflash_vdd {
90 /*
91 * signal name from schematics: TFLASH_VDD_EN
92 */
93 compatible = "regulator-fixed";
94
95 regulator-name = "TFLASH_VDD";
96 regulator-min-microvolt = <3300000>;
97 regulator-max-microvolt = <3300000>;
98
99 gpio = <&gpio_ao GPIOAO_12 GPIO_ACTIVE_HIGH>;
100 enable-active-high;
101 };
102
103 tf_io: gpio-regulator-tf_io {
104 compatible = "regulator-gpio";
105
106 regulator-name = "TF_IO";
107 regulator-min-microvolt = <1800000>;
108 regulator-max-microvolt = <3300000>;
109
110 /*
111 * signal name from schematics: TF_3V3N_1V8_EN
112 */
113 gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
114 gpios-states = <0>;
115
116 states = <3300000 0
117 1800000 1>;
118 };
119
120 vcc1v8: regulator-vcc1v8 {
121 compatible = "regulator-fixed";
122 regulator-name = "VCC1V8";
123 regulator-min-microvolt = <1800000>;
124 regulator-max-microvolt = <1800000>;
125 };
126
127 vcc3v3: regulator-vcc3v3 {
128 compatible = "regulator-fixed";
129 regulator-name = "VCC3V3";
130 regulator-min-microvolt = <3300000>;
131 regulator-max-microvolt = <3300000>;
132 };
133
134 emmc_pwrseq: emmc-pwrseq {
135 compatible = "mmc-pwrseq-emmc";
136 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
137 };
76}; 138};
77 139
78&uart_AO { 140&uart_AO {
@@ -83,7 +145,7 @@
83 145
84&ethmac { 146&ethmac {
85 status = "okay"; 147 status = "okay";
86 pinctrl-0 = <&eth_pins>; 148 pinctrl-0 = <&eth_rgmii_pins>;
87 pinctrl-names = "default"; 149 pinctrl-names = "default";
88}; 150};
89 151
@@ -98,3 +160,58 @@
98 pinctrl-0 = <&i2c_a_pins>; 160 pinctrl-0 = <&i2c_a_pins>;
99 pinctrl-names = "default"; 161 pinctrl-names = "default";
100}; 162};
163
164&usb0_phy {
165 status = "okay";
166 phy-supply = <&usb_otg_pwr>;
167};
168
169&usb1_phy {
170 status = "okay";
171};
172
173&usb0 {
174 status = "okay";
175};
176
177&usb1 {
178 status = "okay";
179};
180
181/* SD */
182&sd_emmc_b {
183 status = "okay";
184 pinctrl-0 = <&sdcard_pins>;
185 pinctrl-names = "default";
186
187 bus-width = <4>;
188 cap-sd-highspeed;
189 max-frequency = <100000000>;
190 disable-wp;
191
192 cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
193 cd-inverted;
194
195 vmmc-supply = <&tflash_vdd>;
196 vqmmc-supply = <&tf_io>;
197};
198
199/* eMMC */
200&sd_emmc_c {
201 status = "okay";
202 pinctrl-0 = <&emmc_pins>;
203 pinctrl-names = "default";
204
205 bus-width = <8>;
206 cap-sd-highspeed;
207 max-frequency = <200000000>;
208 non-removable;
209 disable-wp;
210 cap-mmc-highspeed;
211 mmc-ddr-1_8v;
212 mmc-hs200-1_8v;
213
214 mmc-pwrseq = <&emmc_pwrseq>;
215 vmmc-supply = <&vcc3v3>;
216 vqmmc-supply = <&vcc1v8>;
217};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
index 06a34dc6002f..203be28978d5 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
@@ -70,6 +70,61 @@
70 gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; 70 gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
71 enable-active-high; 71 enable-active-high;
72 }; 72 };
73
74 vddio_card: gpio-regulator {
75 compatible = "regulator-gpio";
76
77 regulator-name = "VDDIO_CARD";
78 regulator-min-microvolt = <1800000>;
79 regulator-max-microvolt = <3300000>;
80
81 gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
82 gpios-states = <1>;
83
84 /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */
85 states = <1800000 0
86 3300000 1>;
87 };
88
89 vddio_boot: regulator-vddio_boot {
90 compatible = "regulator-fixed";
91 regulator-name = "VDDIO_BOOT";
92 regulator-min-microvolt = <1800000>;
93 regulator-max-microvolt = <1800000>;
94 };
95
96 vddao_3v3: regulator-vddao_3v3 {
97 compatible = "regulator-fixed";
98 regulator-name = "VDDAO_3V3";
99 regulator-min-microvolt = <3300000>;
100 regulator-max-microvolt = <3300000>;
101 };
102
103 vcc_3v3: regulator-vcc_3v3 {
104 compatible = "regulator-fixed";
105 regulator-name = "VCC_3V3";
106 regulator-min-microvolt = <3300000>;
107 regulator-max-microvolt = <3300000>;
108 };
109
110 emmc_pwrseq: emmc-pwrseq {
111 compatible = "mmc-pwrseq-emmc";
112 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
113 };
114
115 wifi32k: wifi32k {
116 compatible = "pwm-clock";
117 #clock-cells = <0>;
118 clock-frequency = <32768>;
119 pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
120 };
121
122 sdio_pwrseq: sdio-pwrseq {
123 compatible = "mmc-pwrseq-simple";
124 reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
125 clocks = <&wifi32k>;
126 clock-names = "ext_clock";
127 };
73}; 128};
74 129
75/* This UART is brought out to the DB9 connector */ 130/* This UART is brought out to the DB9 connector */
@@ -81,7 +136,7 @@
81 136
82&ethmac { 137&ethmac {
83 status = "okay"; 138 status = "okay";
84 pinctrl-0 = <&eth_pins>; 139 pinctrl-0 = <&eth_rgmii_pins>;
85 pinctrl-names = "default"; 140 pinctrl-names = "default";
86}; 141};
87 142
@@ -107,3 +162,75 @@
107&usb1 { 162&usb1 {
108 status = "okay"; 163 status = "okay";
109}; 164};
165
166/* Wireless SDIO Module */
167&sd_emmc_a {
168 status = "okay";
169 pinctrl-0 = <&sdio_pins>;
170 pinctrl-names = "default";
171 #address-cells = <1>;
172 #size-cells = <0>;
173
174 bus-width = <4>;
175 cap-sd-highspeed;
176 max-frequency = <100000000>;
177
178 non-removable;
179 disable-wp;
180
181 mmc-pwrseq = <&sdio_pwrseq>;
182
183 vmmc-supply = <&vddao_3v3>;
184 vqmmc-supply = <&vddio_boot>;
185
186 brcmf: bcrmf@1 {
187 reg = <1>;
188 compatible = "brcm,bcm4329-fmac";
189 };
190};
191
192/* SD card */
193&sd_emmc_b {
194 status = "okay";
195 pinctrl-0 = <&sdcard_pins>;
196 pinctrl-names = "default";
197
198 bus-width = <4>;
199 cap-sd-highspeed;
200 max-frequency = <100000000>;
201 disable-wp;
202
203 cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
204 cd-inverted;
205
206 vmmc-supply = <&vddao_3v3>;
207 vqmmc-supply = <&vddio_card>;
208};
209
210/* eMMC */
211&sd_emmc_c {
212 status = "okay";
213 pinctrl-0 = <&emmc_pins>;
214 pinctrl-names = "default";
215
216 bus-width = <8>;
217 cap-sd-highspeed;
218 cap-mmc-highspeed;
219 max-frequency = <200000000>;
220 non-removable;
221 disable-wp;
222 mmc-ddr-1_8v;
223 mmc-hs200-1_8v;
224
225 mmc-pwrseq = <&emmc_pwrseq>;
226 vmmc-supply = <&vcc_3v3>;
227 vqmmc-supply = <&vddio_boot>;
228};
229
230&pwm_ef {
231 status = "okay";
232 pinctrl-0 = <&pwm_e_pins>;
233 pinctrl-names = "default";
234 clocks = <&clkc CLKID_FCLK_DIV4>;
235 clock-names = "clkin0";
236};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
index 73f159370188..e59ad308192f 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
@@ -65,6 +65,39 @@
65 enable-active-high; 65 enable-active-high;
66 }; 66 };
67 67
68 vcc_3v3: regulator-vcc_3v3 {
69 compatible = "regulator-fixed";
70 regulator-name = "VCC_3V3";
71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <3300000>;
73 };
74
75 vcc_1v8: regulator-vcc_1v8 {
76 compatible = "regulator-fixed";
77 regulator-name = "VCC_1V8";
78 regulator-min-microvolt = <1800000>;
79 regulator-max-microvolt = <1800000>;
80 };
81
82 emmc_pwrseq: emmc-pwrseq {
83 compatible = "mmc-pwrseq-emmc";
84 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
85 };
86
87 wifi32k: wifi32k {
88 compatible = "pwm-clock";
89 #clock-cells = <0>;
90 clock-frequency = <32768>;
91 pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
92 };
93
94 sdio_pwrseq: sdio-pwrseq {
95 compatible = "mmc-pwrseq-simple";
96 reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>,
97 <&gpio GPIOX_20 GPIO_ACTIVE_LOW>;
98 clocks = <&wifi32k>;
99 clock-names = "ext_clock";
100 };
68}; 101};
69 102
70&uart_AO { 103&uart_AO {
@@ -82,7 +115,7 @@
82 115
83&ethmac { 116&ethmac {
84 status = "okay"; 117 status = "okay";
85 pinctrl-0 = <&eth_pins>; 118 pinctrl-0 = <&eth_rgmii_pins>;
86 pinctrl-names = "default"; 119 pinctrl-names = "default";
87}; 120};
88 121
@@ -102,3 +135,74 @@
102&usb1 { 135&usb1 {
103 status = "okay"; 136 status = "okay";
104}; 137};
138
139/* Wireless SDIO Module */
140&sd_emmc_a {
141 status = "okay";
142 pinctrl-0 = <&sdio_pins &sdio_irq_pins>;
143 pinctrl-names = "default";
144 #address-cells = <1>;
145 #size-cells = <0>;
146
147 bus-width = <4>;
148 cap-sd-highspeed;
149 max-frequency = <100000000>;
150
151 non-removable;
152 disable-wp;
153
154 mmc-pwrseq = <&sdio_pwrseq>;
155
156 vmmc-supply = <&vcc_3v3>;
157 vqmmc-supply = <&vcc_1v8>;
158
159 brcmf: bcrmf@1 {
160 reg = <1>;
161 compatible = "brcm,bcm4329-fmac";
162 };
163};
164
165/* SD card */
166&sd_emmc_b {
167 status = "okay";
168 pinctrl-0 = <&sdcard_pins>;
169 pinctrl-names = "default";
170
171 bus-width = <4>;
172 cap-sd-highspeed;
173 max-frequency = <100000000>;
174 disable-wp;
175
176 cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
177 cd-inverted;
178
179 vmmc-supply = <&vcc_3v3>;
180};
181
182/* eMMC */
183&sd_emmc_c {
184 status = "okay";
185 pinctrl-0 = <&emmc_pins>;
186 pinctrl-names = "default";
187
188 bus-width = <8>;
189 cap-sd-highspeed;
190 cap-mmc-highspeed;
191 max-frequency = <200000000>;
192 non-removable;
193 disable-wp;
194 mmc-ddr-1_8v;
195 mmc-hs200-1_8v;
196
197 mmc-pwrseq = <&emmc_pwrseq>;
198 vmmc-supply = <&vcc_3v3>;
199 vmmcq-sumpply = <&vcc_1v8>;
200};
201
202&pwm_ef {
203 status = "okay";
204 pinctrl-0 = <&pwm_e_pins>;
205 pinctrl-names = "default";
206 clocks = <&clkc CLKID_FCLK_DIV4>;
207 clock-names = "clkin0";
208};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 610e0e1c3cee..51edd5b5c460 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -40,9 +40,7 @@
40 * OTHER DEALINGS IN THE SOFTWARE. 40 * OTHER DEALINGS IN THE SOFTWARE.
41 */ 41 */
42 42
43#include <dt-bindings/gpio/gpio.h> 43#include "meson-gx.dtsi"
44#include <dt-bindings/interrupt-controller/irq.h>
45#include <dt-bindings/interrupt-controller/arm-gic.h>
46#include <dt-bindings/gpio/meson-gxbb-gpio.h> 44#include <dt-bindings/gpio/meson-gxbb-gpio.h>
47#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> 45#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
48#include <dt-bindings/clock/gxbb-clkc.h> 46#include <dt-bindings/clock/gxbb-clkc.h>
@@ -51,106 +49,30 @@
51 49
52/ { 50/ {
53 compatible = "amlogic,meson-gxbb"; 51 compatible = "amlogic,meson-gxbb";
54 interrupt-parent = <&gic>;
55 #address-cells = <2>;
56 #size-cells = <2>;
57 52
58 cpus { 53 scpi {
59 #address-cells = <0x2>; 54 compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
60 #size-cells = <0x0>; 55 mboxes = <&mailbox 1 &mailbox 2>;
56 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
61 57
62 cpu0: cpu@0 { 58 clocks {
63 device_type = "cpu"; 59 compatible = "arm,scpi-clocks";
64 compatible = "arm,cortex-a53", "arm,armv8";
65 reg = <0x0 0x0>;
66 enable-method = "psci";
67 };
68
69 cpu1: cpu@1 {
70 device_type = "cpu";
71 compatible = "arm,cortex-a53", "arm,armv8";
72 reg = <0x0 0x1>;
73 enable-method = "psci";
74 };
75
76 cpu2: cpu@2 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a53", "arm,armv8";
79 reg = <0x0 0x2>;
80 enable-method = "psci";
81 };
82
83 cpu3: cpu@3 {
84 device_type = "cpu";
85 compatible = "arm,cortex-a53", "arm,armv8";
86 reg = <0x0 0x3>;
87 enable-method = "psci";
88 };
89 };
90
91 arm-pmu {
92 compatible = "arm,cortex-a53-pmu";
93 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
97 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
98 };
99 60
100 psci { 61 scpi_dvfs: scpi_clocks@0 {
101 compatible = "arm,psci-0.2"; 62 compatible = "arm,scpi-dvfs-clocks";
102 method = "smc"; 63 #clock-cells = <1>;
103 }; 64 clock-indices = <0>;
104 65 clock-output-names = "vcpu";
105 firmware { 66 };
106 sm: secure-monitor {
107 compatible = "amlogic,meson-gxbb-sm";
108 };
109 };
110
111 efuse: efuse {
112 compatible = "amlogic,meson-gxbb-efuse";
113 #address-cells = <1>;
114 #size-cells = <1>;
115
116 sn: sn@14 {
117 reg = <0x14 0x10>;
118 };
119
120 eth_mac: eth_mac@34 {
121 reg = <0x34 0x10>;
122 }; 67 };
123 68
124 bid: bid@46 { 69 scpi_sensors: sensors {
125 reg = <0x46 0x30>; 70 compatible = "arm,scpi-sensors";
71 #thermal-sensor-cells = <1>;
126 }; 72 };
127 }; 73 };
128 74
129 timer {
130 compatible = "arm,armv8-timer";
131 interrupts = <GIC_PPI 13
132 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
133 <GIC_PPI 14
134 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
135 <GIC_PPI 11
136 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
137 <GIC_PPI 10
138 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
139 };
140
141 xtal: xtal-clk {
142 compatible = "fixed-clock";
143 clock-frequency = <24000000>;
144 clock-output-names = "xtal";
145 #clock-cells = <0>;
146 };
147
148 soc { 75 soc {
149 compatible = "simple-bus";
150 #address-cells = <2>;
151 #size-cells = <2>;
152 ranges;
153
154 usb0_phy: phy@c0000000 { 76 usb0_phy: phy@c0000000 {
155 compatible = "amlogic,meson-gxbb-usb2-phy"; 77 compatible = "amlogic,meson-gxbb-usb2-phy";
156 #phy-cells = <0>; 78 #phy-cells = <0>;
@@ -165,505 +87,422 @@
165 compatible = "amlogic,meson-gxbb-usb2-phy"; 87 compatible = "amlogic,meson-gxbb-usb2-phy";
166 #phy-cells = <0>; 88 #phy-cells = <0>;
167 reg = <0x0 0xc0000020 0x0 0x20>; 89 reg = <0x0 0xc0000020 0x0 0x20>;
90 resets = <&reset RESET_USB_OTG>;
168 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; 91 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
169 clock-names = "usb_general", "usb"; 92 clock-names = "usb_general", "usb";
170 status = "disabled"; 93 status = "disabled";
171 }; 94 };
172 95
173 cbus: cbus@c1100000 { 96 sram: sram@c8000000 {
174 compatible = "simple-bus"; 97 compatible = "amlogic,meson-gxbb-sram", "mmio-sram";
175 reg = <0x0 0xc1100000 0x0 0x100000>; 98 reg = <0x0 0xc8000000 0x0 0x14000>;
176 #address-cells = <2>;
177 #size-cells = <2>;
178 ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
179 99
180 reset: reset-controller@4404 { 100 #address-cells = <1>;
181 compatible = "amlogic,meson-gxbb-reset"; 101 #size-cells = <1>;
182 reg = <0x0 0x04404 0x0 0x20>; 102 ranges = <0 0x0 0xc8000000 0x14000>;
183 #reset-cells = <1>; 103
104 cpu_scp_lpri: scp-shmem@0 {
105 compatible = "amlogic,meson-gxbb-scp-shmem";
106 reg = <0x13000 0x400>;
107 };
108
109 cpu_scp_hpri: scp-shmem@200 {
110 compatible = "amlogic,meson-gxbb-scp-shmem";
111 reg = <0x13400 0x400>;
184 }; 112 };
113 };
114
115 usb0: usb@c9000000 {
116 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
117 reg = <0x0 0xc9000000 0x0 0x40000>;
118 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
119 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
120 clock-names = "otg";
121 phys = <&usb0_phy>;
122 phy-names = "usb2-phy";
123 dr_mode = "host";
124 status = "disabled";
125 };
126
127 usb1: usb@c9100000 {
128 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
129 reg = <0x0 0xc9100000 0x0 0x40000>;
130 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
131 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
132 clock-names = "otg";
133 phys = <&usb1_phy>;
134 phy-names = "usb2-phy";
135 dr_mode = "host";
136 status = "disabled";
137 };
138 };
139};
140
141&cpu0 {
142 clocks = <&scpi_dvfs 0>;
143};
144
145&cpu1 {
146 clocks = <&scpi_dvfs 0>;
147};
148
149&cpu2 {
150 clocks = <&scpi_dvfs 0>;
151};
152
153&cpu3 {
154 clocks = <&scpi_dvfs 0>;
155};
156
157&cbus {
158 spifc: spi@8c80 {
159 compatible = "amlogic,meson-gxbb-spifc";
160 reg = <0x0 0x08c80 0x0 0x80>;
161 #address-cells = <1>;
162 #size-cells = <0>;
163 clocks = <&clkc CLKID_SPI>;
164 status = "disabled";
165 };
166};
167
168&ethmac {
169 clocks = <&clkc CLKID_ETH>,
170 <&clkc CLKID_FCLK_DIV2>,
171 <&clkc CLKID_MPLL2>;
172 clock-names = "stmmaceth", "clkin0", "clkin1";
173};
174
175&aobus {
176 pinctrl_aobus: pinctrl@14 {
177 compatible = "amlogic,meson-gxbb-aobus-pinctrl";
178 #address-cells = <2>;
179 #size-cells = <2>;
180 ranges;
181
182 gpio_ao: bank@14 {
183 reg = <0x0 0x00014 0x0 0x8>,
184 <0x0 0x0002c 0x0 0x4>,
185 <0x0 0x00024 0x0 0x8>;
186 reg-names = "mux", "pull", "gpio";
187 gpio-controller;
188 #gpio-cells = <2>;
189 };
185 190
186 uart_A: serial@84c0 { 191 uart_ao_a_pins: uart_ao_a {
187 compatible = "amlogic,meson-uart"; 192 mux {
188 reg = <0x0 0x84c0 0x0 0x14>; 193 groups = "uart_tx_ao_a", "uart_rx_ao_a";
189 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 194 function = "uart_ao";
190 clocks = <&xtal>;
191 status = "disabled";
192 }; 195 };
196 };
193 197
194 uart_B: serial@84dc { 198 remote_input_ao_pins: remote_input_ao {
195 compatible = "amlogic,meson-uart"; 199 mux {
196 reg = <0x0 0x84dc 0x0 0x14>; 200 groups = "remote_input_ao";
197 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 201 function = "remote_input_ao";
198 clocks = <&xtal>;
199 status = "disabled";
200 }; 202 };
203 };
201 204
202 pwm_ab: pwm@8550 { 205 i2c_ao_pins: i2c_ao {
203 compatible = "amlogic,meson-gxbb-pwm"; 206 mux {
204 reg = <0x0 0x08550 0x0 0x10>; 207 groups = "i2c_sck_ao",
205 #pwm-cells = <3>; 208 "i2c_sda_ao";
206 status = "disabled"; 209 function = "i2c_ao";
207 }; 210 };
211 };
208 212
209 pwm_cd: pwm@8650 { 213 pwm_ao_a_3_pins: pwm_ao_a_3 {
210 compatible = "amlogic,meson-gxbb-pwm"; 214 mux {
211 reg = <0x0 0x08650 0x0 0x10>; 215 groups = "pwm_ao_a_3";
212 #pwm-cells = <3>; 216 function = "pwm_ao_a_3";
213 status = "disabled";
214 }; 217 };
218 };
215 219
216 pwm_ef: pwm@86c0 { 220 pwm_ao_a_6_pins: pwm_ao_a_6 {
217 compatible = "amlogic,meson-gxbb-pwm"; 221 mux {
218 reg = <0x0 0x086c0 0x0 0x10>; 222 groups = "pwm_ao_a_6";
219 #pwm-cells = <3>; 223 function = "pwm_ao_a_6";
220 status = "disabled";
221 }; 224 };
225 };
222 226
223 uart_C: serial@8700 { 227 pwm_ao_a_12_pins: pwm_ao_a_12 {
224 compatible = "amlogic,meson-uart"; 228 mux {
225 reg = <0x0 0x8700 0x0 0x14>; 229 groups = "pwm_ao_a_12";
226 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 230 function = "pwm_ao_a_12";
227 clocks = <&xtal>;
228 status = "disabled";
229 }; 231 };
232 };
230 233
231 watchdog@98d0 { 234 pwm_ao_b_pins: pwm_ao_b {
232 compatible = "amlogic,meson-gxbb-wdt"; 235 mux {
233 reg = <0x0 0x098d0 0x0 0x10>; 236 groups = "pwm_ao_b";
234 clocks = <&xtal>; 237 function = "pwm_ao_b";
235 }; 238 };
239 };
240 };
241
242 clkc_AO: clock-controller@040 {
243 compatible = "amlogic,gxbb-aoclkc";
244 reg = <0x0 0x00040 0x0 0x4>;
245 #clock-cells = <1>;
246 #reset-cells = <1>;
247 };
248
249 pwm_ab_AO: pwm@550 {
250 compatible = "amlogic,meson-gxbb-pwm";
251 reg = <0x0 0x0550 0x0 0x10>;
252 #pwm-cells = <3>;
253 status = "disabled";
254 };
255
256 i2c_AO: i2c@500 {
257 compatible = "amlogic,meson-gxbb-i2c";
258 reg = <0x0 0x500 0x0 0x20>;
259 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
260 clocks = <&clkc CLKID_AO_I2C>;
261 #address-cells = <1>;
262 #size-cells = <0>;
263 status = "disabled";
264 };
265};
266
267&periphs {
268 pinctrl_periphs: pinctrl@4b0 {
269 compatible = "amlogic,meson-gxbb-periphs-pinctrl";
270 #address-cells = <2>;
271 #size-cells = <2>;
272 ranges;
273
274 gpio: bank@4b0 {
275 reg = <0x0 0x004b0 0x0 0x28>,
276 <0x0 0x004e8 0x0 0x14>,
277 <0x0 0x00120 0x0 0x14>,
278 <0x0 0x00430 0x0 0x40>;
279 reg-names = "mux", "pull", "pull-enable", "gpio";
280 gpio-controller;
281 #gpio-cells = <2>;
282 };
236 283
237 spifc: spi@8c80 { 284 emmc_pins: emmc {
238 compatible = "amlogic,meson-gxbb-spifc"; 285 mux {
239 reg = <0x0 0x08c80 0x0 0x80>; 286 groups = "emmc_nand_d07",
240 #address-cells = <1>; 287 "emmc_cmd",
241 #size-cells = <0>; 288 "emmc_clk",
242 clocks = <&clkc CLKID_SPI>; 289 "emmc_ds";
243 status = "disabled"; 290 function = "emmc";
244 }; 291 };
292 };
245 293
246 i2c_A: i2c@8500 { 294 nor_pins: nor {
247 compatible = "amlogic,meson-gxbb-i2c"; 295 mux {
248 reg = <0x0 0x08500 0x0 0x20>; 296 groups = "nor_d",
249 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 297 "nor_q",
250 clocks = <&clkc CLKID_I2C>; 298 "nor_c",
251 #address-cells = <1>; 299 "nor_cs";
252 #size-cells = <0>; 300 function = "nor";
253 status = "disabled";
254 }; 301 };
302 };
255 303
256 i2c_B: i2c@87c0 { 304 sdcard_pins: sdcard {
257 compatible = "amlogic,meson-gxbb-i2c"; 305 mux {
258 reg = <0x0 0x087c0 0x0 0x20>; 306 groups = "sdcard_d0",
259 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 307 "sdcard_d1",
260 clocks = <&clkc CLKID_I2C>; 308 "sdcard_d2",
261 #address-cells = <1>; 309 "sdcard_d3",
262 #size-cells = <0>; 310 "sdcard_cmd",
263 status = "disabled"; 311 "sdcard_clk";
312 function = "sdcard";
264 }; 313 };
314 };
265 315
266 i2c_C: i2c@87e0 { 316 sdio_pins: sdio {
267 compatible = "amlogic,meson-gxbb-i2c"; 317 mux {
268 reg = <0x0 0x087e0 0x0 0x20>; 318 groups = "sdio_d0",
269 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 319 "sdio_d1",
270 clocks = <&clkc CLKID_I2C>; 320 "sdio_d2",
271 #address-cells = <1>; 321 "sdio_d3",
272 #size-cells = <0>; 322 "sdio_cmd",
273 status = "disabled"; 323 "sdio_clk";
324 function = "sdio";
274 }; 325 };
275 }; 326 };
276 327
277 gic: interrupt-controller@c4301000 { 328 sdio_irq_pins: sdio_irq {
278 compatible = "arm,gic-400"; 329 mux {
279 reg = <0x0 0xc4301000 0 0x1000>, 330 groups = "sdio_irq";
280 <0x0 0xc4302000 0 0x2000>, 331 function = "sdio";
281 <0x0 0xc4304000 0 0x2000>,
282 <0x0 0xc4306000 0 0x2000>;
283 interrupt-controller;
284 interrupts = <GIC_PPI 9
285 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
286 #interrupt-cells = <3>;
287 #address-cells = <0>;
288 };
289
290 aobus: aobus@c8100000 {
291 compatible = "simple-bus";
292 reg = <0x0 0xc8100000 0x0 0x100000>;
293 #address-cells = <2>;
294 #size-cells = <2>;
295 ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
296
297 pinctrl_aobus: pinctrl@14 {
298 compatible = "amlogic,meson-gxbb-aobus-pinctrl";
299 #address-cells = <2>;
300 #size-cells = <2>;
301 ranges;
302
303 gpio_ao: bank@14 {
304 reg = <0x0 0x00014 0x0 0x8>,
305 <0x0 0x0002c 0x0 0x4>,
306 <0x0 0x00024 0x0 0x8>;
307 reg-names = "mux", "pull", "gpio";
308 gpio-controller;
309 #gpio-cells = <2>;
310 };
311
312 uart_ao_a_pins: uart_ao_a {
313 mux {
314 groups = "uart_tx_ao_a", "uart_rx_ao_a";
315 function = "uart_ao";
316 };
317 };
318
319 remote_input_ao_pins: remote_input_ao {
320 mux {
321 groups = "remote_input_ao";
322 function = "remote_input_ao";
323 };
324 };
325
326 i2c_ao_pins: i2c_ao {
327 mux {
328 groups = "i2c_sck_ao",
329 "i2c_sda_ao";
330 function = "i2c_ao";
331 };
332 };
333
334 pwm_ao_a_3_pins: pwm_ao_a_3 {
335 mux {
336 groups = "pwm_ao_a_3";
337 function = "pwm_ao_a_3";
338 };
339 };
340
341 pwm_ao_a_6_pins: pwm_ao_a_6 {
342 mux {
343 groups = "pwm_ao_a_6";
344 function = "pwm_ao_a_6";
345 };
346 };
347
348 pwm_ao_a_12_pins: pwm_ao_a_12 {
349 mux {
350 groups = "pwm_ao_a_12";
351 function = "pwm_ao_a_12";
352 };
353 };
354
355 pwm_ao_b_pins: pwm_ao_b {
356 mux {
357 groups = "pwm_ao_b";
358 function = "pwm_ao_b";
359 };
360 };
361 }; 332 };
333 };
362 334
363 clkc_AO: clock-controller@040 { 335 uart_a_pins: uart_a {
364 compatible = "amlogic,gxbb-aoclkc"; 336 mux {
365 reg = <0x0 0x00040 0x0 0x4>; 337 groups = "uart_tx_a",
366 #clock-cells = <1>; 338 "uart_rx_a";
367 #reset-cells = <1>; 339 function = "uart_a";
368 }; 340 };
341 };
369 342
370 uart_AO: serial@4c0 { 343 uart_b_pins: uart_b {
371 compatible = "amlogic,meson-uart"; 344 mux {
372 reg = <0x0 0x004c0 0x0 0x14>; 345 groups = "uart_tx_b",
373 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 346 "uart_rx_b";
374 clocks = <&xtal>; 347 function = "uart_b";
375 status = "disabled";
376 }; 348 };
349 };
377 350
378 ir: ir@580 { 351 uart_c_pins: uart_c {
379 compatible = "amlogic,meson-gxbb-ir"; 352 mux {
380 reg = <0x0 0x00580 0x0 0x40>; 353 groups = "uart_tx_c",
381 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 354 "uart_rx_c";
382 status = "disabled"; 355 function = "uart_c";
383 }; 356 };
357 };
384 358
385 pwm_ab_AO: pwm@550 { 359 i2c_a_pins: i2c_a {
386 compatible = "amlogic,meson-gxbb-pwm"; 360 mux {
387 reg = <0x0 0x0550 0x0 0x10>; 361 groups = "i2c_sck_a",
388 #pwm-cells = <3>; 362 "i2c_sda_a";
389 status = "disabled"; 363 function = "i2c_a";
390 }; 364 };
365 };
391 366
392 i2c_AO: i2c@500 { 367 i2c_b_pins: i2c_b {
393 compatible = "amlogic,meson-gxbb-i2c"; 368 mux {
394 reg = <0x0 0x500 0x0 0x20>; 369 groups = "i2c_sck_b",
395 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 370 "i2c_sda_b";
396 clocks = <&clkc CLKID_AO_I2C>; 371 function = "i2c_b";
397 #address-cells = <1>;
398 #size-cells = <0>;
399 status = "disabled";
400 }; 372 };
401 }; 373 };
402 374
403 periphs: periphs@c8834000 { 375 i2c_c_pins: i2c_c {
404 compatible = "simple-bus"; 376 mux {
405 reg = <0x0 0xc8834000 0x0 0x2000>; 377 groups = "i2c_sck_c",
406 #address-cells = <2>; 378 "i2c_sda_c";
407 #size-cells = <2>; 379 function = "i2c_c";
408 ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; 380 };
381 };
409 382
410 rng { 383 eth_rgmii_pins: eth-rgmii {
411 compatible = "amlogic,meson-rng"; 384 mux {
412 reg = <0x0 0x0 0x0 0x4>; 385 groups = "eth_mdio",
386 "eth_mdc",
387 "eth_clk_rx_clk",
388 "eth_rx_dv",
389 "eth_rxd0",
390 "eth_rxd1",
391 "eth_rxd2",
392 "eth_rxd3",
393 "eth_rgmii_tx_clk",
394 "eth_tx_en",
395 "eth_txd0",
396 "eth_txd1",
397 "eth_txd2",
398 "eth_txd3";
399 function = "eth";
413 }; 400 };
401 };
414 402
415 pinctrl_periphs: pinctrl@4b0 { 403 eth_rmii_pins: eth-rmii {
416 compatible = "amlogic,meson-gxbb-periphs-pinctrl"; 404 mux {
417 #address-cells = <2>; 405 groups = "eth_mdio",
418 #size-cells = <2>; 406 "eth_mdc",
419 ranges; 407 "eth_clk_rx_clk",
420 408 "eth_rx_dv",
421 gpio: bank@4b0 { 409 "eth_rxd0",
422 reg = <0x0 0x004b0 0x0 0x28>, 410 "eth_rxd1",
423 <0x0 0x004e8 0x0 0x14>, 411 "eth_tx_en",
424 <0x0 0x00120 0x0 0x14>, 412 "eth_txd0",
425 <0x0 0x00430 0x0 0x40>; 413 "eth_txd1";
426 reg-names = "mux", "pull", "pull-enable", "gpio"; 414 function = "eth";
427 gpio-controller;
428 #gpio-cells = <2>;
429 };
430
431 emmc_pins: emmc {
432 mux {
433 groups = "emmc_nand_d07",
434 "emmc_cmd",
435 "emmc_clk";
436 function = "emmc";
437 };
438 };
439
440 nor_pins: nor {
441 mux {
442 groups = "nor_d",
443 "nor_q",
444 "nor_c",
445 "nor_cs";
446 function = "nor";
447 };
448 };
449
450 sdcard_pins: sdcard {
451 mux {
452 groups = "sdcard_d0",
453 "sdcard_d1",
454 "sdcard_d2",
455 "sdcard_d3",
456 "sdcard_cmd",
457 "sdcard_clk";
458 function = "sdcard";
459 };
460 };
461
462 sdio_pins: sdio {
463 mux {
464 groups = "sdio_d0",
465 "sdio_d1",
466 "sdio_d2",
467 "sdio_d3",
468 "sdio_cmd",
469 "sdio_clk";
470 function = "sdio";
471 };
472 };
473
474 sdio_irq_pins: sdio_irq {
475 mux {
476 groups = "sdio_irq";
477 function = "sdio";
478 };
479 };
480
481 uart_a_pins: uart_a {
482 mux {
483 groups = "uart_tx_a",
484 "uart_rx_a";
485 function = "uart_a";
486 };
487 };
488
489 uart_b_pins: uart_b {
490 mux {
491 groups = "uart_tx_b",
492 "uart_rx_b";
493 function = "uart_b";
494 };
495 };
496
497 uart_c_pins: uart_c {
498 mux {
499 groups = "uart_tx_c",
500 "uart_rx_c";
501 function = "uart_c";
502 };
503 };
504
505 i2c_a_pins: i2c_a {
506 mux {
507 groups = "i2c_sck_a",
508 "i2c_sda_a";
509 function = "i2c_a";
510 };
511 };
512
513 i2c_b_pins: i2c_b {
514 mux {
515 groups = "i2c_sck_b",
516 "i2c_sda_b";
517 function = "i2c_b";
518 };
519 };
520
521 i2c_c_pins: i2c_c {
522 mux {
523 groups = "i2c_sck_c",
524 "i2c_sda_c";
525 function = "i2c_c";
526 };
527 };
528
529 eth_pins: eth_c {
530 mux {
531 groups = "eth_mdio",
532 "eth_mdc",
533 "eth_clk_rx_clk",
534 "eth_rx_dv",
535 "eth_rxd0",
536 "eth_rxd1",
537 "eth_rxd2",
538 "eth_rxd3",
539 "eth_rgmii_tx_clk",
540 "eth_tx_en",
541 "eth_txd0",
542 "eth_txd1",
543 "eth_txd2",
544 "eth_txd3";
545 function = "eth";
546 };
547 };
548
549 pwm_a_x_pins: pwm_a_x {
550 mux {
551 groups = "pwm_a_x";
552 function = "pwm_a_x";
553 };
554 };
555
556 pwm_a_y_pins: pwm_a_y {
557 mux {
558 groups = "pwm_a_y";
559 function = "pwm_a_y";
560 };
561 };
562
563 pwm_b_pins: pwm_b {
564 mux {
565 groups = "pwm_b";
566 function = "pwm_b";
567 };
568 };
569
570 pwm_d_pins: pwm_d {
571 mux {
572 groups = "pwm_d";
573 function = "pwm_d";
574 };
575 };
576
577 pwm_e_pins: pwm_e {
578 mux {
579 groups = "pwm_e";
580 function = "pwm_e";
581 };
582 };
583
584 pwm_f_x_pins: pwm_f_x {
585 mux {
586 groups = "pwm_f_x";
587 function = "pwm_f_x";
588 };
589 };
590
591 pwm_f_y_pins: pwm_f_y {
592 mux {
593 groups = "pwm_f_y";
594 function = "pwm_f_y";
595 };
596 };
597 }; 415 };
598 }; 416 };
599 417
600 hiubus: hiubus@c883c000 { 418 pwm_a_x_pins: pwm_a_x {
601 compatible = "simple-bus"; 419 mux {
602 reg = <0x0 0xc883c000 0x0 0x2000>; 420 groups = "pwm_a_x";
603 #address-cells = <2>; 421 function = "pwm_a_x";
604 #size-cells = <2>; 422 };
605 ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; 423 };
606 424
607 clkc: clock-controller@0 { 425 pwm_a_y_pins: pwm_a_y {
608 compatible = "amlogic,gxbb-clkc"; 426 mux {
609 #clock-cells = <1>; 427 groups = "pwm_a_y";
610 reg = <0x0 0x0 0x0 0x3db>; 428 function = "pwm_a_y";
611 }; 429 };
430 };
612 431
613 mailbox: mailbox@404 { 432 pwm_b_pins: pwm_b {
614 compatible = "amlogic,meson-gxbb-mhu"; 433 mux {
615 reg = <0 0x404 0 0x4c>; 434 groups = "pwm_b";
616 interrupts = <0 208 IRQ_TYPE_EDGE_RISING>, 435 function = "pwm_b";
617 <0 209 IRQ_TYPE_EDGE_RISING>,
618 <0 210 IRQ_TYPE_EDGE_RISING>;
619 #mbox-cells = <1>;
620 }; 436 };
621 }; 437 };
622 438
623 apb: apb@d0000000 { 439 pwm_d_pins: pwm_d {
624 compatible = "simple-bus"; 440 mux {
625 reg = <0x0 0xd0000000 0x0 0x200000>; 441 groups = "pwm_d";
626 #address-cells = <2>; 442 function = "pwm_d";
627 #size-cells = <2>; 443 };
628 ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
629 }; 444 };
630 445
631 usb0: usb@c9000000 { 446 pwm_e_pins: pwm_e {
632 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; 447 mux {
633 reg = <0x0 0xc9000000 0x0 0x40000>; 448 groups = "pwm_e";
634 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 449 function = "pwm_e";
635 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; 450 };
636 clock-names = "otg";
637 phys = <&usb0_phy>;
638 phy-names = "usb2-phy";
639 dr_mode = "host";
640 status = "disabled";
641 }; 451 };
642 452
643 usb1: usb@c9100000 { 453 pwm_f_x_pins: pwm_f_x {
644 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; 454 mux {
645 reg = <0x0 0xc9100000 0x0 0x40000>; 455 groups = "pwm_f_x";
646 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 456 function = "pwm_f_x";
647 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 457 };
648 clock-names = "otg";
649 phys = <&usb1_phy>;
650 phy-names = "usb2-phy";
651 dr_mode = "host";
652 status = "disabled";
653 }; 458 };
654 459
655 ethmac: ethernet@c9410000 { 460 pwm_f_y_pins: pwm_f_y {
656 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac"; 461 mux {
657 reg = <0x0 0xc9410000 0x0 0x10000 462 groups = "pwm_f_y";
658 0x0 0xc8834540 0x0 0x4>; 463 function = "pwm_f_y";
659 interrupts = <0 8 1>; 464 };
660 interrupt-names = "macirq";
661 clocks = <&clkc CLKID_ETH>,
662 <&clkc CLKID_FCLK_DIV2>,
663 <&clkc CLKID_MPLL2>;
664 clock-names = "stmmaceth", "clkin0", "clkin1";
665 phy-mode = "rgmii";
666 status = "disabled";
667 }; 465 };
668 }; 466 };
669}; 467};
468
469&hiubus {
470 clkc: clock-controller@0 {
471 compatible = "amlogic,gxbb-clkc";
472 #clock-cells = <1>;
473 reg = <0x0 0x0 0x0 0x3db>;
474 };
475};
476
477&i2c_A {
478 clocks = <&clkc CLKID_I2C>;
479};
480
481&i2c_B {
482 clocks = <&clkc CLKID_I2C>;
483};
484
485&i2c_C {
486 clocks = <&clkc CLKID_I2C>;
487};
488
489&sd_emmc_a {
490 clocks = <&clkc CLKID_SD_EMMC_A>,
491 <&xtal>,
492 <&clkc CLKID_FCLK_DIV2>;
493 clock-names = "core", "clkin0", "clkin1";
494};
495
496&sd_emmc_b {
497 clocks = <&clkc CLKID_SD_EMMC_B>,
498 <&xtal>,
499 <&clkc CLKID_FCLK_DIV2>;
500 clock-names = "core", "clkin0", "clkin1";
501};
502
503&sd_emmc_c {
504 clocks = <&clkc CLKID_SD_EMMC_C>,
505 <&xtal>,
506 <&clkc CLKID_FCLK_DIV2>;
507 clock-names = "core", "clkin0", "clkin1";
508};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-nexbox-a95x.dts
new file mode 100644
index 000000000000..e99101ae9664
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-nexbox-a95x.dts
@@ -0,0 +1,205 @@
1/*
2 * Copyright (c) 2016 Andreas Färber
3 * Copyright (c) 2016 BayLibre, Inc.
4 * Author: Neil Armstrong <narmstrong@kernel.org>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45/dts-v1/;
46
47#include "meson-gxl-s905x.dtsi"
48
49/ {
50 compatible = "nexbox,a95x", "amlogic,s905x", "amlogic,meson-gxl";
51 model = "NEXBOX A95X (S905X)";
52
53 aliases {
54 serial0 = &uart_AO;
55 };
56
57 chosen {
58 stdout-path = "serial0:115200n8";
59 };
60
61 memory@0 {
62 device_type = "memory";
63 reg = <0x0 0x0 0x0 0x80000000>;
64 };
65
66 vddio_card: gpio-regulator {
67 compatible = "regulator-gpio";
68
69 regulator-name = "VDDIO_CARD";
70 regulator-min-microvolt = <1800000>;
71 regulator-max-microvolt = <3300000>;
72
73 gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
74 gpios-states = <1>;
75
76 /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */
77 states = <1800000 0
78 3300000 1>;
79 };
80
81 vddio_boot: regulator-vddio_boot {
82 compatible = "regulator-fixed";
83 regulator-name = "VDDIO_BOOT";
84 regulator-min-microvolt = <1800000>;
85 regulator-max-microvolt = <1800000>;
86 };
87
88 vddao_3v3: regulator-vddao_3v3 {
89 compatible = "regulator-fixed";
90 regulator-name = "VDDAO_3V3";
91 regulator-min-microvolt = <3300000>;
92 regulator-max-microvolt = <3300000>;
93 };
94
95 vcc_3v3: regulator-vcc_3v3 {
96 compatible = "regulator-fixed";
97 regulator-name = "VCC_3V3";
98 regulator-min-microvolt = <3300000>;
99 regulator-max-microvolt = <3300000>;
100 };
101
102 emmc_pwrseq: emmc-pwrseq {
103 compatible = "mmc-pwrseq-emmc";
104 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
105 };
106
107 wifi32k: wifi32k {
108 compatible = "pwm-clock";
109 #clock-cells = <0>;
110 clock-frequency = <32768>;
111 pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
112 };
113
114 sdio_pwrseq: sdio-pwrseq {
115 compatible = "mmc-pwrseq-simple";
116 reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
117 clocks = <&wifi32k>;
118 clock-names = "ext_clock";
119 };
120};
121
122&uart_AO {
123 status = "okay";
124 pinctrl-0 = <&uart_ao_a_pins>;
125 pinctrl-names = "default";
126};
127
128&ethmac {
129 status = "okay";
130 phy-mode = "rmii";
131 phy-handle = <&internal_phy>;
132};
133
134&ir {
135 status = "okay";
136 pinctrl-0 = <&remote_input_ao_pins>;
137 pinctrl-names = "default";
138};
139
140/* Wireless SDIO Module */
141&sd_emmc_a {
142 status = "okay";
143 pinctrl-0 = <&sdio_pins>;
144 pinctrl-names = "default";
145 #address-cells = <1>;
146 #size-cells = <0>;
147
148 bus-width = <4>;
149 cap-sd-highspeed;
150 max-frequency = <100000000>;
151
152 non-removable;
153 disable-wp;
154
155 mmc-pwrseq = <&sdio_pwrseq>;
156
157 vmmc-supply = <&vddao_3v3>;
158 vqmmc-supply = <&vddio_boot>;
159};
160
161/* SD card */
162&sd_emmc_b {
163 status = "okay";
164 pinctrl-0 = <&sdcard_pins>;
165 pinctrl-names = "default";
166
167 bus-width = <4>;
168 cap-sd-highspeed;
169 max-frequency = <100000000>;
170 disable-wp;
171
172 cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
173 cd-inverted;
174
175 vmmc-supply = <&vddao_3v3>;
176 vqmmc-supply = <&vddio_card>;
177};
178
179/* eMMC */
180&sd_emmc_c {
181 status = "okay";
182 pinctrl-0 = <&emmc_pins>;
183 pinctrl-names = "default";
184
185 bus-width = <8>;
186 cap-sd-highspeed;
187 cap-mmc-highspeed;
188 max-frequency = <200000000>;
189 non-removable;
190 disable-wp;
191 mmc-ddr-1_8v;
192 mmc-hs200-1_8v;
193
194 mmc-pwrseq = <&emmc_pwrseq>;
195 vmmc-supply = <&vcc_3v3>;
196 vqmmc-supply = <&vddio_boot>;
197};
198
199&pwm_ef {
200 status = "okay";
201 pinctrl-0 = <&pwm_e_pins>;
202 pinctrl-names = "default";
203 clocks = <&clkc CLKID_FCLK_DIV4>;
204 clock-names = "clkin0";
205};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
new file mode 100644
index 000000000000..f66939cacd37
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
@@ -0,0 +1,77 @@
1/*
2 * Copyright (c) 2016 Endless Computers, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44/dts-v1/;
45
46#include "meson-gxl-s905d.dtsi"
47#include "meson-gx-p23x-q20x.dtsi"
48
49/ {
50 compatible = "amlogic,p230", "amlogic,s905d", "amlogic,meson-gxl";
51 model = "Amlogic Meson GXL (S905D) P230 Development Board";
52};
53
54/* P230 has exclusive choice between internal or external PHY */
55&ethmac {
56 pinctrl-0 = <&eth_pins>;
57 pinctrl-names = "default";
58
59 /* Select external PHY by default */
60 phy-handle = <&external_phy>;
61
62 /* External PHY reset is shared with internal PHY Led signals */
63 snps,reset-gpio = <&gpio GPIOZ_14 0>;
64 snps,reset-delays-us = <0 10000 1000000>;
65 snps,reset-active-low;
66
67 /* External PHY is in RGMII */
68 phy-mode = "rgmii";
69};
70
71&external_mdio {
72 external_phy: ethernet-phy@0 {
73 compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
74 reg = <0>;
75 max-speed = <1000>;
76 };
77};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
new file mode 100644
index 000000000000..95992cf1fe61
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
@@ -0,0 +1,58 @@
1/*
2 * Copyright (c) 2016 Endless Computers, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44/dts-v1/;
45
46#include "meson-gxl-s905d.dtsi"
47#include "meson-gx-p23x-q20x.dtsi"
48
49/ {
50 compatible = "amlogic,p231", "amlogic,s905d", "amlogic,meson-gxl";
51 model = "Amlogic Meson GXL (S905D) P231 Development Board";
52};
53
54/* P231 has only internal PHY port */
55&ethmac {
56 phy-mode = "rmii";
57 phy-handle = <&internal_phy>;
58};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
new file mode 100644
index 000000000000..615308e55576
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
@@ -0,0 +1,48 @@
1/*
2 * Copyright (c) 2016 Endless Computers, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include "meson-gxl.dtsi"
45
46/ {
47 compatible = "amlogic,s905d", "amlogic,meson-gxl";
48};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
new file mode 100644
index 000000000000..9639f012b02b
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
@@ -0,0 +1,69 @@
1/*
2 * Copyright (c) 2016 Endless Computers, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44/dts-v1/;
45
46#include "meson-gxl-s905x.dtsi"
47
48/ {
49 compatible = "amlogic,p212", "amlogic,s905x", "amlogic,meson-gxl";
50 model = "Amlogic Meson GXL (S905X) P212 Development Board";
51
52 aliases {
53 serial0 = &uart_AO;
54 };
55
56 chosen {
57 stdout-path = "serial0:115200n8";
58 };
59
60 memory@0 {
61 device_type = "memory";
62 reg = <0x0 0x0 0x0 0x80000000>;
63 };
64};
65
66/* This UART is brought out to the DB9 connector */
67&uart_AO {
68 status = "okay";
69};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
new file mode 100644
index 000000000000..08237ee1e362
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
@@ -0,0 +1,54 @@
1/*
2 * Copyright (c) 2016 Endless Computers, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include "meson-gxl.dtsi"
45
46/ {
47 compatible = "amlogic,s905x", "amlogic,meson-gxl";
48};
49
50/* S905X Only has access to its internal PHY */
51&ethmac {
52 phy-mode = "rmii";
53 phy-handle = <&internal_phy>;
54};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
new file mode 100644
index 000000000000..9f89b99c4806
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -0,0 +1,301 @@
1/*
2 * Copyright (c) 2016 Endless Computers, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include "meson-gx.dtsi"
45#include <dt-bindings/clock/gxbb-clkc.h>
46#include <dt-bindings/gpio/meson-gxbb-gpio.h>
47
48/ {
49 compatible = "amlogic,meson-gxl";
50};
51
52&ethmac {
53 reg = <0x0 0xc9410000 0x0 0x10000
54 0x0 0xc8834540 0x0 0x4>;
55
56 clocks = <&clkc CLKID_ETH>,
57 <&clkc CLKID_FCLK_DIV2>,
58 <&clkc CLKID_MPLL2>;
59 clock-names = "stmmaceth", "clkin0", "clkin1";
60
61 mdio0: mdio {
62 #address-cells = <1>;
63 #size-cells = <0>;
64 compatible = "snps,dwmac-mdio";
65 };
66};
67
68&aobus {
69 pinctrl_aobus: pinctrl@14 {
70 compatible = "amlogic,meson-gxl-aobus-pinctrl";
71 #address-cells = <2>;
72 #size-cells = <2>;
73 ranges;
74
75 gpio_ao: bank@14 {
76 reg = <0x0 0x00014 0x0 0x8>,
77 <0x0 0x0002c 0x0 0x4>,
78 <0x0 0x00024 0x0 0x8>;
79 reg-names = "mux", "pull", "gpio";
80 gpio-controller;
81 #gpio-cells = <2>;
82 };
83
84 uart_ao_a_pins: uart_ao_a {
85 mux {
86 groups = "uart_tx_ao_a", "uart_rx_ao_a";
87 function = "uart_ao";
88 };
89 };
90
91 remote_input_ao_pins: remote_input_ao {
92 mux {
93 groups = "remote_input_ao";
94 function = "remote_input_ao";
95 };
96 };
97 };
98};
99
100&periphs {
101 pinctrl_periphs: pinctrl@4b0 {
102 compatible = "amlogic,meson-gxl-periphs-pinctrl";
103 #address-cells = <2>;
104 #size-cells = <2>;
105 ranges;
106
107 gpio: bank@4b0 {
108 reg = <0x0 0x004b0 0x0 0x28>,
109 <0x0 0x004e8 0x0 0x14>,
110 <0x0 0x00120 0x0 0x14>,
111 <0x0 0x00430 0x0 0x40>;
112 reg-names = "mux", "pull", "pull-enable", "gpio";
113 gpio-controller;
114 #gpio-cells = <2>;
115 };
116
117 emmc_pins: emmc {
118 mux {
119 groups = "emmc_nand_d07",
120 "emmc_cmd",
121 "emmc_clk",
122 "emmc_ds";
123 function = "emmc";
124 };
125 };
126
127 sdcard_pins: sdcard {
128 mux {
129 groups = "sdcard_d0",
130 "sdcard_d1",
131 "sdcard_d2",
132 "sdcard_d3",
133 "sdcard_cmd",
134 "sdcard_clk";
135 function = "sdcard";
136 };
137 };
138
139 sdio_pins: sdio {
140 mux {
141 groups = "sdio_d0",
142 "sdio_d1",
143 "sdio_d2",
144 "sdio_d3",
145 "sdio_cmd",
146 "sdio_clk";
147 function = "sdio";
148 };
149 };
150
151 sdio_irq_pins: sdio_irq {
152 mux {
153 groups = "sdio_irq";
154 function = "sdio";
155 };
156 };
157
158 uart_a_pins: uart_a {
159 mux {
160 groups = "uart_tx_a",
161 "uart_rx_a";
162 function = "uart_a";
163 };
164 };
165
166 uart_b_pins: uart_b {
167 mux {
168 groups = "uart_tx_b",
169 "uart_rx_b";
170 function = "uart_b";
171 };
172 };
173
174 uart_c_pins: uart_c {
175 mux {
176 groups = "uart_tx_c",
177 "uart_rx_c";
178 function = "uart_c";
179 };
180 };
181
182 i2c_a_pins: i2c_a {
183 mux {
184 groups = "i2c_sck_a",
185 "i2c_sda_a";
186 function = "i2c_a";
187 };
188 };
189
190 i2c_b_pins: i2c_b {
191 mux {
192 groups = "i2c_sck_b",
193 "i2c_sda_b";
194 function = "i2c_b";
195 };
196 };
197
198 i2c_c_pins: i2c_c {
199 mux {
200 groups = "i2c_sck_c",
201 "i2c_sda_c";
202 function = "i2c_c";
203 };
204 };
205
206 eth_pins: eth_c {
207 mux {
208 groups = "eth_mdio",
209 "eth_mdc",
210 "eth_clk_rx_clk",
211 "eth_rx_dv",
212 "eth_rxd0",
213 "eth_rxd1",
214 "eth_rxd2",
215 "eth_rxd3",
216 "eth_rgmii_tx_clk",
217 "eth_tx_en",
218 "eth_txd0",
219 "eth_txd1",
220 "eth_txd2",
221 "eth_txd3";
222 function = "eth";
223 };
224 };
225
226 pwm_e_pins: pwm_e {
227 mux {
228 groups = "pwm_e";
229 function = "pwm_e";
230 };
231 };
232 };
233
234 eth-phy-mux {
235 compatible = "mdio-mux-mmioreg", "mdio-mux";
236 #address-cells = <1>;
237 #size-cells = <0>;
238 reg = <0x0 0x55c 0x0 0x4>;
239 mux-mask = <0xffffffff>;
240 mdio-parent-bus = <&mdio0>;
241
242 internal_mdio: mdio@e40908ff {
243 reg = <0xe40908ff>;
244 #address-cells = <1>;
245 #size-cells = <0>;
246
247 internal_phy: ethernet-phy@8 {
248 compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
249 reg = <8>;
250 max-speed = <100>;
251 };
252 };
253
254 external_mdio: mdio@2009087f {
255 reg = <0x2009087f>;
256 #address-cells = <1>;
257 #size-cells = <0>;
258 };
259 };
260};
261
262&hiubus {
263 clkc: clock-controller@0 {
264 compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
265 #clock-cells = <1>;
266 reg = <0x0 0x0 0x0 0x3db>;
267 };
268};
269
270&i2c_A {
271 clocks = <&clkc CLKID_I2C>;
272};
273
274&i2c_B {
275 clocks = <&clkc CLKID_I2C>;
276};
277
278&i2c_C {
279 clocks = <&clkc CLKID_I2C>;
280};
281
282&sd_emmc_a {
283 clocks = <&clkc CLKID_SD_EMMC_A>,
284 <&xtal>,
285 <&clkc CLKID_FCLK_DIV2>;
286 clock-names = "core", "clkin0", "clkin1";
287};
288
289&sd_emmc_b {
290 clocks = <&clkc CLKID_SD_EMMC_B>,
291 <&xtal>,
292 <&clkc CLKID_FCLK_DIV2>;
293 clock-names = "core", "clkin0", "clkin1";
294};
295
296&sd_emmc_c {
297 clocks = <&clkc CLKID_SD_EMMC_C>,
298 <&xtal>,
299 <&clkc CLKID_FCLK_DIV2>;
300 clock-names = "core", "clkin0", "clkin1";
301};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
new file mode 100644
index 000000000000..f859d75db8bd
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
@@ -0,0 +1,169 @@
1/*
2 * Copyright (c) 2016 BayLibre, SAS.
3 * Author: Neil Armstrong <narmstrong@baylibre.com>
4 *
5 * Copyright (c) 2016 Endless Computers, Inc.
6 * Author: Carlo Caione <carlo@endlessm.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47/dts-v1/;
48
49#include "meson-gxm.dtsi"
50
51/ {
52 compatible = "nexbox,a1", "amlogic,s912", "amlogic,meson-gxm";
53 model = "NEXBOX A1";
54
55 aliases {
56 serial0 = &uart_AO;
57 };
58
59 chosen {
60 stdout-path = "serial0:115200n8";
61 };
62
63 memory@0 {
64 device_type = "memory";
65 reg = <0x0 0x0 0x0 0x80000000>;
66 };
67
68 vddio_boot: regulator-vddio-boot {
69 compatible = "regulator-fixed";
70 regulator-name = "VDDIO_BOOT";
71 regulator-min-microvolt = <1800000>;
72 regulator-max-microvolt = <1800000>;
73 };
74
75 vddao_3v3: regulator-vddao-3v3 {
76 compatible = "regulator-fixed";
77 regulator-name = "VDDAO_3V3";
78 regulator-min-microvolt = <3300000>;
79 regulator-max-microvolt = <3300000>;
80 };
81
82 vcc_3v3: regulator-vcc-3v3 {
83 compatible = "regulator-fixed";
84 regulator-name = "VCC_3V3";
85 regulator-min-microvolt = <3300000>;
86 regulator-max-microvolt = <3300000>;
87 };
88
89 emmc_pwrseq: emmc-pwrseq {
90 compatible = "mmc-pwrseq-emmc";
91 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
92 };
93};
94
95/* This UART is brought out to the DB9 connector */
96&uart_AO {
97 status = "okay";
98 pinctrl-0 = <&uart_ao_a_pins>;
99 pinctrl-names = "default";
100};
101
102&ir {
103 status = "okay";
104 pinctrl-0 = <&remote_input_ao_pins>;
105 pinctrl-names = "default";
106};
107
108/* SD card */
109&sd_emmc_b {
110 status = "okay";
111 pinctrl-0 = <&sdcard_pins>;
112 pinctrl-names = "default";
113
114 bus-width = <4>;
115 cap-sd-highspeed;
116 max-frequency = <100000000>;
117 disable-wp;
118
119 cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
120 cd-inverted;
121
122 vmmc-supply = <&vddao_3v3>;
123 vqmmc-supply = <&vddio_boot>;
124};
125
126/* eMMC */
127&sd_emmc_c {
128 status = "okay";
129 pinctrl-0 = <&emmc_pins>;
130 pinctrl-names = "default";
131
132 bus-width = <8>;
133 cap-sd-highspeed;
134 cap-mmc-highspeed;
135 max-frequency = <200000000>;
136 non-removable;
137 disable-wp;
138 mmc-ddr-1_8v;
139 mmc-hs200-1_8v;
140
141 mmc-pwrseq = <&emmc_pwrseq>;
142 vmmc-supply = <&vcc_3v3>;
143 vqmmc-supply = <&vddio_boot>;
144};
145
146&ethmac {
147 status = "okay";
148
149 pinctrl-0 = <&eth_pins>;
150 pinctrl-names = "default";
151
152 /* Select external PHY by default */
153 phy-handle = <&external_phy>;
154
155 snps,reset-gpio = <&gpio GPIOZ_14 0>;
156 snps,reset-delays-us = <0 10000 1000000>;
157 snps,reset-active-low;
158
159 /* External PHY is in RGMII */
160 phy-mode = "rgmii";
161};
162
163&external_mdio {
164 external_phy: ethernet-phy@0 {
165 compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
166 reg = <0>;
167 max-speed = <1000>;
168 };
169};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts
new file mode 100644
index 000000000000..5dbc66088355
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts
@@ -0,0 +1,77 @@
1/*
2 * Copyright (c) 2016 Endless Computers, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44/dts-v1/;
45
46#include "meson-gxm.dtsi"
47#include "meson-gx-p23x-q20x.dtsi"
48
49/ {
50 compatible = "amlogic,q200", "amlogic,s912", "amlogic,meson-gxm";
51 model = "Amlogic Meson GXM (S912) Q200 Development Board";
52};
53
54/* Q200 has exclusive choice between internal or external PHY */
55&ethmac {
56 pinctrl-0 = <&eth_pins>;
57 pinctrl-names = "default";
58
59 /* Select external PHY by default */
60 phy-handle = <&external_phy>;
61
62 /* External PHY reset is shared with internal PHY Led signals */
63 snps,reset-gpio = <&gpio GPIOZ_14 0>;
64 snps,reset-delays-us = <0 10000 1000000>;
65 snps,reset-active-low;
66
67 /* External PHY is in RGMII */
68 phy-mode = "rgmii";
69};
70
71&external_mdio {
72 external_phy: ethernet-phy@0 {
73 compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
74 reg = <0>;
75 max-speed = <1000>;
76 };
77};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-s912-q201.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-s912-q201.dts
new file mode 100644
index 000000000000..95e11d7faab8
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-s912-q201.dts
@@ -0,0 +1,58 @@
1/*
2 * Copyright (c) 2016 Endless Computers, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44/dts-v1/;
45
46#include "meson-gxm.dtsi"
47#include "meson-gx-p23x-q20x.dtsi"
48
49/ {
50 compatible = "amlogic,q201", "amlogic,s912", "amlogic,meson-gxm";
51 model = "Amlogic Meson GXM (S912) Q201 Development Board";
52};
53
54/* Q201 has only internal PHY port */
55&ethmac {
56 phy-mode = "rmii";
57 phy-handle = <&internal_phy>;
58};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
new file mode 100644
index 000000000000..c1974bbbddea
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
@@ -0,0 +1,114 @@
1/*
2 * Copyright (c) 2016 Endless Computers, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include "meson-gxl.dtsi"
45
46/ {
47 compatible = "amlogic,meson-gxm";
48
49 cpus {
50 cpu-map {
51 cluster0 {
52 core0 {
53 cpu = <&cpu0>;
54 };
55 core1 {
56 cpu = <&cpu1>;
57 };
58 core2 {
59 cpu = <&cpu2>;
60 };
61 core3 {
62 cpu = <&cpu3>;
63 };
64 };
65
66 cluster1 {
67 core0 {
68 cpu = <&cpu4>;
69 };
70 core1 {
71 cpu = <&cpu5>;
72 };
73 core2 {
74 cpu = <&cpu6>;
75 };
76 core3 {
77 cpu = <&cpu7>;
78 };
79 };
80 };
81
82 cpu4: cpu@100 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a53", "arm,armv8";
85 reg = <0x0 0x100>;
86 enable-method = "psci";
87 next-level-cache = <&l2>;
88 };
89
90 cpu5: cpu@101 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a53", "arm,armv8";
93 reg = <0x0 0x101>;
94 enable-method = "psci";
95 next-level-cache = <&l2>;
96 };
97
98 cpu6: cpu@102 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a53", "arm,armv8";
101 reg = <0x0 0x102>;
102 enable-method = "psci";
103 next-level-cache = <&l2>;
104 };
105
106 cpu7: cpu@103 {
107 device_type = "cpu";
108 compatible = "arm,cortex-a53", "arm,armv8";
109 reg = <0x0 0x103>;
110 enable-method = "psci";
111 next-level-cache = <&l2>;
112 };
113 };
114};
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 7d3a2acc6a55..7d832247d0db 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -29,6 +29,28 @@
29 clock-names = "apb_pclk"; 29 clock-names = "apb_pclk";
30 }; 30 };
31 31
32 smmu_pcie: iommu@2b500000 {
33 compatible = "arm,mmu-401", "arm,smmu-v1";
34 reg = <0x0 0x2b500000 0x0 0x10000>;
35 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
36 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
37 #iommu-cells = <1>;
38 #global-interrupts = <1>;
39 dma-coherent;
40 status = "disabled";
41 };
42
43 smmu_etr: iommu@2b600000 {
44 compatible = "arm,mmu-401", "arm,smmu-v1";
45 reg = <0x0 0x2b600000 0x0 0x10000>;
46 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
48 #iommu-cells = <1>;
49 #global-interrupts = <1>;
50 dma-coherent;
51 status = "disabled";
52 };
53
32 gic: interrupt-controller@2c010000 { 54 gic: interrupt-controller@2c010000 {
33 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 55 compatible = "arm,gic-400", "arm,cortex-a15-gic";
34 reg = <0x0 0x2c010000 0 0x1000>, 56 reg = <0x0 0x2c010000 0 0x1000>,
@@ -146,6 +168,7 @@
146 etr@20070000 { 168 etr@20070000 {
147 compatible = "arm,coresight-tmc", "arm,primecell"; 169 compatible = "arm,coresight-tmc", "arm,primecell";
148 reg = <0 0x20070000 0 0x1000>; 170 reg = <0 0x20070000 0 0x1000>;
171 iommus = <&smmu_etr 0>;
149 172
150 clocks = <&soc_smc50mhz>; 173 clocks = <&soc_smc50mhz>;
151 clock-names = "apb_pclk"; 174 clock-names = "apb_pclk";
@@ -404,6 +427,8 @@
404 <0 0 0 4 &gic 0 0 0 139 4>; 427 <0 0 0 4 &gic 0 0 0 139 4>;
405 msi-parent = <&v2m_0>; 428 msi-parent = <&v2m_0>;
406 status = "disabled"; 429 status = "disabled";
430 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
431 iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
407 }; 432 };
408 433
409 scpi { 434 scpi {
@@ -484,6 +509,48 @@
484 509
485 /include/ "juno-clocks.dtsi" 510 /include/ "juno-clocks.dtsi"
486 511
512 smmu_dma: iommu@7fb00000 {
513 compatible = "arm,mmu-401", "arm,smmu-v1";
514 reg = <0x0 0x7fb00000 0x0 0x10000>;
515 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
517 #iommu-cells = <1>;
518 #global-interrupts = <1>;
519 dma-coherent;
520 status = "disabled";
521 };
522
523 smmu_hdlcd1: iommu@7fb10000 {
524 compatible = "arm,mmu-401", "arm,smmu-v1";
525 reg = <0x0 0x7fb10000 0x0 0x10000>;
526 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
528 #iommu-cells = <1>;
529 #global-interrupts = <1>;
530 status = "disabled";
531 };
532
533 smmu_hdlcd0: iommu@7fb20000 {
534 compatible = "arm,mmu-401", "arm,smmu-v1";
535 reg = <0x0 0x7fb20000 0x0 0x10000>;
536 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
538 #iommu-cells = <1>;
539 #global-interrupts = <1>;
540 status = "disabled";
541 };
542
543 smmu_usb: iommu@7fb30000 {
544 compatible = "arm,mmu-401", "arm,smmu-v1";
545 reg = <0x0 0x7fb30000 0x0 0x10000>;
546 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
547 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
548 #iommu-cells = <1>;
549 #global-interrupts = <1>;
550 dma-coherent;
551 status = "disabled";
552 };
553
487 dma@7ff00000 { 554 dma@7ff00000 {
488 compatible = "arm,pl330", "arm,primecell"; 555 compatible = "arm,pl330", "arm,primecell";
489 reg = <0x0 0x7ff00000 0 0x1000>; 556 reg = <0x0 0x7ff00000 0 0x1000>;
@@ -499,6 +566,15 @@
499 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 568 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
569 iommus = <&smmu_dma 0>,
570 <&smmu_dma 1>,
571 <&smmu_dma 2>,
572 <&smmu_dma 3>,
573 <&smmu_dma 4>,
574 <&smmu_dma 5>,
575 <&smmu_dma 6>,
576 <&smmu_dma 7>,
577 <&smmu_dma 8>;
502 clocks = <&soc_faxiclk>; 578 clocks = <&soc_faxiclk>;
503 clock-names = "apb_pclk"; 579 clock-names = "apb_pclk";
504 }; 580 };
@@ -507,6 +583,7 @@
507 compatible = "arm,hdlcd"; 583 compatible = "arm,hdlcd";
508 reg = <0 0x7ff50000 0 0x1000>; 584 reg = <0 0x7ff50000 0 0x1000>;
509 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 585 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
586 iommus = <&smmu_hdlcd1 0>;
510 clocks = <&scpi_clk 3>; 587 clocks = <&scpi_clk 3>;
511 clock-names = "pxlclk"; 588 clock-names = "pxlclk";
512 589
@@ -521,6 +598,7 @@
521 compatible = "arm,hdlcd"; 598 compatible = "arm,hdlcd";
522 reg = <0 0x7ff60000 0 0x1000>; 599 reg = <0 0x7ff60000 0 0x1000>;
523 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 600 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
601 iommus = <&smmu_hdlcd0 0>;
524 clocks = <&scpi_clk 3>; 602 clocks = <&scpi_clk 3>;
525 clock-names = "pxlclk"; 603 clock-names = "pxlclk";
526 604
@@ -574,6 +652,7 @@
574 compatible = "generic-ohci"; 652 compatible = "generic-ohci";
575 reg = <0x0 0x7ffb0000 0x0 0x10000>; 653 reg = <0x0 0x7ffb0000 0x0 0x10000>;
576 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 654 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
655 iommus = <&smmu_usb 0>;
577 clocks = <&soc_usb48mhz>; 656 clocks = <&soc_usb48mhz>;
578 }; 657 };
579 658
@@ -581,6 +660,7 @@
581 compatible = "generic-ehci"; 660 compatible = "generic-ehci";
582 reg = <0x0 0x7ffc0000 0x0 0x10000>; 661 reg = <0x0 0x7ffc0000 0x0 0x10000>;
583 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 662 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
663 iommus = <&smmu_usb 0>;
584 clocks = <&soc_usb48mhz>; 664 clocks = <&soc_usb48mhz>;
585 }; 665 };
586 666
diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
index f0b857d6d73c..eec37feee8fc 100644
--- a/arch/arm64/boot/dts/arm/juno-r1.dts
+++ b/arch/arm64/boot/dts/arm/juno-r1.dts
@@ -90,6 +90,7 @@
90 next-level-cache = <&A57_L2>; 90 next-level-cache = <&A57_L2>;
91 clocks = <&scpi_dvfs 0>; 91 clocks = <&scpi_dvfs 0>;
92 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 92 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
93 capacity-dmips-mhz = <1024>;
93 }; 94 };
94 95
95 A57_1: cpu@1 { 96 A57_1: cpu@1 {
@@ -100,6 +101,7 @@
100 next-level-cache = <&A57_L2>; 101 next-level-cache = <&A57_L2>;
101 clocks = <&scpi_dvfs 0>; 102 clocks = <&scpi_dvfs 0>;
102 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 103 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
104 capacity-dmips-mhz = <1024>;
103 }; 105 };
104 106
105 A53_0: cpu@100 { 107 A53_0: cpu@100 {
@@ -110,6 +112,7 @@
110 next-level-cache = <&A53_L2>; 112 next-level-cache = <&A53_L2>;
111 clocks = <&scpi_dvfs 1>; 113 clocks = <&scpi_dvfs 1>;
112 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 114 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
115 capacity-dmips-mhz = <578>;
113 }; 116 };
114 117
115 A53_1: cpu@101 { 118 A53_1: cpu@101 {
@@ -120,6 +123,7 @@
120 next-level-cache = <&A53_L2>; 123 next-level-cache = <&A53_L2>;
121 clocks = <&scpi_dvfs 1>; 124 clocks = <&scpi_dvfs 1>;
122 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 125 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
126 capacity-dmips-mhz = <578>;
123 }; 127 };
124 128
125 A53_2: cpu@102 { 129 A53_2: cpu@102 {
@@ -130,6 +134,7 @@
130 next-level-cache = <&A53_L2>; 134 next-level-cache = <&A53_L2>;
131 clocks = <&scpi_dvfs 1>; 135 clocks = <&scpi_dvfs 1>;
132 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 136 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
137 capacity-dmips-mhz = <578>;
133 }; 138 };
134 139
135 A53_3: cpu@103 { 140 A53_3: cpu@103 {
@@ -140,6 +145,7 @@
140 next-level-cache = <&A53_L2>; 145 next-level-cache = <&A53_L2>;
141 clocks = <&scpi_dvfs 1>; 146 clocks = <&scpi_dvfs 1>;
142 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 147 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
148 capacity-dmips-mhz = <578>;
143 }; 149 };
144 150
145 A57_L2: l2-cache0 { 151 A57_L2: l2-cache0 {
diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
index 26aaa6a7670f..28f40ec44090 100644
--- a/arch/arm64/boot/dts/arm/juno-r2.dts
+++ b/arch/arm64/boot/dts/arm/juno-r2.dts
@@ -90,6 +90,7 @@
90 next-level-cache = <&A72_L2>; 90 next-level-cache = <&A72_L2>;
91 clocks = <&scpi_dvfs 0>; 91 clocks = <&scpi_dvfs 0>;
92 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 92 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
93 capacity-dmips-mhz = <1024>;
93 }; 94 };
94 95
95 A72_1: cpu@1 { 96 A72_1: cpu@1 {
@@ -100,6 +101,7 @@
100 next-level-cache = <&A72_L2>; 101 next-level-cache = <&A72_L2>;
101 clocks = <&scpi_dvfs 0>; 102 clocks = <&scpi_dvfs 0>;
102 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 103 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
104 capacity-dmips-mhz = <1024>;
103 }; 105 };
104 106
105 A53_0: cpu@100 { 107 A53_0: cpu@100 {
@@ -110,6 +112,7 @@
110 next-level-cache = <&A53_L2>; 112 next-level-cache = <&A53_L2>;
111 clocks = <&scpi_dvfs 1>; 113 clocks = <&scpi_dvfs 1>;
112 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 114 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
115 capacity-dmips-mhz = <485>;
113 }; 116 };
114 117
115 A53_1: cpu@101 { 118 A53_1: cpu@101 {
@@ -120,6 +123,7 @@
120 next-level-cache = <&A53_L2>; 123 next-level-cache = <&A53_L2>;
121 clocks = <&scpi_dvfs 1>; 124 clocks = <&scpi_dvfs 1>;
122 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 125 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
126 capacity-dmips-mhz = <485>;
123 }; 127 };
124 128
125 A53_2: cpu@102 { 129 A53_2: cpu@102 {
@@ -130,6 +134,7 @@
130 next-level-cache = <&A53_L2>; 134 next-level-cache = <&A53_L2>;
131 clocks = <&scpi_dvfs 1>; 135 clocks = <&scpi_dvfs 1>;
132 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 136 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
137 capacity-dmips-mhz = <485>;
133 }; 138 };
134 139
135 A53_3: cpu@103 { 140 A53_3: cpu@103 {
@@ -140,6 +145,7 @@
140 next-level-cache = <&A53_L2>; 145 next-level-cache = <&A53_L2>;
141 clocks = <&scpi_dvfs 1>; 146 clocks = <&scpi_dvfs 1>;
142 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 147 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
148 capacity-dmips-mhz = <485>;
143 }; 149 };
144 150
145 A72_L2: l2-cache0 { 151 A72_L2: l2-cache0 {
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index 6e154d948a80..ac5ceb73f45f 100644
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -90,6 +90,7 @@
90 next-level-cache = <&A57_L2>; 90 next-level-cache = <&A57_L2>;
91 clocks = <&scpi_dvfs 0>; 91 clocks = <&scpi_dvfs 0>;
92 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 92 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
93 capacity-dmips-mhz = <1024>;
93 }; 94 };
94 95
95 A57_1: cpu@1 { 96 A57_1: cpu@1 {
@@ -100,6 +101,7 @@
100 next-level-cache = <&A57_L2>; 101 next-level-cache = <&A57_L2>;
101 clocks = <&scpi_dvfs 0>; 102 clocks = <&scpi_dvfs 0>;
102 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 103 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
104 capacity-dmips-mhz = <1024>;
103 }; 105 };
104 106
105 A53_0: cpu@100 { 107 A53_0: cpu@100 {
@@ -110,6 +112,7 @@
110 next-level-cache = <&A53_L2>; 112 next-level-cache = <&A53_L2>;
111 clocks = <&scpi_dvfs 1>; 113 clocks = <&scpi_dvfs 1>;
112 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 114 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
115 capacity-dmips-mhz = <578>;
113 }; 116 };
114 117
115 A53_1: cpu@101 { 118 A53_1: cpu@101 {
@@ -120,6 +123,7 @@
120 next-level-cache = <&A53_L2>; 123 next-level-cache = <&A53_L2>;
121 clocks = <&scpi_dvfs 1>; 124 clocks = <&scpi_dvfs 1>;
122 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 125 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
126 capacity-dmips-mhz = <578>;
123 }; 127 };
124 128
125 A53_2: cpu@102 { 129 A53_2: cpu@102 {
@@ -130,6 +134,7 @@
130 next-level-cache = <&A53_L2>; 134 next-level-cache = <&A53_L2>;
131 clocks = <&scpi_dvfs 1>; 135 clocks = <&scpi_dvfs 1>;
132 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 136 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
137 capacity-dmips-mhz = <578>;
133 }; 138 };
134 139
135 A53_3: cpu@103 { 140 A53_3: cpu@103 {
@@ -140,6 +145,7 @@
140 next-level-cache = <&A53_L2>; 145 next-level-cache = <&A53_L2>;
141 clocks = <&scpi_dvfs 1>; 146 clocks = <&scpi_dvfs 1>;
142 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 147 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
148 capacity-dmips-mhz = <578>;
143 }; 149 };
144 150
145 A57_L2: l2-cache0 { 151 A57_L2: l2-cache0 {
diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
index 7841b724e340..c309633a1e87 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
+++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
@@ -2,6 +2,7 @@
2#include "bcm2837.dtsi" 2#include "bcm2837.dtsi"
3#include "bcm2835-rpi.dtsi" 3#include "bcm2835-rpi.dtsi"
4#include "bcm283x-rpi-smsc9514.dtsi" 4#include "bcm283x-rpi-smsc9514.dtsi"
5#include "bcm283x-rpi-usb-host.dtsi"
5 6
6/ { 7/ {
7 compatible = "raspberrypi,3-model-b", "brcm,bcm2837"; 8 compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
@@ -15,13 +16,6 @@
15 act { 16 act {
16 gpios = <&gpio 47 0>; 17 gpios = <&gpio 47 0>;
17 }; 18 };
18
19 pwr {
20 label = "PWR";
21 gpios = <&gpio 35 0>;
22 default-state = "keep";
23 linux,default-trigger = "default-on";
24 };
25 }; 19 };
26}; 20};
27 21
diff --git a/arch/arm64/boot/dts/broadcom/bcm2837.dtsi b/arch/arm64/boot/dts/broadcom/bcm2837.dtsi
index 8216bbb29fe0..19f2fe620a21 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2837.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcm2837.dtsi
@@ -1,7 +1,7 @@
1#include "bcm283x.dtsi" 1#include "bcm283x.dtsi"
2 2
3/ { 3/ {
4 compatible = "brcm,bcm2836"; 4 compatible = "brcm,bcm2837";
5 5
6 soc { 6 soc {
7 ranges = <0x7e000000 0x3f000000 0x1000000>, 7 ranges = <0x7e000000 0x3f000000 0x1000000>,
@@ -74,3 +74,9 @@
74 interrupt-parent = <&local_intc>; 74 interrupt-parent = <&local_intc>;
75 interrupts = <8>; 75 interrupts = <8>;
76}; 76};
77
78/* enable thermal sensor with the correct compatible property set */
79&thermal {
80 compatible = "brcm,bcm2837-thermal";
81 status = "okay";
82};
diff --git a/arch/arm64/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi b/arch/arm64/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi
new file mode 120000
index 000000000000..cbeebe312ff8
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi
@@ -0,0 +1 @@
../../../../arm/boot/dts/bcm283x-rpi-usb-host.dtsi \ No newline at end of file
diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
index c4d544244b19..de8d379f44e2 100644
--- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts
+++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
@@ -161,6 +161,10 @@
161 status = "ok"; 161 status = "ok";
162}; 162};
163 163
164&sdio1 {
165 status = "ok";
166};
167
164&nand { 168&nand {
165 nandcs@0 { 169 nandcs@0 {
166 compatible = "brcm,nandcs"; 170 compatible = "brcm,nandcs";
@@ -192,3 +196,37 @@
192 groups = "nand_grp"; 196 groups = "nand_grp";
193 }; 197 };
194}; 198};
199
200&qspi {
201 bspi-sel = <0>;
202 flash: m25p80@0 {
203 #address-cells = <1>;
204 #size-cells = <1>;
205 compatible = "m25p80";
206 reg = <0x0>;
207 spi-max-frequency = <12500000>;
208 m25p,fast-read;
209 spi-cpol;
210 spi-cpha;
211
212 partition@0 {
213 label = "boot";
214 reg = <0x00000000 0x000a0000>;
215 };
216
217 partition@a0000 {
218 label = "env";
219 reg = <0x000a0000 0x00060000>;
220 };
221
222 partition@100000 {
223 label = "system";
224 reg = <0x00100000 0x00600000>;
225 };
226
227 partition@700000 {
228 label = "rootfs";
229 reg = <0x00700000 0x01900000>;
230 };
231 };
232};
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index 773ed593da4d..4fcdeca3a983 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -133,6 +133,9 @@
133 133
134 status = "disabled"; 134 status = "disabled";
135 135
136 phys = <&pci_phy0>;
137 phy-names = "pcie-phy";
138
136 msi-parent = <&msi0>; 139 msi-parent = <&msi0>;
137 msi0: msi@20020000 { 140 msi0: msi@20020000 {
138 compatible = "brcm,iproc-msi"; 141 compatible = "brcm,iproc-msi";
@@ -171,6 +174,9 @@
171 174
172 status = "disabled"; 175 status = "disabled";
173 176
177 phys = <&pci_phy1>;
178 phy-names = "pcie-phy";
179
174 msi-parent = <&msi4>; 180 msi-parent = <&msi4>;
175 msi4: msi@50020000 { 181 msi4: msi@50020000 {
176 compatible = "brcm,iproc-msi"; 182 compatible = "brcm,iproc-msi";
@@ -203,6 +209,42 @@
203 status = "disabled"; 209 status = "disabled";
204 }; 210 };
205 211
212 pdc0: iproc-pdc0@612c0000 {
213 compatible = "brcm,iproc-pdc-mbox";
214 reg = <0x612c0000 0x445>; /* PDC FS0 regs */
215 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
216 #mbox-cells = <1>;
217 brcm,rx-status-len = <32>;
218 brcm,use-bcm-hdr;
219 };
220
221 pdc1: iproc-pdc1@612e0000 {
222 compatible = "brcm,iproc-pdc-mbox";
223 reg = <0x612e0000 0x445>; /* PDC FS1 regs */
224 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
225 #mbox-cells = <1>;
226 brcm,rx-status-len = <32>;
227 brcm,use-bcm-hdr;
228 };
229
230 pdc2: iproc-pdc2@61300000 {
231 compatible = "brcm,iproc-pdc-mbox";
232 reg = <0x61300000 0x445>; /* PDC FS2 regs */
233 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
234 #mbox-cells = <1>;
235 brcm,rx-status-len = <32>;
236 brcm,use-bcm-hdr;
237 };
238
239 pdc3: iproc-pdc3@61320000 {
240 compatible = "brcm,iproc-pdc-mbox";
241 reg = <0x61320000 0x445>; /* PDC FS3 regs */
242 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
243 #mbox-cells = <1>;
244 brcm,rx-status-len = <32>;
245 brcm,use-bcm-hdr;
246 };
247
206 dma0: dma@61360000 { 248 dma0: dma@61360000 {
207 compatible = "arm,pl330", "arm,primecell"; 249 compatible = "arm,pl330", "arm,primecell";
208 reg = <0x61360000 0x1000>; 250 reg = <0x61360000 0x1000>;
@@ -260,7 +302,7 @@
260 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 304 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
263 mmu-masters; 305 #iommu-cells = <1>;
264 }; 306 };
265 307
266 pinctrl: pinctrl@6501d130 { 308 pinctrl: pinctrl@6501d130 {
@@ -577,5 +619,23 @@
577 619
578 brcm,nand-has-wp; 620 brcm,nand-has-wp;
579 }; 621 };
622
623 qspi: spi@66470200 {
624 compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi";
625 reg = <0x66470200 0x184>,
626 <0x66470000 0x124>,
627 <0x67017408 0x004>,
628 <0x664703a0 0x01c>;
629 reg-names = "mspi", "bspi", "intr_regs",
630 "intr_status_reg";
631 interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
632 interrupt-names = "spi_l1_intr";
633 clocks = <&iprocmed>;
634 clock-names = "iprocmed";
635 num-cs = <2>;
636 #address-cells = <1>;
637 #size-cells = <0>;
638 };
639
580 }; 640 };
581}; 641};
diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile
index 50c9b9383cfa..7ddea53769a7 100644
--- a/arch/arm64/boot/dts/exynos/Makefile
+++ b/arch/arm64/boot/dts/exynos/Makefile
@@ -1,4 +1,7 @@
1dtb-$(CONFIG_ARCH_EXYNOS) += exynos7-espresso.dtb 1dtb-$(CONFIG_ARCH_EXYNOS) += \
2 exynos5433-tm2.dtb \
3 exynos5433-tm2e.dtb \
4 exynos7-espresso.dtb
2 5
3always := $(dtb-y) 6always := $(dtb-y)
4subdir-y := $(dts-dirs) 7subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
new file mode 100644
index 000000000000..ad71247b074f
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
@@ -0,0 +1,804 @@
1/*
2 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
3 *
4 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
5 * Chanwoo Choi <cw00.choi@samsung.com>
6 *
7 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
8 * tree nodes are listed in this file.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#define PIN_PULL_NONE 0
16#define PIN_PULL_DOWN 1
17#define PIN_PULL_UP 3
18
19#define PIN_DRV_LV1 0
20#define PIN_DRV_LV2 2
21#define PIN_DRV_LV3 1
22#define PIN_DRV_LV4 3
23
24#define PIN_IN 0
25#define PIN_OUT 1
26#define PIN_FUNC1 2
27
28#define PIN(_func, _pin, _pull, _drv) \
29 _pin { \
30 samsung,pins = #_pin; \
31 samsung,pin-function = <PIN_ ##_func>; \
32 samsung,pin-pud = <PIN_PULL_ ##_pull>; \
33 samsung,pin-drv = <PIN_DRV_ ##_drv>; \
34 }
35
36&pinctrl_alive {
37 gpa0: gpa0 {
38 gpio-controller;
39 #gpio-cells = <2>;
40
41 interrupt-controller;
42 interrupt-parent = <&gic>;
43 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
44 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
48 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
49 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
50 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
51 #interrupt-cells = <2>;
52 };
53
54 gpa1: gpa1 {
55 gpio-controller;
56 #gpio-cells = <2>;
57
58 interrupt-controller;
59 interrupt-parent = <&gic>;
60 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
68 #interrupt-cells = <2>;
69 };
70
71 gpa2: gpa2 {
72 gpio-controller;
73 #gpio-cells = <2>;
74
75 interrupt-controller;
76 #interrupt-cells = <2>;
77 };
78
79 gpa3: gpa3 {
80 gpio-controller;
81 #gpio-cells = <2>;
82
83 interrupt-controller;
84 #interrupt-cells = <2>;
85 };
86
87 gpf1: gpf1 {
88 gpio-controller;
89 #gpio-cells = <2>;
90
91 interrupt-controller;
92 #interrupt-cells = <2>;
93 };
94
95 gpf2: gpf2 {
96 gpio-controller;
97 #gpio-cells = <2>;
98
99 interrupt-controller;
100 #interrupt-cells = <2>;
101 };
102
103 gpf3: gpf3 {
104 gpio-controller;
105 #gpio-cells = <2>;
106
107 interrupt-controller;
108 #interrupt-cells = <2>;
109 };
110
111 gpf4: gpf4 {
112 gpio-controller;
113 #gpio-cells = <2>;
114
115 interrupt-controller;
116 #interrupt-cells = <2>;
117 };
118
119 gpf5: gpf5 {
120 gpio-controller;
121 #gpio-cells = <2>;
122
123 interrupt-controller;
124 #interrupt-cells = <2>;
125 };
126};
127
128&pinctrl_aud {
129 gpz0: gpz0 {
130 gpio-controller;
131 #gpio-cells = <2>;
132
133 interrupt-controller;
134 #interrupt-cells = <2>;
135 };
136
137 gpz1: gpz1 {
138 gpio-controller;
139 #gpio-cells = <2>;
140
141 interrupt-controller;
142 #interrupt-cells = <2>;
143 };
144
145 i2s0_bus: i2s0-bus {
146 samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3",
147 "gpz0-4", "gpz0-5", "gpz0-6";
148 samsung,pin-function = <2>;
149 samsung,pin-pud = <1>;
150 samsung,pin-drv = <0>;
151 };
152
153 pcm0_bus: pcm0-bus {
154 samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3";
155 samsung,pin-function = <3>;
156 samsung,pin-pud = <1>;
157 samsung,pin-drv = <0>;
158 };
159
160 uart_aud_bus: uart-aud-bus {
161 samsung,pins = "gpz1-3", "gpz1-2", "gpz1-1", "gpz1-0";
162 samsung,pin-function = <2>;
163 samsung,pin-pud = <0>;
164 samsung,pin-drv = <0>;
165 };
166};
167
168&pinctrl_cpif {
169 gpv6: gpv6 {
170 gpio-controller;
171 #gpio-cells = <2>;
172
173 interrupt-controller;
174 #interrupt-cells = <2>;
175 };
176};
177
178&pinctrl_ese {
179 gpj2: gpj2 {
180 gpio-controller;
181 #gpio-cells = <2>;
182
183 interrupt-controller;
184 #interrupt-cells = <2>;
185 };
186};
187
188&pinctrl_finger {
189 gpd5: gpd5 {
190 gpio-controller;
191 #gpio-cells = <2>;
192
193 interrupt-controller;
194 #interrupt-cells = <2>;
195 };
196
197 spi2_bus: spi2-bus {
198 samsung,pins = "gpd5-0", "gpd5-2", "gpd5-3";
199 samsung,pin-function = <2>;
200 samsung,pin-pud = <3>;
201 samsung,pin-drv = <0>;
202 };
203
204 hs_i2c6_bus: hs-i2c6-bus {
205 samsung,pins = "gpd5-3", "gpd5-2";
206 samsung,pin-function = <4>;
207 samsung,pin-pud = <3>;
208 samsung,pin-drv = <0>;
209 };
210};
211
212&pinctrl_fsys {
213 gph1: gph1 {
214 gpio-controller;
215 #gpio-cells = <2>;
216
217 interrupt-controller;
218 #interrupt-cells = <2>;
219 };
220
221 gpr4: gpr4 {
222 gpio-controller;
223 #gpio-cells = <2>;
224
225 interrupt-controller;
226 #interrupt-cells = <2>;
227 };
228
229 gpr0: gpr0 {
230 gpio-controller;
231 #gpio-cells = <2>;
232
233 interrupt-controller;
234 #interrupt-cells = <2>;
235 };
236
237 gpr1: gpr1 {
238 gpio-controller;
239 #gpio-cells = <2>;
240
241 interrupt-controller;
242 #interrupt-cells = <2>;
243 };
244
245 gpr2: gpr2 {
246 gpio-controller;
247 #gpio-cells = <2>;
248
249 interrupt-controller;
250 #interrupt-cells = <2>;
251 };
252
253 gpr3: gpr3 {
254 gpio-controller;
255 #gpio-cells = <2>;
256
257 interrupt-controller;
258 #interrupt-cells = <2>;
259 };
260
261 sd0_clk: sd0-clk {
262 samsung,pins = "gpr0-0";
263 samsung,pin-function = <2>;
264 samsung,pin-pud = <0>;
265 samsung,pin-drv = <3>;
266 };
267
268 sd0_cmd: sd0-cmd {
269 samsung,pins = "gpr0-1";
270 samsung,pin-function = <2>;
271 samsung,pin-pud = <0>;
272 samsung,pin-drv = <3>;
273 };
274
275 sd0_rdqs: sd0-rdqs {
276 samsung,pins = "gpr0-2";
277 samsung,pin-function = <2>;
278 samsung,pin-pud = <1>;
279 samsung,pin-drv = <3>;
280 };
281
282 sd0_qrdy: sd0-qrdy {
283 samsung,pins = "gpr0-3";
284 samsung,pin-function = <2>;
285 samsung,pin-pud = <1>;
286 samsung,pin-drv = <3>;
287 };
288
289 sd0_bus1: sd0-bus-width1 {
290 samsung,pins = "gpr1-0";
291 samsung,pin-function = <2>;
292 samsung,pin-pud = <3>;
293 samsung,pin-drv = <3>;
294 };
295
296 sd0_bus4: sd0-bus-width4 {
297 samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3";
298 samsung,pin-function = <2>;
299 samsung,pin-pud = <3>;
300 samsung,pin-drv = <3>;
301 };
302
303 sd0_bus8: sd0-bus-width8 {
304 samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7";
305 samsung,pin-function = <2>;
306 samsung,pin-pud = <3>;
307 samsung,pin-drv = <3>;
308 };
309
310 sd1_clk: sd1-clk {
311 samsung,pins = "gpr2-0";
312 samsung,pin-function = <2>;
313 samsung,pin-pud = <0>;
314 samsung,pin-drv = <3>;
315 };
316
317 sd1_cmd: sd1-cmd {
318 samsung,pins = "gpr2-1";
319 samsung,pin-function = <2>;
320 samsung,pin-pud = <0>;
321 samsung,pin-drv = <3>;
322 };
323
324 sd1_bus1: sd1-bus-width1 {
325 samsung,pins = "gpr3-0";
326 samsung,pin-function = <2>;
327 samsung,pin-pud = <3>;
328 samsung,pin-drv = <3>;
329 };
330
331 sd1_bus4: sd1-bus-width4 {
332 samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3";
333 samsung,pin-function = <2>;
334 samsung,pin-pud = <3>;
335 samsung,pin-drv = <3>;
336 };
337
338 sd1_bus8: sd1-bus-width8 {
339 samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
340 samsung,pin-function = <2>;
341 samsung,pin-pud = <3>;
342 samsung,pin-drv = <3>;
343 };
344
345 pcie_bus: pcie_bus {
346 samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
347 samsung,pin-function = <3>;
348 samsung,pin-pud = <3>;
349 };
350
351 sd2_clk: sd2-clk {
352 samsung,pins = "gpr4-0";
353 samsung,pin-function = <2>;
354 samsung,pin-pud = <0>;
355 samsung,pin-drv = <3>;
356 };
357
358 sd2_cmd: sd2-cmd {
359 samsung,pins = "gpr4-1";
360 samsung,pin-function = <2>;
361 samsung,pin-pud = <0>;
362 samsung,pin-drv = <3>;
363 };
364
365 sd2_cd: sd2-cd {
366 samsung,pins = "gpr4-2";
367 samsung,pin-function = <2>;
368 samsung,pin-pud = <3>;
369 samsung,pin-drv = <3>;
370 };
371
372 sd2_bus1: sd2-bus-width1 {
373 samsung,pins = "gpr4-3";
374 samsung,pin-function = <2>;
375 samsung,pin-pud = <3>;
376 samsung,pin-drv = <3>;
377 };
378
379 sd2_bus4: sd2-bus-width4 {
380 samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6";
381 samsung,pin-function = <2>;
382 samsung,pin-pud = <3>;
383 samsung,pin-drv = <3>;
384 };
385
386 sd2_clk_output: sd2-clk-output {
387 samsung,pins = "gpr4-0";
388 samsung,pin-function = <1>;
389 samsung,pin-pud = <0>;
390 samsung,pin-drv = <2>;
391 };
392
393 sd2_cmd_output: sd2-cmd-output {
394 samsung,pins = "gpr4-1";
395 samsung,pin-function = <1>;
396 samsung,pin-pud = <0>;
397 samsung,pin-drv = <2>;
398 };
399};
400
401&pinctrl_imem {
402 gpf0: gpf0 {
403 gpio-controller;
404 #gpio-cells = <2>;
405
406 interrupt-controller;
407 #interrupt-cells = <2>;
408 };
409};
410
411&pinctrl_nfc {
412 gpj0: gpj0 {
413 gpio-controller;
414 #gpio-cells = <2>;
415
416 interrupt-controller;
417 #interrupt-cells = <2>;
418 };
419
420 hs_i2c4_bus: hs-i2c4-bus {
421 samsung,pins = "gpj0-1", "gpj0-0";
422 samsung,pin-function = <4>;
423 samsung,pin-pud = <3>;
424 samsung,pin-drv = <0>;
425 };
426};
427
428&pinctrl_peric {
429 gpv7: gpv7 {
430 gpio-controller;
431 #gpio-cells = <2>;
432
433 interrupt-controller;
434 #interrupt-cells = <2>;
435 };
436
437 gpb0: gpb0 {
438 gpio-controller;
439 #gpio-cells = <2>;
440
441 interrupt-controller;
442 #interrupt-cells = <2>;
443 };
444
445 gpc0: gpc0 {
446 gpio-controller;
447 #gpio-cells = <2>;
448
449 interrupt-controller;
450 #interrupt-cells = <2>;
451 };
452
453 gpc1: gpc1 {
454 gpio-controller;
455 #gpio-cells = <2>;
456
457 interrupt-controller;
458 #interrupt-cells = <2>;
459 };
460
461 gpc2: gpc2 {
462 gpio-controller;
463 #gpio-cells = <2>;
464
465 interrupt-controller;
466 #interrupt-cells = <2>;
467 };
468
469 gpc3: gpc3 {
470 gpio-controller;
471 #gpio-cells = <2>;
472
473 interrupt-controller;
474 #interrupt-cells = <2>;
475 };
476
477 gpg0: gpg0 {
478 gpio-controller;
479 #gpio-cells = <2>;
480
481 interrupt-controller;
482 #interrupt-cells = <2>;
483 };
484
485 gpd0: gpd0 {
486 gpio-controller;
487 #gpio-cells = <2>;
488
489 interrupt-controller;
490 #interrupt-cells = <2>;
491 };
492
493 gpd1: gpd1 {
494 gpio-controller;
495 #gpio-cells = <2>;
496
497 interrupt-controller;
498 #interrupt-cells = <2>;
499 };
500
501 gpd2: gpd2 {
502 gpio-controller;
503 #gpio-cells = <2>;
504
505 interrupt-controller;
506 #interrupt-cells = <2>;
507 };
508
509 gpd4: gpd4 {
510 gpio-controller;
511 #gpio-cells = <2>;
512
513 interrupt-controller;
514 #interrupt-cells = <2>;
515 };
516
517 gpd8: gpd8 {
518 gpio-controller;
519 #gpio-cells = <2>;
520
521 interrupt-controller;
522 #interrupt-cells = <2>;
523 };
524
525 gpd6: gpd6 {
526 gpio-controller;
527 #gpio-cells = <2>;
528
529 interrupt-controller;
530 #interrupt-cells = <2>;
531 };
532
533 gpd7: gpd7 {
534 gpio-controller;
535 #gpio-cells = <2>;
536
537 interrupt-controller;
538 #interrupt-cells = <2>;
539 };
540
541 gpg1: gpg1 {
542 gpio-controller;
543 #gpio-cells = <2>;
544
545 interrupt-controller;
546 #interrupt-cells = <2>;
547 };
548
549 gpg2: gpg2 {
550 gpio-controller;
551 #gpio-cells = <2>;
552
553 interrupt-controller;
554 #interrupt-cells = <2>;
555 };
556
557 gpg3: gpg3 {
558 gpio-controller;
559 #gpio-cells = <2>;
560
561 interrupt-controller;
562 #interrupt-cells = <2>;
563 };
564
565 hs_i2c8_bus: hs-i2c8-bus {
566 samsung,pins = "gpb0-1", "gpb0-0";
567 samsung,pin-function = <4>;
568 samsung,pin-pud = <3>;
569 samsung,pin-drv = <0>;
570 };
571
572 hs_i2c9_bus: hs-i2c9-bus {
573 samsung,pins = "gpb0-3", "gpb0-2";
574 samsung,pin-function = <4>;
575 samsung,pin-pud = <3>;
576 samsung,pin-drv = <0>;
577 };
578
579 i2s1_bus: i2s1-bus {
580 samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2",
581 "gpd4-3", "gpd4-4";
582 samsung,pin-function = <2>;
583 samsung,pin-pud = <1>;
584 samsung,pin-drv = <0>;
585 };
586
587 pcm1_bus: pcm1-bus {
588 samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2",
589 "gpd4-3", "gpd4-4";
590 samsung,pin-function = <3>;
591 samsung,pin-pud = <1>;
592 samsung,pin-drv = <0>;
593 };
594
595 spdif_bus: spdif-bus {
596 samsung,pins = "gpd4-3", "gpd4-4";
597 samsung,pin-function = <4>;
598 samsung,pin-pud = <1>;
599 samsung,pin-drv = <0>;
600 };
601
602 fimc_is_spi_pin0: fimc-is-spi-pin0 {
603 samsung,pins = "gpc3-3", "gpc3-2", "gpc3-1", "gpc3-0";
604 samsung,pin-function = <2>;
605 samsung,pin-pud = <0>;
606 samsung,pin-drv = <0>;
607 };
608
609 fimc_is_spi_pin1: fimc-is-spi-pin1 {
610 samsung,pins = "gpc3-7", "gpc3-6", "gpc3-5", "gpc3-4";
611 samsung,pin-function = <2>;
612 samsung,pin-pud = <0>;
613 samsung,pin-drv = <0>;
614 };
615
616 uart0_bus: uart0-bus {
617 samsung,pins = "gpd0-3", "gpd0-2", "gpd0-1", "gpd0-0";
618 samsung,pin-function = <2>;
619 samsung,pin-pud = <0>;
620 };
621
622 hs_i2c2_bus: hs-i2c2-bus {
623 samsung,pins = "gpd0-3", "gpd0-2";
624 samsung,pin-function = <3>;
625 samsung,pin-pud = <3>;
626 samsung,pin-drv = <0>;
627 };
628
629 uart2_bus: uart2-bus {
630 samsung,pins = "gpd1-5", "gpd1-4";
631 samsung,pin-function = <2>;
632 samsung,pin-pud = <0>;
633 };
634
635 uart1_bus: uart1-bus {
636 samsung,pins = "gpd1-3", "gpd1-2", "gpd1-1", "gpd1-0";
637 samsung,pin-function = <2>;
638 samsung,pin-pud = <0>;
639 };
640
641 hs_i2c3_bus: hs-i2c3-bus {
642 samsung,pins = "gpd1-3", "gpd1-2";
643 samsung,pin-function = <3>;
644 samsung,pin-pud = <3>;
645 samsung,pin-drv = <0>;
646 };
647
648 hs_i2c0_bus: hs-i2c0-bus {
649 samsung,pins = "gpd2-1", "gpd2-0";
650 samsung,pin-function = <2>;
651 samsung,pin-pud = <3>;
652 samsung,pin-drv = <0>;
653 };
654
655 hs_i2c1_bus: hs-i2c1-bus {
656 samsung,pins = "gpd2-3", "gpd2-2";
657 samsung,pin-function = <2>;
658 samsung,pin-pud = <3>;
659 samsung,pin-drv = <0>;
660 };
661
662 pwm0_out: pwm0-out {
663 samsung,pins = "gpd2-4";
664 samsung,pin-function = <2>;
665 samsung,pin-pud = <0>;
666 samsung,pin-drv = <0>;
667 };
668
669 pwm1_out: pwm1-out {
670 samsung,pins = "gpd2-5";
671 samsung,pin-function = <2>;
672 samsung,pin-pud = <0>;
673 samsung,pin-drv = <0>;
674 };
675
676 pwm2_out: pwm2-out {
677 samsung,pins = "gpd2-6";
678 samsung,pin-function = <2>;
679 samsung,pin-pud = <0>;
680 samsung,pin-drv = <0>;
681 };
682
683 pwm3_out: pwm3-out {
684 samsung,pins = "gpd2-7";
685 samsung,pin-function = <2>;
686 samsung,pin-pud = <0>;
687 samsung,pin-drv = <0>;
688 };
689
690 spi1_bus: spi1-bus {
691 samsung,pins = "gpd6-2", "gpd6-4", "gpd6-5";
692 samsung,pin-function = <2>;
693 samsung,pin-pud = <3>;
694 samsung,pin-drv = <0>;
695 };
696
697 hs_i2c7_bus: hs-i2c7-bus {
698 samsung,pins = "gpd2-7", "gpd2-6";
699 samsung,pin-function = <4>;
700 samsung,pin-pud = <3>;
701 samsung,pin-drv = <0>;
702 };
703
704 spi0_bus: spi0-bus {
705 samsung,pins = "gpd8-0", "gpd6-0", "gpd6-1";
706 samsung,pin-function = <2>;
707 samsung,pin-pud = <3>;
708 samsung,pin-drv = <0>;
709 };
710
711 hs_i2c10_bus: hs-i2c10-bus {
712 samsung,pins = "gpg3-1", "gpg3-0";
713 samsung,pin-function = <4>;
714 samsung,pin-pud = <3>;
715 samsung,pin-drv = <0>;
716 };
717
718 hs_i2c11_bus: hs-i2c11-bus {
719 samsung,pins = "gpg3-3", "gpg3-2";
720 samsung,pin-function = <4>;
721 samsung,pin-pud = <3>;
722 samsung,pin-drv = <0>;
723 };
724
725 spi3_bus: spi3-bus {
726 samsung,pins = "gpg3-4", "gpg3-6", "gpg3-7";
727 samsung,pin-function = <3>;
728 samsung,pin-pud = <3>;
729 samsung,pin-drv = <0>;
730 };
731
732 spi4_bus: spi4-bus {
733 samsung,pins = "gpv7-1", "gpv7-3", "gpv7-4";
734 samsung,pin-function = <3>;
735 samsung,pin-pud = <3>;
736 samsung,pin-drv = <0>;
737 };
738
739 fimc_is_uart: fimc-is-uart {
740 samsung,pins = "gpc1-1", "gpc0-7";
741 samsung,pin-function = <3>;
742 samsung,pin-pud = <0>;
743 samsung,pin-drv = <0>;
744 };
745
746 fimc_is_ch0_i2c: fimc-is-ch0_i2c {
747 samsung,pins = "gpc2-1", "gpc2-0";
748 samsung,pin-function = <2>;
749 samsung,pin-pud = <0>;
750 samsung,pin-drv = <0>;
751 };
752
753 fimc_is_ch0_mclk: fimc-is-ch0_mclk {
754 samsung,pins = "gpd7-0";
755 samsung,pin-function = <2>;
756 samsung,pin-pud = <0>;
757 samsung,pin-drv = <0>;
758 };
759
760 fimc_is_ch1_i2c: fimc-is-ch1-i2c {
761 samsung,pins = "gpc2-3", "gpc2-2";
762 samsung,pin-function = <2>;
763 samsung,pin-pud = <0>;
764 samsung,pin-drv = <0>;
765 };
766
767 fimc_is_ch1_mclk: fimc-is-ch1-mclk {
768 samsung,pins = "gpd7-1";
769 samsung,pin-function = <2>;
770 samsung,pin-pud = <0>;
771 samsung,pin-drv = <0>;
772 };
773
774 fimc_is_ch2_i2c: fimc-is-ch2-i2c {
775 samsung,pins = "gpc2-5", "gpc2-4";
776 samsung,pin-function = <2>;
777 samsung,pin-pud = <0>;
778 samsung,pin-drv = <0>;
779 };
780
781 fimc_is_ch2_mclk: fimc-is-ch2-mclk {
782 samsung,pins = "gpd7-2";
783 samsung,pin-function = <2>;
784 samsung,pin-pud = <0>;
785 samsung,pin-drv = <0>;
786 };
787};
788
789&pinctrl_touch {
790 gpj1: gpj1 {
791 gpio-controller;
792 #gpio-cells = <2>;
793
794 interrupt-controller;
795 #interrupt-cells = <2>;
796 };
797
798 hs_i2c5_bus: hs-i2c5-bus {
799 samsung,pins = "gpj1-1", "gpj1-0";
800 samsung,pin-function = <4>;
801 samsung,pin-pud = <3>;
802 samsung,pin-drv = <0>;
803 };
804};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
new file mode 100644
index 000000000000..f21bdc2ff834
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -0,0 +1,1049 @@
1/*
2 * SAMSUNG Exynos5433 TM2 board device tree source
3 *
4 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
5 *
6 * Device tree source file for Samsung's TM2 board which is based on
7 * Samsung Exynos5433 SoC.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14/dts-v1/;
15#include "exynos5433.dtsi"
16#include <dt-bindings/clock/samsung,s2mps11.h>
17#include <dt-bindings/gpio/gpio.h>
18#include <dt-bindings/input/input.h>
19#include <dt-bindings/interrupt-controller/irq.h>
20
21/ {
22 model = "Samsung TM2 board";
23 compatible = "samsung,tm2", "samsung,exynos5433";
24
25 aliases {
26 gsc0 = &gsc_0;
27 gsc1 = &gsc_1;
28 gsc2 = &gsc_2;
29 pinctrl0 = &pinctrl_alive;
30 pinctrl1 = &pinctrl_aud;
31 pinctrl2 = &pinctrl_cpif;
32 pinctrl3 = &pinctrl_ese;
33 pinctrl4 = &pinctrl_finger;
34 pinctrl5 = &pinctrl_fsys;
35 pinctrl6 = &pinctrl_imem;
36 pinctrl7 = &pinctrl_nfc;
37 pinctrl8 = &pinctrl_peric;
38 pinctrl9 = &pinctrl_touch;
39 serial0 = &serial_0;
40 serial1 = &serial_1;
41 serial2 = &serial_2;
42 serial3 = &serial_3;
43 spi0 = &spi_0;
44 spi1 = &spi_1;
45 spi2 = &spi_2;
46 spi3 = &spi_3;
47 spi4 = &spi_4;
48 mshc0 = &mshc_0;
49 mshc2 = &mshc_2;
50 };
51
52 chosen {
53 stdout-path = &serial_1;
54 };
55
56 memory@20000000 {
57 device_type = "memory";
58 reg = <0x0 0x20000000 0x0 0xc0000000>;
59 };
60
61 gpio-keys {
62 compatible = "gpio-keys";
63
64 power-key {
65 gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
66 linux,code = <KEY_POWER>;
67 label = "power key";
68 debounce-interval = <10>;
69 };
70
71 volume-up-key {
72 gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
73 linux,code = <KEY_VOLUMEUP>;
74 label = "volume-up key";
75 debounce-interval = <10>;
76 };
77
78 volume-down-key {
79 gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
80 linux,code = <KEY_VOLUMEDOWN>;
81 label = "volume-down key";
82 debounce-interval = <10>;
83 };
84
85 homepage-key {
86 gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
87 linux,code = <KEY_MENU>;
88 label = "homepage key";
89 debounce-interval = <10>;
90 };
91 };
92
93 i2c_max98504: i2c-gpio-0 {
94 compatible = "i2c-gpio";
95 gpios = <&gpd0 1 GPIO_ACTIVE_HIGH /* SPK_AMP_SDA */
96 &gpd0 0 GPIO_ACTIVE_HIGH /* SPK_AMP_SCL */ >;
97 i2c-gpio,delay-us = <2>;
98 #address-cells = <1>;
99 #size-cells = <0>;
100 status = "okay";
101
102 max98504: max98504@31 {
103 compatible = "maxim,max98504";
104 reg = <0x31>;
105 maxim,rx-path = <1>;
106 maxim,tx-path = <1>;
107 maxim,tx-channel-mask = <3>;
108 maxim,tx-channel-source = <2>;
109 };
110 };
111
112 sound {
113 compatible = "samsung,tm2-audio";
114 audio-codec = <&wm5110>;
115 i2s-controller = <&i2s0>;
116 audio-amplifier = <&max98504>;
117 mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
118 model = "wm5110";
119 samsung,audio-routing =
120 /* Headphone */
121 "HP", "HPOUT1L",
122 "HP", "HPOUT1R",
123
124 /* Speaker */
125 "SPK", "SPKOUT",
126 "SPKOUT", "HPOUT2L",
127 "SPKOUT", "HPOUT2R",
128
129 /* Receiver */
130 "RCV", "HPOUT3L",
131 "RCV", "HPOUT3R";
132 status = "okay";
133 };
134};
135
136&adc {
137 vdd-supply = <&ldo3_reg>;
138 status = "okay";
139
140 thermistor-ap {
141 compatible = "murata,ncp03wf104";
142 pullup-uv = <1800000>;
143 pullup-ohm = <100000>;
144 pulldown-ohm = <0>;
145 io-channels = <&adc 0>;
146 };
147
148 thermistor-battery {
149 compatible = "murata,ncp03wf104";
150 pullup-uv = <1800000>;
151 pullup-ohm = <100000>;
152 pulldown-ohm = <0>;
153 io-channels = <&adc 1>;
154 #thermal-sensor-cells = <0>;
155 };
156
157 thermistor-charger {
158 compatible = "murata,ncp03wf104";
159 pullup-uv = <1800000>;
160 pullup-ohm = <100000>;
161 pulldown-ohm = <0>;
162 io-channels = <&adc 2>;
163 };
164};
165
166&cmu_aud {
167 assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>;
168 assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
169};
170
171&cmu_fsys {
172 assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
173 <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
174 <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
175 <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
176 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
177 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
178 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
179 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
180 <&cmu_top CLK_DIV_SCLK_USBDRD30>,
181 <&cmu_top CLK_DIV_SCLK_USBHOST30>;
182 assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
183 <&cmu_top CLK_MOUT_BUS_PLL_USER>,
184 <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
185 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
186 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
187 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
188 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
189 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
190 assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
191 <66700000>, <66700000>;
192};
193
194&cmu_gscl {
195 assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>,
196 <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>;
197 assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
198 <&cmu_top CLK_ACLK_GSCL_333>;
199};
200
201&cmu_mfc {
202 assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>;
203 assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
204};
205
206&cmu_mscl {
207 assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
208 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
209 <&cmu_mscl CLK_MOUT_SCLK_JPEG>,
210 <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
211 assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
212 <&cmu_top CLK_SCLK_JPEG_MSCL>,
213 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
214 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
215};
216
217&cpu0 {
218 cpu-supply = <&buck3_reg>;
219};
220
221&cpu4 {
222 cpu-supply = <&buck2_reg>;
223};
224
225&decon {
226 status = "okay";
227
228 i80-if-timings {
229 };
230};
231
232&dsi {
233 status = "okay";
234 vddcore-supply = <&ldo6_reg>;
235 vddio-supply = <&ldo7_reg>;
236 samsung,pll-clock-frequency = <24000000>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&te_irq>;
239
240 ports {
241 #address-cells = <1>;
242 #size-cells = <0>;
243
244 port@1 {
245 reg = <1>;
246
247 dsi_out: endpoint {
248 samsung,burst-clock-frequency = <512000000>;
249 samsung,esc-clock-frequency = <16000000>;
250 };
251 };
252 };
253};
254
255&hsi2c_0 {
256 status = "okay";
257 clock-frequency = <2500000>;
258
259 s2mps13-pmic@66 {
260 compatible = "samsung,s2mps13-pmic";
261 interrupt-parent = <&gpa0>;
262 interrupts = <7 IRQ_TYPE_NONE>;
263 reg = <0x66>;
264 samsung,s2mps11-wrstbi-ground;
265
266 s2mps13_osc: clocks {
267 compatible = "samsung,s2mps13-clk";
268 #clock-cells = <1>;
269 clock-output-names = "s2mps13_ap", "s2mps13_cp",
270 "s2mps13_bt";
271 };
272
273 regulators {
274 ldo1_reg: LDO1 {
275 regulator-name = "VDD_ALIVE_0.9V_AP";
276 regulator-min-microvolt = <900000>;
277 regulator-max-microvolt = <900000>;
278 regulator-always-on;
279 };
280
281 ldo2_reg: LDO2 {
282 regulator-name = "VDDQ_MMC2_2.8V_AP";
283 regulator-min-microvolt = <2800000>;
284 regulator-max-microvolt = <2800000>;
285 regulator-always-on;
286 regulator-state-mem {
287 regulator-off-in-suspend;
288 };
289 };
290
291 ldo3_reg: LDO3 {
292 regulator-name = "VDD1_E_1.8V_AP";
293 regulator-min-microvolt = <1800000>;
294 regulator-max-microvolt = <1800000>;
295 regulator-always-on;
296 };
297
298 ldo4_reg: LDO4 {
299 regulator-name = "VDD10_MIF_PLL_1.0V_AP";
300 regulator-min-microvolt = <1300000>;
301 regulator-max-microvolt = <1300000>;
302 regulator-always-on;
303 regulator-state-mem {
304 regulator-off-in-suspend;
305 };
306 };
307
308 ldo5_reg: LDO5 {
309 regulator-name = "VDD10_DPLL_1.0V_AP";
310 regulator-min-microvolt = <1000000>;
311 regulator-max-microvolt = <1000000>;
312 regulator-always-on;
313 regulator-state-mem {
314 regulator-off-in-suspend;
315 };
316 };
317
318 ldo6_reg: LDO6 {
319 regulator-name = "VDD10_MIPI2L_1.0V_AP";
320 regulator-min-microvolt = <1000000>;
321 regulator-max-microvolt = <1000000>;
322 regulator-state-mem {
323 regulator-off-in-suspend;
324 };
325 };
326
327 ldo7_reg: LDO7 {
328 regulator-name = "VDD18_MIPI2L_1.8V_AP";
329 regulator-min-microvolt = <1800000>;
330 regulator-max-microvolt = <1800000>;
331 };
332
333 ldo8_reg: LDO8 {
334 regulator-name = "VDD18_LLI_1.8V_AP";
335 regulator-min-microvolt = <1800000>;
336 regulator-max-microvolt = <1800000>;
337 regulator-always-on;
338 regulator-state-mem {
339 regulator-off-in-suspend;
340 };
341 };
342
343 ldo9_reg: LDO9 {
344 regulator-name = "VDD18_ABB_ETC_1.8V_AP";
345 regulator-min-microvolt = <1800000>;
346 regulator-max-microvolt = <1800000>;
347 regulator-always-on;
348 regulator-state-mem {
349 regulator-off-in-suspend;
350 };
351 };
352
353 ldo10_reg: LDO10 {
354 regulator-name = "VDD33_USB30_3.0V_AP";
355 regulator-min-microvolt = <3000000>;
356 regulator-max-microvolt = <3000000>;
357 regulator-state-mem {
358 regulator-off-in-suspend;
359 };
360 };
361
362 ldo11_reg: LDO11 {
363 regulator-name = "VDD_INT_M_1.0V_AP";
364 regulator-min-microvolt = <1000000>;
365 regulator-max-microvolt = <1000000>;
366 regulator-always-on;
367 regulator-state-mem {
368 regulator-off-in-suspend;
369 };
370 };
371
372 ldo12_reg: LDO12 {
373 regulator-name = "VDD_KFC_M_1.1V_AP";
374 regulator-min-microvolt = <800000>;
375 regulator-max-microvolt = <1350000>;
376 regulator-always-on;
377 };
378
379 ldo13_reg: LDO13 {
380 regulator-name = "VDD_G3D_M_0.95V_AP";
381 regulator-min-microvolt = <950000>;
382 regulator-max-microvolt = <950000>;
383 regulator-always-on;
384 regulator-state-mem {
385 regulator-off-in-suspend;
386 };
387 };
388
389 ldo14_reg: LDO14 {
390 regulator-name = "VDDQ_M1_LDO_1.2V_AP";
391 regulator-min-microvolt = <1200000>;
392 regulator-max-microvolt = <1200000>;
393 regulator-always-on;
394 regulator-state-mem {
395 regulator-off-in-suspend;
396 };
397 };
398
399 ldo15_reg: LDO15 {
400 regulator-name = "VDDQ_M2_LDO_1.2V_AP";
401 regulator-min-microvolt = <1200000>;
402 regulator-max-microvolt = <1200000>;
403 regulator-always-on;
404 regulator-state-mem {
405 regulator-off-in-suspend;
406 };
407 };
408
409 ldo16_reg: LDO16 {
410 regulator-name = "VDDQ_EFUSE";
411 regulator-min-microvolt = <1400000>;
412 regulator-max-microvolt = <3400000>;
413 regulator-always-on;
414 };
415
416 ldo17_reg: LDO17 {
417 regulator-name = "V_TFLASH_2.8V_AP";
418 regulator-min-microvolt = <2800000>;
419 regulator-max-microvolt = <2800000>;
420 };
421
422 ldo18_reg: LDO18 {
423 regulator-name = "V_CODEC_1.8V_AP";
424 regulator-min-microvolt = <1800000>;
425 regulator-max-microvolt = <1800000>;
426 };
427
428 ldo19_reg: LDO19 {
429 regulator-name = "VDDA_1.8V_COMP";
430 regulator-min-microvolt = <1800000>;
431 regulator-max-microvolt = <1800000>;
432 regulator-always-on;
433 };
434
435 ldo20_reg: LDO20 {
436 regulator-name = "VCC_2.8V_AP";
437 regulator-min-microvolt = <2800000>;
438 regulator-max-microvolt = <2800000>;
439 regulator-always-on;
440 };
441
442 ldo21_reg: LDO21 {
443 regulator-name = "VT_CAM_1.8V";
444 regulator-min-microvolt = <1800000>;
445 regulator-max-microvolt = <1800000>;
446 };
447
448 ldo22_reg: LDO22 {
449 regulator-name = "CAM_IO_1.8V_AP";
450 regulator-min-microvolt = <1800000>;
451 regulator-max-microvolt = <1800000>;
452 };
453
454 ldo23_reg: LDO23 {
455 regulator-name = "CAM_SEN_CORE_1.2V_AP";
456 regulator-min-microvolt = <1050000>;
457 regulator-max-microvolt = <1200000>;
458 };
459
460 ldo24_reg: LDO24 {
461 regulator-name = "VT_CAM_1.2V";
462 regulator-min-microvolt = <1200000>;
463 regulator-max-microvolt = <1200000>;
464 };
465
466 ldo25_reg: LDO25 {
467 regulator-name = "CAM_SEN_A2.8V_AP";
468 regulator-min-microvolt = <2800000>;
469 regulator-max-microvolt = <2800000>;
470 };
471
472 ldo26_reg: LDO26 {
473 regulator-name = "CAM_AF_2.8V_AP";
474 regulator-min-microvolt = <2800000>;
475 regulator-max-microvolt = <2800000>;
476 };
477
478 ldo27_reg: LDO27 {
479 regulator-name = "VCC_3.0V_LCD_AP";
480 regulator-min-microvolt = <3000000>;
481 regulator-max-microvolt = <3000000>;
482 };
483
484 ldo28_reg: LDO28 {
485 regulator-name = "VCC_1.8V_LCD_AP";
486 regulator-min-microvolt = <1800000>;
487 regulator-max-microvolt = <1800000>;
488 };
489
490 ldo29_reg: LDO29 {
491 regulator-name = "VT_CAM_2.8V";
492 regulator-min-microvolt = <3000000>;
493 regulator-max-microvolt = <3000000>;
494 };
495
496 ldo30_reg: LDO30 {
497 regulator-name = "TSP_AVDD_3.3V_AP";
498 regulator-min-microvolt = <3300000>;
499 regulator-max-microvolt = <3300000>;
500 };
501
502 ldo31_reg: LDO31 {
503 regulator-name = "TSP_VDD_1.85V_AP";
504 regulator-min-microvolt = <1850000>;
505 regulator-max-microvolt = <1850000>;
506 };
507
508 ldo32_reg: LDO32 {
509 regulator-name = "VTOUCH_1.8V_AP";
510 regulator-min-microvolt = <1800000>;
511 regulator-max-microvolt = <1800000>;
512 };
513
514 ldo33_reg: LDO33 {
515 regulator-name = "VTOUCH_LED_3.3V";
516 regulator-min-microvolt = <2500000>;
517 regulator-max-microvolt = <3300000>;
518 regulator-ramp-delay = <12500>;
519 };
520
521 ldo34_reg: LDO34 {
522 regulator-name = "VCC_1.8V_MHL_AP";
523 regulator-min-microvolt = <1000000>;
524 regulator-max-microvolt = <2100000>;
525 };
526
527 ldo35_reg: LDO35 {
528 regulator-name = "OIS_VM_2.8V";
529 regulator-min-microvolt = <1800000>;
530 regulator-max-microvolt = <2800000>;
531 };
532
533 ldo36_reg: LDO36 {
534 regulator-name = "VSIL_1.0V";
535 regulator-min-microvolt = <1000000>;
536 regulator-max-microvolt = <1000000>;
537 };
538
539 ldo37_reg: LDO37 {
540 regulator-name = "VF_1.8V";
541 regulator-min-microvolt = <1800000>;
542 regulator-max-microvolt = <1800000>;
543 };
544
545 ldo38_reg: LDO38 {
546 regulator-name = "VCC_3.0V_MOTOR_AP";
547 regulator-min-microvolt = <3000000>;
548 regulator-max-microvolt = <3000000>;
549 };
550
551 ldo39_reg: LDO39 {
552 regulator-name = "V_HRM_1.8V";
553 regulator-min-microvolt = <1800000>;
554 regulator-max-microvolt = <1800000>;
555 };
556
557 ldo40_reg: LDO40 {
558 regulator-name = "V_HRM_3.3V";
559 regulator-min-microvolt = <3300000>;
560 regulator-max-microvolt = <3300000>;
561 };
562
563 buck1_reg: BUCK1 {
564 regulator-name = "VDD_MIF_0.9V_AP";
565 regulator-min-microvolt = <600000>;
566 regulator-max-microvolt = <1500000>;
567 regulator-always-on;
568 regulator-state-mem {
569 regulator-off-in-suspend;
570 };
571 };
572
573 buck2_reg: BUCK2 {
574 regulator-name = "VDD_EGL_1.0V_AP";
575 regulator-min-microvolt = <900000>;
576 regulator-max-microvolt = <1300000>;
577 regulator-always-on;
578 regulator-state-mem {
579 regulator-off-in-suspend;
580 };
581 };
582
583 buck3_reg: BUCK3 {
584 regulator-name = "VDD_KFC_1.0V_AP";
585 regulator-min-microvolt = <800000>;
586 regulator-max-microvolt = <1200000>;
587 regulator-always-on;
588 regulator-state-mem {
589 regulator-off-in-suspend;
590 };
591 };
592
593 buck4_reg: BUCK4 {
594 regulator-name = "VDD_INT_0.95V_AP";
595 regulator-min-microvolt = <600000>;
596 regulator-max-microvolt = <1500000>;
597 regulator-always-on;
598 regulator-state-mem {
599 regulator-off-in-suspend;
600 };
601 };
602
603 buck5_reg: BUCK5 {
604 regulator-name = "VDD_DISP_CAM0_0.9V_AP";
605 regulator-min-microvolt = <600000>;
606 regulator-max-microvolt = <1500000>;
607 regulator-always-on;
608 regulator-state-mem {
609 regulator-off-in-suspend;
610 };
611 };
612
613 buck6_reg: BUCK6 {
614 regulator-name = "VDD_G3D_0.9V_AP";
615 regulator-min-microvolt = <600000>;
616 regulator-max-microvolt = <1500000>;
617 regulator-always-on;
618 regulator-state-mem {
619 regulator-off-in-suspend;
620 };
621 };
622
623 buck7_reg: BUCK7 {
624 regulator-name = "VDD_MEM1_1.2V_AP";
625 regulator-min-microvolt = <1200000>;
626 regulator-max-microvolt = <1200000>;
627 regulator-always-on;
628 };
629
630 buck8_reg: BUCK8 {
631 regulator-name = "VDD_LLDO_1.35V_AP";
632 regulator-min-microvolt = <1350000>;
633 regulator-max-microvolt = <3300000>;
634 regulator-always-on;
635 };
636
637 buck9_reg: BUCK9 {
638 regulator-name = "VDD_MLDO_2.0V_AP";
639 regulator-min-microvolt = <1350000>;
640 regulator-max-microvolt = <3300000>;
641 regulator-always-on;
642 };
643
644 buck10_reg: BUCK10 {
645 regulator-name = "vdd_mem2";
646 regulator-min-microvolt = <550000>;
647 regulator-max-microvolt = <1500000>;
648 regulator-always-on;
649 };
650 };
651 };
652};
653
654&hsi2c_8 {
655 status = "okay";
656
657 max77843@66 {
658 compatible = "maxim,max77843";
659 interrupt-parent = <&gpa1>;
660 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
661 reg = <0x66>;
662
663 muic: max77843-muic {
664 compatible = "maxim,max77843-muic";
665 };
666
667 regulators {
668 compatible = "maxim,max77843-regulator";
669 safeout1_reg: SAFEOUT1 {
670 regulator-name = "SAFEOUT1";
671 regulator-min-microvolt = <3300000>;
672 regulator-max-microvolt = <4950000>;
673 };
674
675 safeout2_reg: SAFEOUT2 {
676 regulator-name = "SAFEOUT2";
677 regulator-min-microvolt = <3300000>;
678 regulator-max-microvolt = <4950000>;
679 };
680
681 charger_reg: CHARGER {
682 regulator-name = "CHARGER";
683 regulator-min-microamp = <100000>;
684 regulator-max-microamp = <3150000>;
685 };
686 };
687
688 haptic: max77843-haptic {
689 compatible = "maxim,max77843-haptic";
690 haptic-supply = <&ldo38_reg>;
691 pwms = <&pwm 0 33670 0>;
692 pwm-names = "haptic";
693 };
694 };
695};
696
697&i2s0 {
698 status = "okay";
699};
700
701&mshc_0 {
702 status = "okay";
703 num-slots = <1>;
704 mmc-hs200-1_8v;
705 mmc-hs400-1_8v;
706 cap-mmc-highspeed;
707 non-removable;
708 card-detect-delay = <200>;
709 samsung,dw-mshc-ciu-div = <3>;
710 samsung,dw-mshc-sdr-timing = <0 4>;
711 samsung,dw-mshc-ddr-timing = <0 2>;
712 samsung,dw-mshc-hs400-timing = <0 3>;
713 samsung,read-strobe-delay = <90>;
714 fifo-depth = <0x80>;
715 pinctrl-names = "default";
716 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
717 &sd0_bus8 &sd0_rdqs>;
718 bus-width = <8>;
719 assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
720 assigned-clock-rates = <800000000>;
721};
722
723&mshc_2 {
724 status = "okay";
725 num-slots = <1>;
726 cap-sd-highspeed;
727 disable-wp;
728 cd-gpios = <&gpa2 4 GPIO_ACTIVE_HIGH>;
729 cd-inverted;
730 card-detect-delay = <200>;
731 samsung,dw-mshc-ciu-div = <3>;
732 samsung,dw-mshc-sdr-timing = <0 4>;
733 samsung,dw-mshc-ddr-timing = <0 2>;
734 fifo-depth = <0x80>;
735 pinctrl-names = "default";
736 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
737 bus-width = <4>;
738};
739
740&pinctrl_alive {
741 pinctrl-names = "default";
742 pinctrl-0 = <&initial_alive>;
743
744 initial_alive: initial-state {
745 PIN(IN, gpa0-0, DOWN, LV1);
746 PIN(IN, gpa0-1, NONE, LV1);
747 PIN(IN, gpa0-2, DOWN, LV1);
748 PIN(IN, gpa0-3, NONE, LV1);
749 PIN(IN, gpa0-4, NONE, LV1);
750 PIN(IN, gpa0-5, DOWN, LV1);
751 PIN(IN, gpa0-6, NONE, LV1);
752 PIN(IN, gpa0-7, NONE, LV1);
753
754 PIN(IN, gpa1-0, UP, LV1);
755 PIN(IN, gpa1-1, NONE, LV1);
756 PIN(IN, gpa1-2, NONE, LV1);
757 PIN(IN, gpa1-3, DOWN, LV1);
758 PIN(IN, gpa1-4, DOWN, LV1);
759 PIN(IN, gpa1-5, NONE, LV1);
760 PIN(IN, gpa1-6, NONE, LV1);
761 PIN(IN, gpa1-7, NONE, LV1);
762
763 PIN(IN, gpa2-0, NONE, LV1);
764 PIN(IN, gpa2-1, NONE, LV1);
765 PIN(IN, gpa2-2, NONE, LV1);
766 PIN(IN, gpa2-3, DOWN, LV1);
767 PIN(IN, gpa2-4, NONE, LV1);
768 PIN(IN, gpa2-5, DOWN, LV1);
769 PIN(IN, gpa2-6, DOWN, LV1);
770 PIN(IN, gpa2-7, NONE, LV1);
771
772 PIN(IN, gpa3-0, DOWN, LV1);
773 PIN(IN, gpa3-1, DOWN, LV1);
774 PIN(IN, gpa3-2, NONE, LV1);
775 PIN(IN, gpa3-3, DOWN, LV1);
776 PIN(IN, gpa3-4, NONE, LV1);
777 PIN(IN, gpa3-5, DOWN, LV1);
778 PIN(IN, gpa3-6, DOWN, LV1);
779 PIN(IN, gpa3-7, DOWN, LV1);
780
781 PIN(IN, gpf1-0, NONE, LV1);
782 PIN(IN, gpf1-1, NONE, LV1);
783 PIN(IN, gpf1-2, DOWN, LV1);
784 PIN(IN, gpf1-4, UP, LV1);
785 PIN(OUT, gpf1-5, NONE, LV1);
786 PIN(IN, gpf1-6, DOWN, LV1);
787 PIN(IN, gpf1-7, DOWN, LV1);
788
789 PIN(IN, gpf2-0, DOWN, LV1);
790 PIN(IN, gpf2-1, DOWN, LV1);
791 PIN(IN, gpf2-2, DOWN, LV1);
792 PIN(IN, gpf2-3, DOWN, LV1);
793
794 PIN(IN, gpf3-0, DOWN, LV1);
795 PIN(IN, gpf3-1, DOWN, LV1);
796 PIN(IN, gpf3-2, NONE, LV1);
797 PIN(IN, gpf3-3, DOWN, LV1);
798
799 PIN(IN, gpf4-0, DOWN, LV1);
800 PIN(IN, gpf4-1, DOWN, LV1);
801 PIN(IN, gpf4-2, DOWN, LV1);
802 PIN(IN, gpf4-3, DOWN, LV1);
803 PIN(IN, gpf4-4, DOWN, LV1);
804 PIN(IN, gpf4-5, DOWN, LV1);
805 PIN(IN, gpf4-6, DOWN, LV1);
806 PIN(IN, gpf4-7, DOWN, LV1);
807
808 PIN(IN, gpf5-0, DOWN, LV1);
809 PIN(IN, gpf5-1, DOWN, LV1);
810 PIN(IN, gpf5-2, DOWN, LV1);
811 PIN(IN, gpf5-3, DOWN, LV1);
812 PIN(OUT, gpf5-4, NONE, LV1);
813 PIN(IN, gpf5-5, DOWN, LV1);
814 PIN(IN, gpf5-6, DOWN, LV1);
815 PIN(IN, gpf5-7, DOWN, LV1);
816 };
817
818 te_irq: te_irq {
819 samsung,pins = "gpf1-3";
820 samsung,pin-function = <0xf>;
821 };
822};
823
824&pinctrl_cpif {
825 pinctrl-names = "default";
826 pinctrl-0 = <&initial_cpif>;
827
828 initial_cpif: initial-state {
829 PIN(IN, gpv6-0, DOWN, LV1);
830 PIN(IN, gpv6-1, DOWN, LV1);
831 };
832};
833
834&pinctrl_ese {
835 pinctrl-names = "default";
836 pinctrl-0 = <&initial_ese>;
837
838 initial_ese: initial-state {
839 PIN(IN, gpj2-0, DOWN, LV1);
840 PIN(IN, gpj2-1, DOWN, LV1);
841 PIN(IN, gpj2-2, DOWN, LV1);
842 };
843};
844
845&pinctrl_fsys {
846 pinctrl-names = "default";
847 pinctrl-0 = <&initial_fsys>;
848
849 initial_fsys: initial-state {
850 PIN(IN, gpr3-0, NONE, LV1);
851 PIN(IN, gpr3-1, DOWN, LV1);
852 PIN(IN, gpr3-2, DOWN, LV1);
853 PIN(IN, gpr3-3, DOWN, LV1);
854 PIN(IN, gpr3-7, NONE, LV1);
855 };
856};
857
858&pinctrl_imem {
859 pinctrl-names = "default";
860 pinctrl-0 = <&initial_imem>;
861
862 initial_imem: initial-state {
863 PIN(IN, gpf0-0, UP, LV1);
864 PIN(IN, gpf0-1, UP, LV1);
865 PIN(IN, gpf0-2, DOWN, LV1);
866 PIN(IN, gpf0-3, UP, LV1);
867 PIN(IN, gpf0-4, DOWN, LV1);
868 PIN(IN, gpf0-5, NONE, LV1);
869 PIN(IN, gpf0-6, DOWN, LV1);
870 PIN(IN, gpf0-7, UP, LV1);
871 };
872};
873
874&pinctrl_nfc {
875 pinctrl-names = "default";
876 pinctrl-0 = <&initial_nfc>;
877
878 initial_nfc: initial-state {
879 PIN(IN, gpj0-2, DOWN, LV1);
880 };
881};
882
883&pinctrl_peric {
884 pinctrl-names = "default";
885 pinctrl-0 = <&initial_peric>;
886
887 initial_peric: initial-state {
888 PIN(IN, gpv7-0, DOWN, LV1);
889 PIN(IN, gpv7-1, DOWN, LV1);
890 PIN(IN, gpv7-2, NONE, LV1);
891 PIN(IN, gpv7-3, DOWN, LV1);
892 PIN(IN, gpv7-4, DOWN, LV1);
893 PIN(IN, gpv7-5, DOWN, LV1);
894
895 PIN(IN, gpb0-4, DOWN, LV1);
896
897 PIN(IN, gpc0-2, DOWN, LV1);
898 PIN(IN, gpc0-5, DOWN, LV1);
899 PIN(IN, gpc0-7, DOWN, LV1);
900
901 PIN(IN, gpc1-1, DOWN, LV1);
902
903 PIN(IN, gpc3-4, NONE, LV1);
904 PIN(IN, gpc3-5, NONE, LV1);
905 PIN(IN, gpc3-6, NONE, LV1);
906 PIN(IN, gpc3-7, NONE, LV1);
907
908 PIN(OUT, gpg0-0, NONE, LV1);
909 PIN(FUNC1, gpg0-1, DOWN, LV1);
910
911 PIN(IN, gpd2-5, DOWN, LV1);
912
913 PIN(IN, gpd4-0, NONE, LV1);
914 PIN(IN, gpd4-1, DOWN, LV1);
915 PIN(IN, gpd4-2, DOWN, LV1);
916 PIN(IN, gpd4-3, DOWN, LV1);
917 PIN(IN, gpd4-4, DOWN, LV1);
918
919 PIN(IN, gpd6-3, DOWN, LV1);
920
921 PIN(IN, gpd8-1, UP, LV1);
922
923 PIN(IN, gpg1-0, DOWN, LV1);
924 PIN(IN, gpg1-1, DOWN, LV1);
925 PIN(IN, gpg1-2, DOWN, LV1);
926 PIN(IN, gpg1-3, DOWN, LV1);
927 PIN(IN, gpg1-4, DOWN, LV1);
928
929 PIN(IN, gpg2-0, DOWN, LV1);
930 PIN(IN, gpg2-1, DOWN, LV1);
931
932 PIN(IN, gpg3-0, DOWN, LV1);
933 PIN(IN, gpg3-1, DOWN, LV1);
934 PIN(IN, gpg3-5, DOWN, LV1);
935 PIN(IN, gpg3-7, DOWN, LV1);
936 };
937};
938
939&pinctrl_touch {
940 pinctrl-names = "default";
941 pinctrl-0 = <&initial_touch>;
942
943 initial_touch: initial-state {
944 PIN(IN, gpj1-2, DOWN, LV1);
945 };
946};
947
948&pwm {
949 pinctrl-0 = <&pwm0_out>;
950 pinctrl-names = "default";
951 status = "okay";
952};
953
954&mic {
955 status = "okay";
956
957 i80-if-timings {
958 };
959};
960
961&pmu_system_controller {
962 assigned-clocks = <&pmu_system_controller 0>;
963 assigned-clock-parents = <&xxti>;
964};
965
966&serial_1 {
967 status = "okay";
968};
969
970&spi_1 {
971 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
972 status = "okay";
973
974 wm5110: wm5110-codec@0 {
975 compatible = "wlf,wm5110";
976 reg = <0x0>;
977 spi-max-frequency = <20000000>;
978 interrupt-parent = <&gpa0>;
979 interrupts = <4 IRQ_TYPE_NONE>;
980 clocks = <&pmu_system_controller 0>,
981 <&s2mps13_osc S2MPS11_CLK_BT>;
982 clock-names = "mclk1", "mclk2";
983
984 gpio-controller;
985 #gpio-cells = <2>;
986
987 wlf,micd-detect-debounce = <300>;
988 wlf,micd-bias-start-time = <0x1>;
989 wlf,micd-rate = <0x7>;
990 wlf,micd-dbtime = <0x1>;
991 wlf,micd-force-micbias;
992 wlf,micd-configs = <0x0 1 0>;
993 wlf,hpdet-channel = <1>;
994 wlf,gpsw = <0x1>;
995 wlf,inmode = <2 0 2 0>;
996
997 wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
998 wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
999
1000 /* core supplies */
1001 AVDD-supply = <&ldo18_reg>;
1002 DBVDD1-supply = <&ldo18_reg>;
1003 CPVDD-supply = <&ldo18_reg>;
1004 DBVDD2-supply = <&ldo18_reg>;
1005 DBVDD3-supply = <&ldo18_reg>;
1006
1007 controller-data {
1008 samsung,spi-feedback-delay = <0>;
1009 };
1010 };
1011};
1012
1013&timer {
1014 clock-frequency = <24000000>;
1015};
1016
1017&tmu_atlas0 {
1018 vtmu-supply = <&ldo3_reg>;
1019 status = "okay";
1020};
1021
1022&tmu_apollo {
1023 vtmu-supply = <&ldo3_reg>;
1024 status = "okay";
1025};
1026
1027&tmu_g3d {
1028 vtmu-supply = <&ldo3_reg>;
1029 status = "okay";
1030};
1031
1032&usbdrd30 {
1033 vdd33-supply = <&ldo10_reg>;
1034 vdd10-supply = <&ldo6_reg>;
1035 status = "okay";
1036};
1037
1038&usbdrd_dwc3_0 {
1039 dr_mode = "otg";
1040};
1041
1042&usbdrd30_phy {
1043 vbus-supply = <&safeout1_reg>;
1044 status = "okay";
1045};
1046
1047&xxti {
1048 clock-frequency = <24000000>;
1049};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
new file mode 100644
index 000000000000..1db4e7f363a9
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
@@ -0,0 +1,41 @@
1/*
2 * SAMSUNG Exynos5433 TM2E board device tree source
3 *
4 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
5 *
6 * Device tree source file for Samsung's TM2E(TM2 EDGE) board which is based on
7 * Samsung Exynos5433 SoC.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include "exynos5433-tm2.dts"
15
16/ {
17 model = "Samsung TM2E board";
18 compatible = "samsung,tm2e", "samsung,exynos5433";
19};
20
21&ldo23_reg {
22 regulator-name = "CAM_SEN_CORE_1.025V_AP";
23 regulator-max-microvolt = <1050000>;
24};
25
26&ldo25_reg {
27 regulator-name = "UNUSED_LDO25";
28 regulator-always-off;
29};
30
31&ldo31_reg {
32 regulator-name = "TSP_VDD_1.8V_AP";
33 regulator-min-microvolt = <1800000>;
34 regulator-max-microvolt = <1800000>;
35};
36
37&ldo38_reg {
38 regulator-name = "VCC_3.3V_MOTOR_AP";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
41};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi
new file mode 100644
index 000000000000..9be2978f1b9a
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi
@@ -0,0 +1,23 @@
1/*
2 * Device tree sources for Exynos5433 TMU sensor configuration
3 *
4 * Copyright (c) 2016 Jonghwa Lee <jonghwa3.lee@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <dt-bindings/thermal/thermal_exynos.h>
12
13#thermal-sensor-cells = <0>;
14samsung,tmu_gain = <8>;
15samsung,tmu_reference_voltage = <23>;
16samsung,tmu_noise_cancel_mode = <4>;
17samsung,tmu_efuse_value = <75>;
18samsung,tmu_min_efuse_value = <40>;
19samsung,tmu_max_efuse_value = <150>;
20samsung,tmu_first_point_trim = <25>;
21samsung,tmu_second_point_trim = <85>;
22samsung,tmu_default_temp_offset = <50>;
23samsung,tmu_mux_addr = <6>;
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi
new file mode 100644
index 000000000000..125fe58d77ce
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi
@@ -0,0 +1,22 @@
1/*
2 * Device tree sources for Exynos5433 TMU sensor configuration
3 *
4 * Copyright (c) 2016 Chanwoo Choi <cw00.choi@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <dt-bindings/thermal/thermal_exynos.h>
12
13#thermal-sensor-cells = <0>;
14samsung,tmu_gain = <8>;
15samsung,tmu_reference_voltage = <16>;
16samsung,tmu_noise_cancel_mode = <4>;
17samsung,tmu_efuse_value = <75>;
18samsung,tmu_min_efuse_value = <40>;
19samsung,tmu_max_efuse_value = <150>;
20samsung,tmu_first_point_trim = <25>;
21samsung,tmu_second_point_trim = <85>;
22samsung,tmu_default_temp_offset = <50>;
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi
new file mode 100644
index 000000000000..ceaa05145b8a
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi
@@ -0,0 +1,296 @@
1/*
2 * Device tree sources for Exynos5433 thermal zone
3 *
4 * Copyright (c) 2016 Chanwoo Choi <cw00.choi@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <dt-bindings/thermal/thermal.h>
12
13/ {
14thermal-zones {
15 atlas0_thermal: atlas0-thermal {
16 thermal-sensors = <&tmu_atlas0>;
17 polling-delay-passive = <0>;
18 polling-delay = <0>;
19 trips {
20 atlas0_alert_0: atlas0-alert-0 {
21 temperature = <65000>; /* millicelsius */
22 hysteresis = <1000>; /* millicelsius */
23 type = "active";
24 };
25 atlas0_alert_1: atlas0-alert-1 {
26 temperature = <70000>; /* millicelsius */
27 hysteresis = <1000>; /* millicelsius */
28 type = "active";
29 };
30 atlas0_alert_2: atlas0-alert-2 {
31 temperature = <75000>; /* millicelsius */
32 hysteresis = <1000>; /* millicelsius */
33 type = "active";
34 };
35 atlas0_alert_3: atlas0-alert-3 {
36 temperature = <80000>; /* millicelsius */
37 hysteresis = <1000>; /* millicelsius */
38 type = "active";
39 };
40 atlas0_alert_4: atlas0-alert-4 {
41 temperature = <85000>; /* millicelsius */
42 hysteresis = <1000>; /* millicelsius */
43 type = "active";
44 };
45 atlas0_alert_5: atlas0-alert-5 {
46 temperature = <90000>; /* millicelsius */
47 hysteresis = <1000>; /* millicelsius */
48 type = "active";
49 };
50 atlas0_alert_6: atlas0-alert-6 {
51 temperature = <95000>; /* millicelsius */
52 hysteresis = <1000>; /* millicelsius */
53 type = "active";
54 };
55 };
56
57 cooling-maps {
58 map0 {
59 /* Set maximum frequency as 1800MHz */
60 trip = <&atlas0_alert_0>;
61 cooling-device = <&cpu4 1 2>;
62 };
63 map1 {
64 /* Set maximum frequency as 1700MHz */
65 trip = <&atlas0_alert_1>;
66 cooling-device = <&cpu4 2 3>;
67 };
68 map2 {
69 /* Set maximum frequency as 1600MHz */
70 trip = <&atlas0_alert_2>;
71 cooling-device = <&cpu4 3 4>;
72 };
73 map3 {
74 /* Set maximum frequency as 1500MHz */
75 trip = <&atlas0_alert_3>;
76 cooling-device = <&cpu4 4 5>;
77 };
78 map4 {
79 /* Set maximum frequency as 1400MHz */
80 trip = <&atlas0_alert_4>;
81 cooling-device = <&cpu4 5 7>;
82 };
83 map5 {
84 /* Set maximum frequencyas 1200MHz */
85 trip = <&atlas0_alert_5>;
86 cooling-device = <&cpu4 7 9>;
87 };
88 map6 {
89 /* Set maximum frequency as 1000MHz */
90 trip = <&atlas0_alert_6>;
91 cooling-device = <&cpu4 9 14>;
92 };
93 };
94 };
95
96 atlas1_thermal: atlas1-thermal {
97 thermal-sensors = <&tmu_atlas1>;
98 polling-delay-passive = <0>;
99 polling-delay = <0>;
100 trips {
101 atlas1_alert_0: atlas1-alert-0 {
102 temperature = <65000>; /* millicelsius */
103 hysteresis = <1000>; /* millicelsius */
104 type = "active";
105 };
106 atlas1_alert_1: atlas1-alert-1 {
107 temperature = <70000>; /* millicelsius */
108 hysteresis = <1000>; /* millicelsius */
109 type = "active";
110 };
111 atlas1_alert_2: atlas1-alert-2 {
112 temperature = <75000>; /* millicelsius */
113 hysteresis = <1000>; /* millicelsius */
114 type = "active";
115 };
116 atlas1_alert_3: atlas1-alert-3 {
117 temperature = <80000>; /* millicelsius */
118 hysteresis = <1000>; /* millicelsius */
119 type = "active";
120 };
121 atlas1_alert_4: atlas1-alert-4 {
122 temperature = <85000>; /* millicelsius */
123 hysteresis = <1000>; /* millicelsius */
124 type = "active";
125 };
126 atlas1_alert_5: atlas1-alert-5 {
127 temperature = <90000>; /* millicelsius */
128 hysteresis = <1000>; /* millicelsius */
129 type = "active";
130 };
131 atlas1_alert_6: atlas1-alert-6 {
132 temperature = <95000>; /* millicelsius */
133 hysteresis = <1000>; /* millicelsius */
134 type = "active";
135 };
136 };
137 };
138
139 g3d_thermal: g3d-thermal {
140 thermal-sensors = <&tmu_g3d>;
141 polling-delay-passive = <0>;
142 polling-delay = <0>;
143 trips {
144 g3d_alert_0: g3d-alert-0 {
145 temperature = <70000>; /* millicelsius */
146 hysteresis = <1000>; /* millicelsius */
147 type = "active";
148 };
149 g3d_alert_1: g3d-alert-1 {
150 temperature = <75000>; /* millicelsius */
151 hysteresis = <1000>; /* millicelsius */
152 type = "active";
153 };
154 g3d_alert_2: g3d-alert-2 {
155 temperature = <80000>; /* millicelsius */
156 hysteresis = <1000>; /* millicelsius */
157 type = "active";
158 };
159 g3d_alert_3: g3d-alert-3 {
160 temperature = <85000>; /* millicelsius */
161 hysteresis = <1000>; /* millicelsius */
162 type = "active";
163 };
164 g3d_alert_4: g3d-alert-4 {
165 temperature = <90000>; /* millicelsius */
166 hysteresis = <1000>; /* millicelsius */
167 type = "active";
168 };
169 g3d_alert_5: g3d-alert-5 {
170 temperature = <95000>; /* millicelsius */
171 hysteresis = <1000>; /* millicelsius */
172 type = "active";
173 };
174 g3d_alert_6: g3d-alert-6 {
175 temperature = <100000>; /* millicelsius */
176 hysteresis = <1000>; /* millicelsius */
177 type = "active";
178 };
179 };
180 };
181
182 apollo_thermal: apollo-thermal {
183 thermal-sensors = <&tmu_apollo>;
184 polling-delay-passive = <0>;
185 polling-delay = <0>;
186 trips {
187 apollo_alert_0: apollo-alert-0 {
188 temperature = <65000>; /* millicelsius */
189 hysteresis = <1000>; /* millicelsius */
190 type = "active";
191 };
192 apollo_alert_1: apollo-alert-1 {
193 temperature = <70000>; /* millicelsius */
194 hysteresis = <1000>; /* millicelsius */
195 type = "active";
196 };
197 apollo_alert_2: apollo-alert-2 {
198 temperature = <75000>; /* millicelsius */
199 hysteresis = <1000>; /* millicelsius */
200 type = "active";
201 };
202 apollo_alert_3: apollo-alert-3 {
203 temperature = <80000>; /* millicelsius */
204 hysteresis = <1000>; /* millicelsius */
205 type = "active";
206 };
207 apollo_alert_4: apollo-alert-4 {
208 temperature = <85000>; /* millicelsius */
209 hysteresis = <1000>; /* millicelsius */
210 type = "active";
211 };
212 apollo_alert_5: apollo-alert-5 {
213 temperature = <90000>; /* millicelsius */
214 hysteresis = <1000>; /* millicelsius */
215 type = "active";
216 };
217 apollo_alert_6: apollo-alert-6 {
218 temperature = <95000>; /* millicelsius */
219 hysteresis = <1000>; /* millicelsius */
220 type = "active";
221 };
222 };
223
224 cooling-maps {
225 map0 {
226 /* Set maximum frequency as 1200MHz */
227 trip = <&apollo_alert_2>;
228 cooling-device = <&cpu0 1 2>;
229 };
230 map1 {
231 /* Set maximum frequency as 1100MHz */
232 trip = <&apollo_alert_3>;
233 cooling-device = <&cpu0 2 3>;
234 };
235 map2 {
236 /* Set maximum frequency as 1000MHz */
237 trip = <&apollo_alert_4>;
238 cooling-device = <&cpu0 3 4>;
239 };
240 map3 {
241 /* Set maximum frequency as 900MHz */
242 trip = <&apollo_alert_5>;
243 cooling-device = <&cpu0 4 5>;
244 };
245 map4 {
246 /* Set maximum frequency as 800MHz */
247 trip = <&apollo_alert_6>;
248 cooling-device = <&cpu0 5 9>;
249 };
250 };
251 };
252
253 isp_thermal: isp-thermal {
254 thermal-sensors = <&tmu_isp>;
255 polling-delay-passive = <0>;
256 polling-delay = <0>;
257 trips {
258 isp_alert_0: isp-alert-0 {
259 temperature = <80000>; /* millicelsius */
260 hysteresis = <1000>; /* millicelsius */
261 type = "active";
262 };
263 isp_alert_1: isp-alert-1 {
264 temperature = <85000>; /* millicelsius */
265 hysteresis = <1000>; /* millicelsius */
266 type = "active";
267 };
268 isp_alert_2: isp-alert-2 {
269 temperature = <90000>; /* millicelsius */
270 hysteresis = <1000>; /* millicelsius */
271 type = "active";
272 };
273 isp_alert_3: isp-alert-3 {
274 temperature = <95000>; /* millicelsius */
275 hysteresis = <1000>; /* millicelsius */
276 type = "active";
277 };
278 isp_alert_4: isp-alert-4 {
279 temperature = <100000>; /* millicelsius */
280 hysteresis = <1000>; /* millicelsius */
281 type = "active";
282 };
283 isp_alert_5: isp-alert-5 {
284 temperature = <105000>; /* millicelsius */
285 hysteresis = <1000>; /* millicelsius */
286 type = "active";
287 };
288 isp_alert_6: isp-alert-6 {
289 temperature = <110000>; /* millicelsius */
290 hysteresis = <1000>; /* millicelsius */
291 type = "active";
292 };
293 };
294 };
295};
296};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
new file mode 100644
index 000000000000..64226d5ae471
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -0,0 +1,1462 @@
1/*
2 * Samsung's Exynos5433 SoC device tree source
3 *
4 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
5 *
6 * Samsung's Exynos5433 SoC device nodes are listed in this file.
7 * Exynos5433 based board files can include this file and provide
8 * values for board specific bindings.
9 *
10 * Note: This file does not include device nodes for all the controllers in
11 * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
12 * additional nodes can be added to this file.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <dt-bindings/clock/exynos5433.h>
20#include <dt-bindings/interrupt-controller/arm-gic.h>
21
22/ {
23 compatible = "samsung,exynos5433";
24 #address-cells = <2>;
25 #size-cells = <2>;
26
27 interrupt-parent = <&gic>;
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu0: cpu@100 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a53", "arm,armv8";
36 enable-method = "psci";
37 reg = <0x100>;
38 clock-frequency = <1300000000>;
39 clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
40 clock-names = "apolloclk";
41 operating-points-v2 = <&cluster_a53_opp_table>;
42 #cooling-cells = <2>;
43 };
44
45 cpu1: cpu@101 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a53", "arm,armv8";
48 enable-method = "psci";
49 reg = <0x101>;
50 clock-frequency = <1300000000>;
51 operating-points-v2 = <&cluster_a53_opp_table>;
52 #cooling-cells = <2>;
53 };
54
55 cpu2: cpu@102 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a53", "arm,armv8";
58 enable-method = "psci";
59 reg = <0x102>;
60 clock-frequency = <1300000000>;
61 operating-points-v2 = <&cluster_a53_opp_table>;
62 #cooling-cells = <2>;
63 };
64
65 cpu3: cpu@103 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a53", "arm,armv8";
68 enable-method = "psci";
69 reg = <0x103>;
70 clock-frequency = <1300000000>;
71 operating-points-v2 = <&cluster_a53_opp_table>;
72 #cooling-cells = <2>;
73 };
74
75 cpu4: cpu@0 {
76 device_type = "cpu";
77 compatible = "arm,cortex-a57", "arm,armv8";
78 enable-method = "psci";
79 reg = <0x0>;
80 clock-frequency = <1900000000>;
81 clocks = <&cmu_atlas CLK_SCLK_ATLAS>;
82 clock-names = "atlasclk";
83 operating-points-v2 = <&cluster_a57_opp_table>;
84 #cooling-cells = <2>;
85 };
86
87 cpu5: cpu@1 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a57", "arm,armv8";
90 enable-method = "psci";
91 reg = <0x1>;
92 clock-frequency = <1900000000>;
93 operating-points-v2 = <&cluster_a57_opp_table>;
94 #cooling-cells = <2>;
95 };
96
97 cpu6: cpu@2 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a57", "arm,armv8";
100 enable-method = "psci";
101 reg = <0x2>;
102 clock-frequency = <1900000000>;
103 operating-points-v2 = <&cluster_a57_opp_table>;
104 #cooling-cells = <2>;
105 };
106
107 cpu7: cpu@3 {
108 device_type = "cpu";
109 compatible = "arm,cortex-a57", "arm,armv8";
110 enable-method = "psci";
111 reg = <0x3>;
112 clock-frequency = <1900000000>;
113 operating-points-v2 = <&cluster_a57_opp_table>;
114 #cooling-cells = <2>;
115 };
116 };
117
118 cluster_a53_opp_table: opp_table0 {
119 compatible = "operating-points-v2";
120 opp-shared;
121
122 opp@400000000 {
123 opp-hz = /bits/ 64 <400000000>;
124 opp-microvolt = <900000>;
125 };
126 opp@500000000 {
127 opp-hz = /bits/ 64 <500000000>;
128 opp-microvolt = <925000>;
129 };
130 opp@600000000 {
131 opp-hz = /bits/ 64 <600000000>;
132 opp-microvolt = <950000>;
133 };
134 opp@700000000 {
135 opp-hz = /bits/ 64 <700000000>;
136 opp-microvolt = <975000>;
137 };
138 opp@800000000 {
139 opp-hz = /bits/ 64 <800000000>;
140 opp-microvolt = <1000000>;
141 };
142 opp@900000000 {
143 opp-hz = /bits/ 64 <900000000>;
144 opp-microvolt = <1050000>;
145 };
146 opp@1000000000 {
147 opp-hz = /bits/ 64 <1000000000>;
148 opp-microvolt = <1075000>;
149 };
150 opp@1100000000 {
151 opp-hz = /bits/ 64 <1100000000>;
152 opp-microvolt = <1112500>;
153 };
154 opp@1200000000 {
155 opp-hz = /bits/ 64 <1200000000>;
156 opp-microvolt = <1112500>;
157 };
158 opp@1300000000 {
159 opp-hz = /bits/ 64 <1300000000>;
160 opp-microvolt = <1150000>;
161 };
162 };
163
164 cluster_a57_opp_table: opp_table1 {
165 compatible = "operating-points-v2";
166 opp-shared;
167
168 opp@500000000 {
169 opp-hz = /bits/ 64 <500000000>;
170 opp-microvolt = <900000>;
171 };
172 opp@600000000 {
173 opp-hz = /bits/ 64 <600000000>;
174 opp-microvolt = <900000>;
175 };
176 opp@700000000 {
177 opp-hz = /bits/ 64 <700000000>;
178 opp-microvolt = <912500>;
179 };
180 opp@800000000 {
181 opp-hz = /bits/ 64 <800000000>;
182 opp-microvolt = <912500>;
183 };
184 opp@900000000 {
185 opp-hz = /bits/ 64 <900000000>;
186 opp-microvolt = <937500>;
187 };
188 opp@1000000000 {
189 opp-hz = /bits/ 64 <1000000000>;
190 opp-microvolt = <975000>;
191 };
192 opp@1100000000 {
193 opp-hz = /bits/ 64 <1100000000>;
194 opp-microvolt = <1012500>;
195 };
196 opp@1200000000 {
197 opp-hz = /bits/ 64 <1200000000>;
198 opp-microvolt = <1037500>;
199 };
200 opp@1300000000 {
201 opp-hz = /bits/ 64 <1300000000>;
202 opp-microvolt = <1062500>;
203 };
204 opp@1400000000 {
205 opp-hz = /bits/ 64 <1400000000>;
206 opp-microvolt = <1087500>;
207 };
208 opp@1500000000 {
209 opp-hz = /bits/ 64 <1500000000>;
210 opp-microvolt = <1125000>;
211 };
212 opp@1600000000 {
213 opp-hz = /bits/ 64 <1600000000>;
214 opp-microvolt = <1137500>;
215 };
216 opp@1700000000 {
217 opp-hz = /bits/ 64 <1700000000>;
218 opp-microvolt = <1175000>;
219 };
220 opp@1800000000 {
221 opp-hz = /bits/ 64 <1800000000>;
222 opp-microvolt = <1212500>;
223 };
224 opp@1900000000 {
225 opp-hz = /bits/ 64 <1900000000>;
226 opp-microvolt = <1262500>;
227 };
228 };
229
230 psci {
231 compatible = "arm,psci";
232 method = "smc";
233 cpu_off = <0x84000002>;
234 cpu_on = <0xC4000003>;
235 };
236
237 reboot: syscon-reboot {
238 compatible = "syscon-reboot";
239 regmap = <&pmu_system_controller>;
240 offset = <0x400>; /* SWRESET */
241 mask = <0x1>;
242 };
243
244 soc: soc {
245 compatible = "simple-bus";
246 #address-cells = <1>;
247 #size-cells = <1>;
248 ranges = <0x0 0x0 0x0 0x18000000>;
249
250 chipid@10000000 {
251 compatible = "samsung,exynos4210-chipid";
252 reg = <0x10000000 0x100>;
253 };
254
255 xxti: xxti {
256 compatible = "fixed-clock";
257 clock-output-names = "oscclk";
258 #clock-cells = <0>;
259 };
260
261 cmu_top: clock-controller@10030000 {
262 compatible = "samsung,exynos5433-cmu-top";
263 reg = <0x10030000 0x1000>;
264 #clock-cells = <1>;
265
266 clock-names = "oscclk",
267 "sclk_mphy_pll",
268 "sclk_mfc_pll",
269 "sclk_bus_pll";
270 clocks = <&xxti>,
271 <&cmu_cpif CLK_SCLK_MPHY_PLL>,
272 <&cmu_mif CLK_SCLK_MFC_PLL>,
273 <&cmu_mif CLK_SCLK_BUS_PLL>;
274 };
275
276 cmu_cpif: clock-controller@10fc0000 {
277 compatible = "samsung,exynos5433-cmu-cpif";
278 reg = <0x10fc0000 0x1000>;
279 #clock-cells = <1>;
280
281 clock-names = "oscclk";
282 clocks = <&xxti>;
283 };
284
285 cmu_mif: clock-controller@105b0000 {
286 compatible = "samsung,exynos5433-cmu-mif";
287 reg = <0x105b0000 0x2000>;
288 #clock-cells = <1>;
289
290 clock-names = "oscclk",
291 "sclk_mphy_pll";
292 clocks = <&xxti>,
293 <&cmu_cpif CLK_SCLK_MPHY_PLL>;
294 };
295
296 cmu_peric: clock-controller@14c80000 {
297 compatible = "samsung,exynos5433-cmu-peric";
298 reg = <0x14c80000 0x1000>;
299 #clock-cells = <1>;
300 };
301
302 cmu_peris: clock-controller@0x10040000 {
303 compatible = "samsung,exynos5433-cmu-peris";
304 reg = <0x10040000 0x1000>;
305 #clock-cells = <1>;
306 };
307
308 cmu_fsys: clock-controller@156e0000 {
309 compatible = "samsung,exynos5433-cmu-fsys";
310 reg = <0x156e0000 0x1000>;
311 #clock-cells = <1>;
312
313 clock-names = "oscclk",
314 "sclk_ufs_mphy",
315 "aclk_fsys_200",
316 "sclk_pcie_100_fsys",
317 "sclk_ufsunipro_fsys",
318 "sclk_mmc2_fsys",
319 "sclk_mmc1_fsys",
320 "sclk_mmc0_fsys",
321 "sclk_usbhost30_fsys",
322 "sclk_usbdrd30_fsys";
323 clocks = <&xxti>,
324 <&cmu_cpif CLK_SCLK_UFS_MPHY>,
325 <&cmu_top CLK_ACLK_FSYS_200>,
326 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
327 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
328 <&cmu_top CLK_SCLK_MMC2_FSYS>,
329 <&cmu_top CLK_SCLK_MMC1_FSYS>,
330 <&cmu_top CLK_SCLK_MMC0_FSYS>,
331 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
332 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
333 };
334
335 cmu_g2d: clock-controller@12460000 {
336 compatible = "samsung,exynos5433-cmu-g2d";
337 reg = <0x12460000 0x1000>;
338 #clock-cells = <1>;
339
340 clock-names = "oscclk",
341 "aclk_g2d_266",
342 "aclk_g2d_400";
343 clocks = <&xxti>,
344 <&cmu_top CLK_ACLK_G2D_266>,
345 <&cmu_top CLK_ACLK_G2D_400>;
346 };
347
348 cmu_disp: clock-controller@13b90000 {
349 compatible = "samsung,exynos5433-cmu-disp";
350 reg = <0x13b90000 0x1000>;
351 #clock-cells = <1>;
352
353 clock-names = "oscclk",
354 "sclk_dsim1_disp",
355 "sclk_dsim0_disp",
356 "sclk_dsd_disp",
357 "sclk_decon_tv_eclk_disp",
358 "sclk_decon_vclk_disp",
359 "sclk_decon_eclk_disp",
360 "sclk_decon_tv_vclk_disp",
361 "aclk_disp_333";
362 clocks = <&xxti>,
363 <&cmu_mif CLK_SCLK_DSIM1_DISP>,
364 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
365 <&cmu_mif CLK_SCLK_DSD_DISP>,
366 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
367 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
368 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
369 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
370 <&cmu_mif CLK_ACLK_DISP_333>;
371 };
372
373 cmu_aud: clock-controller@114c0000 {
374 compatible = "samsung,exynos5433-cmu-aud";
375 reg = <0x114c0000 0x1000>;
376 #clock-cells = <1>;
377 clock-names = "oscclk", "fout_aud_pll";
378 clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
379 };
380
381 cmu_bus0: clock-controller@13600000 {
382 compatible = "samsung,exynos5433-cmu-bus0";
383 reg = <0x13600000 0x1000>;
384 #clock-cells = <1>;
385
386 clock-names = "aclk_bus0_400";
387 clocks = <&cmu_top CLK_ACLK_BUS0_400>;
388 };
389
390 cmu_bus1: clock-controller@14800000 {
391 compatible = "samsung,exynos5433-cmu-bus1";
392 reg = <0x14800000 0x1000>;
393 #clock-cells = <1>;
394
395 clock-names = "aclk_bus1_400";
396 clocks = <&cmu_top CLK_ACLK_BUS1_400>;
397 };
398
399 cmu_bus2: clock-controller@13400000 {
400 compatible = "samsung,exynos5433-cmu-bus2";
401 reg = <0x13400000 0x1000>;
402 #clock-cells = <1>;
403
404 clock-names = "oscclk", "aclk_bus2_400";
405 clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
406 };
407
408 cmu_g3d: clock-controller@14aa0000 {
409 compatible = "samsung,exynos5433-cmu-g3d";
410 reg = <0x14aa0000 0x2000>;
411 #clock-cells = <1>;
412
413 clock-names = "oscclk", "aclk_g3d_400";
414 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
415 };
416
417 cmu_gscl: clock-controller@13cf0000 {
418 compatible = "samsung,exynos5433-cmu-gscl";
419 reg = <0x13cf0000 0x1000>;
420 #clock-cells = <1>;
421
422 clock-names = "oscclk",
423 "aclk_gscl_111",
424 "aclk_gscl_333";
425 clocks = <&xxti>,
426 <&cmu_top CLK_ACLK_GSCL_111>,
427 <&cmu_top CLK_ACLK_GSCL_333>;
428 };
429
430 cmu_apollo: clock-controller@11900000 {
431 compatible = "samsung,exynos5433-cmu-apollo";
432 reg = <0x11900000 0x2000>;
433 #clock-cells = <1>;
434
435 clock-names = "oscclk", "sclk_bus_pll_apollo";
436 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
437 };
438
439 cmu_atlas: clock-controller@11800000 {
440 compatible = "samsung,exynos5433-cmu-atlas";
441 reg = <0x11800000 0x2000>;
442 #clock-cells = <1>;
443
444 clock-names = "oscclk", "sclk_bus_pll_atlas";
445 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
446 };
447
448 cmu_mscl: clock-controller@105d0000 {
449 compatible = "samsung,exynos5433-cmu-mscl";
450 reg = <0x150d0000 0x1000>;
451 #clock-cells = <1>;
452
453 clock-names = "oscclk",
454 "sclk_jpeg_mscl",
455 "aclk_mscl_400";
456 clocks = <&xxti>,
457 <&cmu_top CLK_SCLK_JPEG_MSCL>,
458 <&cmu_top CLK_ACLK_MSCL_400>;
459 };
460
461 cmu_mfc: clock-controller@15280000 {
462 compatible = "samsung,exynos5433-cmu-mfc";
463 reg = <0x15280000 0x1000>;
464 #clock-cells = <1>;
465
466 clock-names = "oscclk", "aclk_mfc_400";
467 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
468 };
469
470 cmu_hevc: clock-controller@14f80000 {
471 compatible = "samsung,exynos5433-cmu-hevc";
472 reg = <0x14f80000 0x1000>;
473 #clock-cells = <1>;
474
475 clock-names = "oscclk", "aclk_hevc_400";
476 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
477 };
478
479 cmu_isp: clock-controller@146d0000 {
480 compatible = "samsung,exynos5433-cmu-isp";
481 reg = <0x146d0000 0x1000>;
482 #clock-cells = <1>;
483
484 clock-names = "oscclk",
485 "aclk_isp_dis_400",
486 "aclk_isp_400";
487 clocks = <&xxti>,
488 <&cmu_top CLK_ACLK_ISP_DIS_400>,
489 <&cmu_top CLK_ACLK_ISP_400>;
490 };
491
492 cmu_cam0: clock-controller@120d0000 {
493 compatible = "samsung,exynos5433-cmu-cam0";
494 reg = <0x120d0000 0x1000>;
495 #clock-cells = <1>;
496
497 clock-names = "oscclk",
498 "aclk_cam0_333",
499 "aclk_cam0_400",
500 "aclk_cam0_552";
501 clocks = <&xxti>,
502 <&cmu_top CLK_ACLK_CAM0_333>,
503 <&cmu_top CLK_ACLK_CAM0_400>,
504 <&cmu_top CLK_ACLK_CAM0_552>;
505 };
506
507 cmu_cam1: clock-controller@145d0000 {
508 compatible = "samsung,exynos5433-cmu-cam1";
509 reg = <0x145d0000 0x1000>;
510 #clock-cells = <1>;
511
512 clock-names = "oscclk",
513 "sclk_isp_uart_cam1",
514 "sclk_isp_spi1_cam1",
515 "sclk_isp_spi0_cam1",
516 "aclk_cam1_333",
517 "aclk_cam1_400",
518 "aclk_cam1_552";
519 clocks = <&xxti>,
520 <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
521 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
522 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
523 <&cmu_top CLK_ACLK_CAM1_333>,
524 <&cmu_top CLK_ACLK_CAM1_400>,
525 <&cmu_top CLK_ACLK_CAM1_552>;
526 };
527
528 tmu_atlas0: tmu@10060000 {
529 compatible = "samsung,exynos5433-tmu";
530 reg = <0x10060000 0x200>;
531 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
533 <&cmu_peris CLK_SCLK_TMU0>;
534 clock-names = "tmu_apbif", "tmu_sclk";
535 #include "exynos5433-tmu-sensor-conf.dtsi"
536 status = "disabled";
537 };
538
539 tmu_atlas1: tmu@10068000 {
540 compatible = "samsung,exynos5433-tmu";
541 reg = <0x10068000 0x200>;
542 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
544 <&cmu_peris CLK_SCLK_TMU0>;
545 clock-names = "tmu_apbif", "tmu_sclk";
546 #include "exynos5433-tmu-sensor-conf.dtsi"
547 status = "disabled";
548 };
549
550 tmu_g3d: tmu@10070000 {
551 compatible = "samsung,exynos5433-tmu";
552 reg = <0x10070000 0x200>;
553 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
555 <&cmu_peris CLK_SCLK_TMU1>;
556 clock-names = "tmu_apbif", "tmu_sclk";
557 #include "exynos5433-tmu-g3d-sensor-conf.dtsi"
558 status = "disabled";
559 };
560
561 tmu_apollo: tmu@10078000 {
562 compatible = "samsung,exynos5433-tmu";
563 reg = <0x10078000 0x200>;
564 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
566 <&cmu_peris CLK_SCLK_TMU1>;
567 clock-names = "tmu_apbif", "tmu_sclk";
568 #include "exynos5433-tmu-sensor-conf.dtsi"
569 status = "disabled";
570 };
571
572 tmu_isp: tmu@1007c000 {
573 compatible = "samsung,exynos5433-tmu";
574 reg = <0x1007c000 0x200>;
575 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
577 <&cmu_peris CLK_SCLK_TMU1>;
578 clock-names = "tmu_apbif", "tmu_sclk";
579 #include "exynos5433-tmu-sensor-conf.dtsi"
580 status = "disabled";
581 };
582
583 mct@101c0000 {
584 compatible = "samsung,exynos4210-mct";
585 reg = <0x101c0000 0x800>;
586 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>;
599 clock-names = "fin_pll", "mct";
600 };
601
602 pinctrl_alive: pinctrl@10580000 {
603 compatible = "samsung,exynos5433-pinctrl";
604 reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
605
606 wakeup-interrupt-controller {
607 compatible = "samsung,exynos7-wakeup-eint";
608 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
609 };
610 };
611
612 pinctrl_aud: pinctrl@114b0000 {
613 compatible = "samsung,exynos5433-pinctrl";
614 reg = <0x114b0000 0x1000>;
615 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
616 };
617
618 pinctrl_cpif: pinctrl@10fe0000 {
619 compatible = "samsung,exynos5433-pinctrl";
620 reg = <0x10fe0000 0x1000>;
621 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
622 };
623
624 pinctrl_ese: pinctrl@14ca0000 {
625 compatible = "samsung,exynos5433-pinctrl";
626 reg = <0x14ca0000 0x1000>;
627 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
628 };
629
630 pinctrl_finger: pinctrl@14cb0000 {
631 compatible = "samsung,exynos5433-pinctrl";
632 reg = <0x14cb0000 0x1000>;
633 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
634 };
635
636 pinctrl_fsys: pinctrl@15690000 {
637 compatible = "samsung,exynos5433-pinctrl";
638 reg = <0x15690000 0x1000>;
639 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
640 };
641
642 pinctrl_imem: pinctrl@11090000 {
643 compatible = "samsung,exynos5433-pinctrl";
644 reg = <0x11090000 0x1000>;
645 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
646 };
647
648 pinctrl_nfc: pinctrl@14cd0000 {
649 compatible = "samsung,exynos5433-pinctrl";
650 reg = <0x14cd0000 0x1000>;
651 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
652 };
653
654 pinctrl_peric: pinctrl@14cc0000 {
655 compatible = "samsung,exynos5433-pinctrl";
656 reg = <0x14cc0000 0x1100>;
657 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
658 };
659
660 pinctrl_touch: pinctrl@14ce0000 {
661 compatible = "samsung,exynos5433-pinctrl";
662 reg = <0x14ce0000 0x1100>;
663 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
664 };
665
666 pmu_system_controller: system-controller@105c0000 {
667 compatible = "samsung,exynos5433-pmu", "syscon";
668 reg = <0x105c0000 0x5008>;
669 #clock-cells = <1>;
670 clock-names = "clkout16";
671 clocks = <&xxti>;
672 };
673
674 gic: interrupt-controller@11001000 {
675 compatible = "arm,gic-400";
676 #interrupt-cells = <3>;
677 interrupt-controller;
678 reg = <0x11001000 0x1000>,
679 <0x11002000 0x2000>,
680 <0x11004000 0x2000>,
681 <0x11006000 0x2000>;
682 interrupts = <GIC_PPI 9 0xf04>;
683 };
684
685 mipi_phy: video-phy@105c0710 {
686 compatible = "samsung,exynos5433-mipi-video-phy";
687 #phy-cells = <1>;
688 samsung,pmu-syscon = <&pmu_system_controller>;
689 samsung,cam0-sysreg = <&syscon_cam0>;
690 samsung,cam1-sysreg = <&syscon_cam1>;
691 samsung,disp-sysreg = <&syscon_disp>;
692 };
693
694 decon: decon@13800000 {
695 compatible = "samsung,exynos5433-decon";
696 reg = <0x13800000 0x2104>;
697 clocks = <&cmu_disp CLK_PCLK_DECON>,
698 <&cmu_disp CLK_ACLK_DECON>,
699 <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
700 <&cmu_disp CLK_ACLK_XIU_DECON0X>,
701 <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
702 <&cmu_disp CLK_SCLK_DECON_VCLK>,
703 <&cmu_disp CLK_SCLK_DECON_ECLK>;
704 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
705 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
706 "sclk_decon_vclk", "sclk_decon_eclk";
707 interrupt-names = "fifo", "vsync", "lcd_sys";
708 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
710 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
711 samsung,disp-sysreg = <&syscon_disp>;
712 status = "disabled";
713 iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
714 iommu-names = "m0", "m1";
715
716 ports {
717 #address-cells = <1>;
718 #size-cells = <0>;
719
720 port@0 {
721 reg = <0>;
722 decon_to_mic: endpoint {
723 remote-endpoint =
724 <&mic_to_decon>;
725 };
726 };
727 };
728 };
729
730 dsi: dsi@13900000 {
731 compatible = "samsung,exynos5433-mipi-dsi";
732 reg = <0x13900000 0xC0>;
733 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
734 phys = <&mipi_phy 1>;
735 phy-names = "dsim";
736 clocks = <&cmu_disp CLK_PCLK_DSIM0>,
737 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
738 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
739 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
740 <&cmu_disp CLK_SCLK_DSIM0>;
741 clock-names = "bus_clk",
742 "phyclk_mipidphy0_bitclkdiv8",
743 "phyclk_mipidphy0_rxclkesc0",
744 "sclk_rgb_vclk_to_dsim0",
745 "sclk_mipi";
746 status = "disabled";
747 #address-cells = <1>;
748 #size-cells = <0>;
749
750 ports {
751 #address-cells = <1>;
752 #size-cells = <0>;
753
754 port@0 {
755 reg = <0>;
756 dsi_to_mic: endpoint {
757 remote-endpoint = <&mic_to_dsi>;
758 };
759 };
760 };
761 };
762
763 mic: mic@13930000 {
764 compatible = "samsung,exynos5433-mic";
765 reg = <0x13930000 0x48>;
766 clocks = <&cmu_disp CLK_PCLK_MIC0>,
767 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
768 clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
769 samsung,disp-syscon = <&syscon_disp>;
770 status = "disabled";
771
772 ports {
773 #address-cells = <1>;
774 #size-cells = <0>;
775
776 port@0 {
777 reg = <0>;
778 mic_to_decon: endpoint {
779 remote-endpoint =
780 <&decon_to_mic>;
781 };
782 };
783
784 port@1 {
785 reg = <1>;
786 mic_to_dsi: endpoint {
787 remote-endpoint = <&dsi_to_mic>;
788 };
789 };
790 };
791 };
792
793 syscon_disp: syscon@13b80000 {
794 compatible = "syscon";
795 reg = <0x13b80000 0x1010>;
796 };
797
798 syscon_cam0: syscon@120f0000 {
799 compatible = "syscon";
800 reg = <0x120f0000 0x1020>;
801 };
802
803 syscon_cam1: syscon@145f0000 {
804 compatible = "syscon";
805 reg = <0x145f0000 0x1038>;
806 };
807
808 gsc_0: video-scaler@13C00000 {
809 compatible = "samsung,exynos5433-gsc";
810 reg = <0x13c00000 0x1000>;
811 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
812 clock-names = "pclk", "aclk", "aclk_xiu",
813 "aclk_gsclbend";
814 clocks = <&cmu_gscl CLK_PCLK_GSCL0>,
815 <&cmu_gscl CLK_ACLK_GSCL0>,
816 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
817 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
818 iommus = <&sysmmu_gscl0>;
819 };
820
821 gsc_1: video-scaler@13C10000 {
822 compatible = "samsung,exynos5433-gsc";
823 reg = <0x13c10000 0x1000>;
824 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
825 clock-names = "pclk", "aclk", "aclk_xiu",
826 "aclk_gsclbend";
827 clocks = <&cmu_gscl CLK_PCLK_GSCL1>,
828 <&cmu_gscl CLK_ACLK_GSCL1>,
829 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
830 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
831 iommus = <&sysmmu_gscl1>;
832 };
833
834 gsc_2: video-scaler@13C20000 {
835 compatible = "samsung,exynos5433-gsc";
836 reg = <0x13c20000 0x1000>;
837 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
838 clock-names = "pclk", "aclk", "aclk_xiu",
839 "aclk_gsclbend";
840 clocks = <&cmu_gscl CLK_PCLK_GSCL2>,
841 <&cmu_gscl CLK_ACLK_GSCL2>,
842 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
843 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
844 iommus = <&sysmmu_gscl2>;
845 };
846
847 jpeg: codec@15020000 {
848 compatible = "samsung,exynos5433-jpeg";
849 reg = <0x15020000 0x10000>;
850 interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
851 clock-names = "pclk", "aclk", "aclk_xiu", "sclk";
852 clocks = <&cmu_mscl CLK_PCLK_JPEG>,
853 <&cmu_mscl CLK_ACLK_JPEG>,
854 <&cmu_mscl CLK_ACLK_XIU_MSCLX>,
855 <&cmu_mscl CLK_SCLK_JPEG>;
856 iommus = <&sysmmu_jpeg>;
857 };
858
859 mfc: codec@152E0000 {
860 compatible = "samsung,exynos5433-mfc";
861 reg = <0x152E0000 0x10000>;
862 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
863 clock-names = "pclk", "aclk", "aclk_xiu";
864 clocks = <&cmu_mfc CLK_PCLK_MFC>,
865 <&cmu_mfc CLK_ACLK_MFC>,
866 <&cmu_mfc CLK_ACLK_XIU_MFCX>;
867 iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>;
868 iommu-names = "left", "right";
869 };
870
871 sysmmu_decon0x: sysmmu@0x13a00000 {
872 compatible = "samsung,exynos-sysmmu";
873 reg = <0x13a00000 0x1000>;
874 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
875 clock-names = "pclk", "aclk";
876 clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
877 <&cmu_disp CLK_ACLK_SMMU_DECON0X>;
878 #iommu-cells = <0>;
879 };
880
881 sysmmu_decon1x: sysmmu@0x13a10000 {
882 compatible = "samsung,exynos-sysmmu";
883 reg = <0x13a10000 0x1000>;
884 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
885 clock-names = "pclk", "aclk";
886 clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
887 <&cmu_disp CLK_ACLK_SMMU_DECON1X>;
888 #iommu-cells = <0>;
889 };
890
891 sysmmu_gscl0: sysmmu@0x13C80000 {
892 compatible = "samsung,exynos-sysmmu";
893 reg = <0x13C80000 0x1000>;
894 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
895 clock-names = "aclk", "pclk";
896 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>,
897 <&cmu_gscl CLK_PCLK_SMMU_GSCL0>;
898 #iommu-cells = <0>;
899 };
900
901 sysmmu_gscl1: sysmmu@0x13C90000 {
902 compatible = "samsung,exynos-sysmmu";
903 reg = <0x13C90000 0x1000>;
904 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
905 clock-names = "aclk", "pclk";
906 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>,
907 <&cmu_gscl CLK_PCLK_SMMU_GSCL1>;
908 #iommu-cells = <0>;
909 };
910
911 sysmmu_gscl2: sysmmu@0x13CA0000 {
912 compatible = "samsung,exynos-sysmmu";
913 reg = <0x13CA0000 0x1000>;
914 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
915 clock-names = "aclk", "pclk";
916 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>,
917 <&cmu_gscl CLK_PCLK_SMMU_GSCL2>;
918 #iommu-cells = <0>;
919 };
920
921 sysmmu_jpeg: sysmmu@0x15060000 {
922 compatible = "samsung,exynos-sysmmu";
923 reg = <0x15060000 0x1000>;
924 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
925 clock-names = "pclk", "aclk";
926 clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>,
927 <&cmu_mscl CLK_ACLK_SMMU_JPEG>;
928 #iommu-cells = <0>;
929 };
930
931 sysmmu_mfc_0: sysmmu@0x15200000 {
932 compatible = "samsung,exynos-sysmmu";
933 reg = <0x15200000 0x1000>;
934 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
935 clock-names = "pclk", "aclk";
936 clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>,
937 <&cmu_mfc CLK_ACLK_SMMU_MFC_0>;
938 #iommu-cells = <0>;
939 };
940
941 sysmmu_mfc_1: sysmmu@0x15210000 {
942 compatible = "samsung,exynos-sysmmu";
943 reg = <0x15210000 0x1000>;
944 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
945 clock-names = "pclk", "aclk";
946 clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>,
947 <&cmu_mfc CLK_ACLK_SMMU_MFC_1>;
948 #iommu-cells = <0>;
949 };
950
951 serial_0: serial@14c10000 {
952 compatible = "samsung,exynos5433-uart";
953 reg = <0x14c10000 0x100>;
954 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
955 clocks = <&cmu_peric CLK_PCLK_UART0>,
956 <&cmu_peric CLK_SCLK_UART0>;
957 clock-names = "uart", "clk_uart_baud0";
958 pinctrl-names = "default";
959 pinctrl-0 = <&uart0_bus>;
960 status = "disabled";
961 };
962
963 serial_1: serial@14c20000 {
964 compatible = "samsung,exynos5433-uart";
965 reg = <0x14c20000 0x100>;
966 interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
967 clocks = <&cmu_peric CLK_PCLK_UART1>,
968 <&cmu_peric CLK_SCLK_UART1>;
969 clock-names = "uart", "clk_uart_baud0";
970 pinctrl-names = "default";
971 pinctrl-0 = <&uart1_bus>;
972 status = "disabled";
973 };
974
975 serial_2: serial@14c30000 {
976 compatible = "samsung,exynos5433-uart";
977 reg = <0x14c30000 0x100>;
978 interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
979 clocks = <&cmu_peric CLK_PCLK_UART2>,
980 <&cmu_peric CLK_SCLK_UART2>;
981 clock-names = "uart", "clk_uart_baud0";
982 pinctrl-names = "default";
983 pinctrl-0 = <&uart2_bus>;
984 status = "disabled";
985 };
986
987 spi_0: spi@14d20000 {
988 compatible = "samsung,exynos5433-spi";
989 reg = <0x14d20000 0x100>;
990 interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>;
991 dmas = <&pdma0 9>, <&pdma0 8>;
992 dma-names = "tx", "rx";
993 #address-cells = <1>;
994 #size-cells = <0>;
995 clocks = <&cmu_peric CLK_PCLK_SPI0>,
996 <&cmu_peric CLK_SCLK_SPI0>,
997 <&cmu_peric CLK_SCLK_IOCLK_SPI0>;
998 clock-names = "spi", "spi_busclk0", "spi_ioclk";
999 samsung,spi-src-clk = <0>;
1000 pinctrl-names = "default";
1001 pinctrl-0 = <&spi0_bus>;
1002 num-cs = <1>;
1003 status = "disabled";
1004 };
1005
1006 spi_1: spi@14d30000 {
1007 compatible = "samsung,exynos5433-spi";
1008 reg = <0x14d30000 0x100>;
1009 interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
1010 dmas = <&pdma0 11>, <&pdma0 10>;
1011 dma-names = "tx", "rx";
1012 #address-cells = <1>;
1013 #size-cells = <0>;
1014 clocks = <&cmu_peric CLK_PCLK_SPI1>,
1015 <&cmu_peric CLK_SCLK_SPI1>,
1016 <&cmu_peric CLK_SCLK_IOCLK_SPI1>;
1017 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1018 samsung,spi-src-clk = <0>;
1019 pinctrl-names = "default";
1020 pinctrl-0 = <&spi1_bus>;
1021 num-cs = <1>;
1022 status = "disabled";
1023 };
1024
1025 spi_2: spi@14d40000 {
1026 compatible = "samsung,exynos5433-spi";
1027 reg = <0x14d40000 0x100>;
1028 interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>;
1029 dmas = <&pdma0 13>, <&pdma0 12>;
1030 dma-names = "tx", "rx";
1031 #address-cells = <1>;
1032 #size-cells = <0>;
1033 clocks = <&cmu_peric CLK_PCLK_SPI2>,
1034 <&cmu_peric CLK_SCLK_SPI2>,
1035 <&cmu_peric CLK_SCLK_IOCLK_SPI2>;
1036 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1037 samsung,spi-src-clk = <0>;
1038 pinctrl-names = "default";
1039 pinctrl-0 = <&spi2_bus>;
1040 num-cs = <1>;
1041 status = "disabled";
1042 };
1043
1044 spi_3: spi@14d50000 {
1045 compatible = "samsung,exynos5433-spi";
1046 reg = <0x14d50000 0x100>;
1047 interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
1048 dmas = <&pdma0 23>, <&pdma0 22>;
1049 dma-names = "tx", "rx";
1050 #address-cells = <1>;
1051 #size-cells = <0>;
1052 clocks = <&cmu_peric CLK_PCLK_SPI3>,
1053 <&cmu_peric CLK_SCLK_SPI3>,
1054 <&cmu_peric CLK_SCLK_IOCLK_SPI3>;
1055 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1056 samsung,spi-src-clk = <0>;
1057 pinctrl-names = "default";
1058 pinctrl-0 = <&spi3_bus>;
1059 num-cs = <1>;
1060 status = "disabled";
1061 };
1062
1063 spi_4: spi@14d00000 {
1064 compatible = "samsung,exynos5433-spi";
1065 reg = <0x14d00000 0x100>;
1066 interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
1067 dmas = <&pdma0 25>, <&pdma0 24>;
1068 dma-names = "tx", "rx";
1069 #address-cells = <1>;
1070 #size-cells = <0>;
1071 clocks = <&cmu_peric CLK_PCLK_SPI4>,
1072 <&cmu_peric CLK_SCLK_SPI4>,
1073 <&cmu_peric CLK_SCLK_IOCLK_SPI4>;
1074 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1075 samsung,spi-src-clk = <0>;
1076 pinctrl-names = "default";
1077 pinctrl-0 = <&spi4_bus>;
1078 num-cs = <1>;
1079 status = "disabled";
1080 };
1081
1082 adc: adc@14d10000 {
1083 compatible = "samsung,exynos7-adc";
1084 reg = <0x14d10000 0x100>;
1085 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
1086 clock-names = "adc";
1087 clocks = <&cmu_peric CLK_PCLK_ADCIF>;
1088 #io-channel-cells = <1>;
1089 io-channel-ranges;
1090 status = "disabled";
1091 };
1092
1093 pwm: pwm@14dd0000 {
1094 compatible = "samsung,exynos4210-pwm";
1095 reg = <0x14dd0000 0x100>;
1096 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1097 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1098 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1099 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1100 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
1101 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
1102 clocks = <&cmu_peric CLK_PCLK_PWM>;
1103 clock-names = "timers";
1104 #pwm-cells = <3>;
1105 status = "disabled";
1106 };
1107
1108 hsi2c_0: hsi2c@14e40000 {
1109 compatible = "samsung,exynos7-hsi2c";
1110 reg = <0x14e40000 0x1000>;
1111 interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>;
1112 #address-cells = <1>;
1113 #size-cells = <0>;
1114 pinctrl-names = "default";
1115 pinctrl-0 = <&hs_i2c0_bus>;
1116 clocks = <&cmu_peric CLK_PCLK_HSI2C0>;
1117 clock-names = "hsi2c";
1118 status = "disabled";
1119 };
1120
1121 hsi2c_1: hsi2c@14e50000 {
1122 compatible = "samsung,exynos7-hsi2c";
1123 reg = <0x14e50000 0x1000>;
1124 interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
1125 #address-cells = <1>;
1126 #size-cells = <0>;
1127 pinctrl-names = "default";
1128 pinctrl-0 = <&hs_i2c1_bus>;
1129 clocks = <&cmu_peric CLK_PCLK_HSI2C1>;
1130 clock-names = "hsi2c";
1131 status = "disabled";
1132 };
1133
1134 hsi2c_2: hsi2c@14e60000 {
1135 compatible = "samsung,exynos7-hsi2c";
1136 reg = <0x14e60000 0x1000>;
1137 interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
1138 #address-cells = <1>;
1139 #size-cells = <0>;
1140 pinctrl-names = "default";
1141 pinctrl-0 = <&hs_i2c2_bus>;
1142 clocks = <&cmu_peric CLK_PCLK_HSI2C2>;
1143 clock-names = "hsi2c";
1144 status = "disabled";
1145 };
1146
1147 hsi2c_3: hsi2c@14e70000 {
1148 compatible = "samsung,exynos7-hsi2c";
1149 reg = <0x14e70000 0x1000>;
1150 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
1151 #address-cells = <1>;
1152 #size-cells = <0>;
1153 pinctrl-names = "default";
1154 pinctrl-0 = <&hs_i2c3_bus>;
1155 clocks = <&cmu_peric CLK_PCLK_HSI2C3>;
1156 clock-names = "hsi2c";
1157 status = "disabled";
1158 };
1159
1160 hsi2c_4: hsi2c@14ec0000 {
1161 compatible = "samsung,exynos7-hsi2c";
1162 reg = <0x14ec0000 0x1000>;
1163 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
1164 #address-cells = <1>;
1165 #size-cells = <0>;
1166 pinctrl-names = "default";
1167 pinctrl-0 = <&hs_i2c4_bus>;
1168 clocks = <&cmu_peric CLK_PCLK_HSI2C4>;
1169 clock-names = "hsi2c";
1170 status = "disabled";
1171 };
1172
1173 hsi2c_5: hsi2c@14ed0000 {
1174 compatible = "samsung,exynos7-hsi2c";
1175 reg = <0x14ed0000 0x1000>;
1176 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
1177 #address-cells = <1>;
1178 #size-cells = <0>;
1179 pinctrl-names = "default";
1180 pinctrl-0 = <&hs_i2c5_bus>;
1181 clocks = <&cmu_peric CLK_PCLK_HSI2C5>;
1182 clock-names = "hsi2c";
1183 status = "disabled";
1184 };
1185
1186 hsi2c_6: hsi2c@14ee0000 {
1187 compatible = "samsung,exynos7-hsi2c";
1188 reg = <0x14ee0000 0x1000>;
1189 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>;
1190 #address-cells = <1>;
1191 #size-cells = <0>;
1192 pinctrl-names = "default";
1193 pinctrl-0 = <&hs_i2c6_bus>;
1194 clocks = <&cmu_peric CLK_PCLK_HSI2C6>;
1195 clock-names = "hsi2c";
1196 status = "disabled";
1197 };
1198
1199 hsi2c_7: hsi2c@14ef0000 {
1200 compatible = "samsung,exynos7-hsi2c";
1201 reg = <0x14ef0000 0x1000>;
1202 interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>;
1203 #address-cells = <1>;
1204 #size-cells = <0>;
1205 pinctrl-names = "default";
1206 pinctrl-0 = <&hs_i2c7_bus>;
1207 clocks = <&cmu_peric CLK_PCLK_HSI2C7>;
1208 clock-names = "hsi2c";
1209 status = "disabled";
1210 };
1211
1212 hsi2c_8: hsi2c@14d90000 {
1213 compatible = "samsung,exynos7-hsi2c";
1214 reg = <0x14d90000 0x1000>;
1215 interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
1216 #address-cells = <1>;
1217 #size-cells = <0>;
1218 pinctrl-names = "default";
1219 pinctrl-0 = <&hs_i2c8_bus>;
1220 clocks = <&cmu_peric CLK_PCLK_HSI2C8>;
1221 clock-names = "hsi2c";
1222 status = "disabled";
1223 };
1224
1225 hsi2c_9: hsi2c@14da0000 {
1226 compatible = "samsung,exynos7-hsi2c";
1227 reg = <0x14da0000 0x1000>;
1228 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1229 #address-cells = <1>;
1230 #size-cells = <0>;
1231 pinctrl-names = "default";
1232 pinctrl-0 = <&hs_i2c9_bus>;
1233 clocks = <&cmu_peric CLK_PCLK_HSI2C9>;
1234 clock-names = "hsi2c";
1235 status = "disabled";
1236 };
1237
1238 hsi2c_10: hsi2c@14de0000 {
1239 compatible = "samsung,exynos7-hsi2c";
1240 reg = <0x14de0000 0x1000>;
1241 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
1242 #address-cells = <1>;
1243 #size-cells = <0>;
1244 pinctrl-names = "default";
1245 pinctrl-0 = <&hs_i2c10_bus>;
1246 clocks = <&cmu_peric CLK_PCLK_HSI2C10>;
1247 clock-names = "hsi2c";
1248 status = "disabled";
1249 };
1250
1251 hsi2c_11: hsi2c@14df0000 {
1252 compatible = "samsung,exynos7-hsi2c";
1253 reg = <0x14df0000 0x1000>;
1254 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
1255 #address-cells = <1>;
1256 #size-cells = <0>;
1257 pinctrl-names = "default";
1258 pinctrl-0 = <&hs_i2c11_bus>;
1259 clocks = <&cmu_peric CLK_PCLK_HSI2C11>;
1260 clock-names = "hsi2c";
1261 status = "disabled";
1262 };
1263
1264 usbdrd30: usb@15400000 {
1265 compatible = "samsung,exynos5250-dwusb3";
1266 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
1267 <&cmu_fsys CLK_SCLK_USBDRD30>;
1268 clock-names = "usbdrd30", "usbdrd30_susp_clk";
1269 #address-cells = <1>;
1270 #size-cells = <1>;
1271 ranges;
1272 status = "disabled";
1273
1274 dwc3@15400000 {
1275 compatible = "snps,dwc3";
1276 reg = <0x15400000 0x10000>;
1277 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1278 phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
1279 phy-names = "usb2-phy", "usb3-phy";
1280 };
1281 };
1282
1283 usbdrd30_phy: phy@15500000 {
1284 compatible = "samsung,exynos5433-usbdrd-phy";
1285 reg = <0x15500000 0x100>;
1286 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
1287 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1288 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>,
1289 <&cmu_fsys CLK_SCLK_USBDRD30>;
1290 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1291 "itp";
1292 #phy-cells = <1>;
1293 samsung,pmu-syscon = <&pmu_system_controller>;
1294 status = "disabled";
1295 };
1296
1297 usbhost30_phy: phy@15580000 {
1298 compatible = "samsung,exynos5433-usbdrd-phy";
1299 reg = <0x15580000 0x100>;
1300 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>,
1301 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1302 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>,
1303 <&cmu_fsys CLK_SCLK_USBHOST30>;
1304 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1305 "itp";
1306 #phy-cells = <1>;
1307 samsung,pmu-syscon = <&pmu_system_controller>;
1308 status = "disabled";
1309 };
1310
1311 usbhost30: usb@15a00000 {
1312 compatible = "samsung,exynos5250-dwusb3";
1313 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
1314 <&cmu_fsys CLK_SCLK_USBHOST30>;
1315 clock-names = "usbdrd30", "usbdrd30_susp_clk";
1316 #address-cells = <1>;
1317 #size-cells = <1>;
1318 ranges;
1319 status = "disabled";
1320
1321 usbdrd_dwc3_0: dwc3@15a00000 {
1322 compatible = "snps,dwc3";
1323 reg = <0x15a00000 0x10000>;
1324 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1325 phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
1326 phy-names = "usb2-phy", "usb3-phy";
1327 };
1328 };
1329
1330 mshc_0: mshc@15540000 {
1331 compatible = "samsung,exynos7-dw-mshc-smu";
1332 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1333 #address-cells = <1>;
1334 #size-cells = <0>;
1335 reg = <0x15540000 0x2000>;
1336 clocks = <&cmu_fsys CLK_ACLK_MMC0>,
1337 <&cmu_fsys CLK_SCLK_MMC0>;
1338 clock-names = "biu", "ciu";
1339 fifo-depth = <0x40>;
1340 status = "disabled";
1341 };
1342
1343 mshc_1: mshc@15550000 {
1344 compatible = "samsung,exynos7-dw-mshc-smu";
1345 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1346 #address-cells = <1>;
1347 #size-cells = <0>;
1348 reg = <0x15550000 0x2000>;
1349 clocks = <&cmu_fsys CLK_ACLK_MMC1>,
1350 <&cmu_fsys CLK_SCLK_MMC1>;
1351 clock-names = "biu", "ciu";
1352 fifo-depth = <0x40>;
1353 status = "disabled";
1354 };
1355
1356 mshc_2: mshc@15560000 {
1357 compatible = "samsung,exynos7-dw-mshc-smu";
1358 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1359 #address-cells = <1>;
1360 #size-cells = <0>;
1361 reg = <0x15560000 0x2000>;
1362 clocks = <&cmu_fsys CLK_ACLK_MMC2>,
1363 <&cmu_fsys CLK_SCLK_MMC2>;
1364 clock-names = "biu", "ciu";
1365 fifo-depth = <0x40>;
1366 status = "disabled";
1367 };
1368
1369 amba {
1370 compatible = "arm,amba-bus";
1371 #address-cells = <1>;
1372 #size-cells = <1>;
1373 ranges;
1374
1375 pdma0: pdma@15610000 {
1376 compatible = "arm,pl330", "arm,primecell";
1377 reg = <0x15610000 0x1000>;
1378 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1379 clocks = <&cmu_fsys CLK_PDMA0>;
1380 clock-names = "apb_pclk";
1381 #dma-cells = <1>;
1382 #dma-channels = <8>;
1383 #dma-requests = <32>;
1384 };
1385
1386 pdma1: pdma@15600000 {
1387 compatible = "arm,pl330", "arm,primecell";
1388 reg = <0x15600000 0x1000>;
1389 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1390 clocks = <&cmu_fsys CLK_PDMA1>;
1391 clock-names = "apb_pclk";
1392 #dma-cells = <1>;
1393 #dma-channels = <8>;
1394 #dma-requests = <32>;
1395 };
1396 };
1397
1398 audio-subsystem@11400000 {
1399 compatible = "samsung,exynos5433-lpass";
1400 reg = <0x11400000 0x100>, <0x11500000 0x08>;
1401 samsung,pmu-syscon = <&pmu_system_controller>;
1402 #address-cells = <1>;
1403 #size-cells = <1>;
1404 ranges;
1405
1406 adma: adma@11420000 {
1407 compatible = "arm,pl330", "arm,primecell";
1408 reg = <0x11420000 0x1000>;
1409 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1410 clocks = <&cmu_aud CLK_ACLK_DMAC>;
1411 clock-names = "apb_pclk";
1412 #dma-cells = <1>;
1413 #dma-channels = <8>;
1414 #dma-requests = <32>;
1415 };
1416
1417 i2s0: i2s0@11440000 {
1418 compatible = "samsung,exynos7-i2s";
1419 reg = <0x11440000 0x100>;
1420 dmas = <&adma 0 &adma 2>;
1421 dma-names = "tx", "rx";
1422 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1423 #address-cells = <1>;
1424 #size-cells = <0>;
1425 clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
1426 <&cmu_aud CLK_SCLK_AUD_I2S>,
1427 <&cmu_aud CLK_SCLK_I2S_BCLK>;
1428 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1429 pinctrl-names = "default";
1430 pinctrl-0 = <&i2s0_bus>;
1431 status = "disabled";
1432 };
1433
1434 serial_3: serial@11460000 {
1435 compatible = "samsung,exynos5433-uart";
1436 reg = <0x11460000 0x100>;
1437 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1438 clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
1439 <&cmu_aud CLK_SCLK_AUD_UART>;
1440 clock-names = "uart", "clk_uart_baud0";
1441 pinctrl-names = "default";
1442 pinctrl-0 = <&uart_aud_bus>;
1443 status = "disabled";
1444 };
1445 };
1446 };
1447
1448 timer: timer {
1449 compatible = "arm,armv8-timer";
1450 interrupts = <GIC_PPI 13
1451 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1452 <GIC_PPI 14
1453 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1454 <GIC_PPI 11
1455 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1456 <GIC_PPI 10
1457 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1458 };
1459};
1460
1461#include "exynos5433-pinctrl.dtsi"
1462#include "exynos5433-tmu.dtsi"
diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
index f77ddaf21d04..82321984e1fb 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -20,8 +20,14 @@
20 interrupt-controller; 20 interrupt-controller;
21 interrupt-parent = <&gic>; 21 interrupt-parent = <&gic>;
22 #interrupt-cells = <2>; 22 #interrupt-cells = <2>;
23 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, 23 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
24 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>; 24 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
25 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
26 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
27 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
28 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
29 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
30 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
25 }; 31 };
26 32
27 gpa1: gpa1 { 33 gpa1: gpa1 {
@@ -31,8 +37,14 @@
31 interrupt-controller; 37 interrupt-controller;
32 interrupt-parent = <&gic>; 38 interrupt-parent = <&gic>;
33 #interrupt-cells = <2>; 39 #interrupt-cells = <2>;
34 interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, 40 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
35 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; 41 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
42 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
43 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
44 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
36 }; 48 };
37 49
38 gpa2: gpa2 { 50 gpa2: gpa2 {
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 6328a66ed97e..80aa60e38237 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -35,28 +35,28 @@
35 #address-cells = <1>; 35 #address-cells = <1>;
36 #size-cells = <0>; 36 #size-cells = <0>;
37 37
38 cpu@0 { 38 cpu_atlas0: cpu@0 {
39 device_type = "cpu"; 39 device_type = "cpu";
40 compatible = "arm,cortex-a57", "arm,armv8"; 40 compatible = "arm,cortex-a57", "arm,armv8";
41 reg = <0x0>; 41 reg = <0x0>;
42 enable-method = "psci"; 42 enable-method = "psci";
43 }; 43 };
44 44
45 cpu@1 { 45 cpu_atlas1: cpu@1 {
46 device_type = "cpu"; 46 device_type = "cpu";
47 compatible = "arm,cortex-a57", "arm,armv8"; 47 compatible = "arm,cortex-a57", "arm,armv8";
48 reg = <0x1>; 48 reg = <0x1>;
49 enable-method = "psci"; 49 enable-method = "psci";
50 }; 50 };
51 51
52 cpu@2 { 52 cpu_atlas2: cpu@2 {
53 device_type = "cpu"; 53 device_type = "cpu";
54 compatible = "arm,cortex-a57", "arm,armv8"; 54 compatible = "arm,cortex-a57", "arm,armv8";
55 reg = <0x2>; 55 reg = <0x2>;
56 enable-method = "psci"; 56 enable-method = "psci";
57 }; 57 };
58 58
59 cpu@3 { 59 cpu_atlas3: cpu@3 {
60 device_type = "cpu"; 60 device_type = "cpu";
61 compatible = "arm,cortex-a57", "arm,armv8"; 61 compatible = "arm,cortex-a57", "arm,armv8";
62 reg = <0x3>; 62 reg = <0x3>;
@@ -106,7 +106,7 @@
106 pdma0: pdma@10E10000 { 106 pdma0: pdma@10E10000 {
107 compatible = "arm,pl330", "arm,primecell"; 107 compatible = "arm,pl330", "arm,primecell";
108 reg = <0x10E10000 0x1000>; 108 reg = <0x10E10000 0x1000>;
109 interrupts = <0 225 0>; 109 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&clock_fsys0 ACLK_PDMA0>; 110 clocks = <&clock_fsys0 ACLK_PDMA0>;
111 clock-names = "apb_pclk"; 111 clock-names = "apb_pclk";
112 #dma-cells = <1>; 112 #dma-cells = <1>;
@@ -117,7 +117,7 @@
117 pdma1: pdma@10EB0000 { 117 pdma1: pdma@10EB0000 {
118 compatible = "arm,pl330", "arm,primecell"; 118 compatible = "arm,pl330", "arm,primecell";
119 reg = <0x10EB0000 0x1000>; 119 reg = <0x10EB0000 0x1000>;
120 interrupts = <0 226 0>; 120 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
121 clocks = <&clock_fsys0 ACLK_PDMA1>; 121 clocks = <&clock_fsys0 ACLK_PDMA1>;
122 clock-names = "apb_pclk"; 122 clock-names = "apb_pclk";
123 #dma-cells = <1>; 123 #dma-cells = <1>;
@@ -220,7 +220,7 @@
220 serial_0: serial@13630000 { 220 serial_0: serial@13630000 {
221 compatible = "samsung,exynos4210-uart"; 221 compatible = "samsung,exynos4210-uart";
222 reg = <0x13630000 0x100>; 222 reg = <0x13630000 0x100>;
223 interrupts = <0 440 0>; 223 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&clock_peric0 PCLK_UART0>, 224 clocks = <&clock_peric0 PCLK_UART0>,
225 <&clock_peric0 SCLK_UART0>; 225 <&clock_peric0 SCLK_UART0>;
226 clock-names = "uart", "clk_uart_baud0"; 226 clock-names = "uart", "clk_uart_baud0";
@@ -230,7 +230,7 @@
230 serial_1: serial@14c20000 { 230 serial_1: serial@14c20000 {
231 compatible = "samsung,exynos4210-uart"; 231 compatible = "samsung,exynos4210-uart";
232 reg = <0x14c20000 0x100>; 232 reg = <0x14c20000 0x100>;
233 interrupts = <0 456 0>; 233 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&clock_peric1 PCLK_UART1>, 234 clocks = <&clock_peric1 PCLK_UART1>,
235 <&clock_peric1 SCLK_UART1>; 235 <&clock_peric1 SCLK_UART1>;
236 clock-names = "uart", "clk_uart_baud0"; 236 clock-names = "uart", "clk_uart_baud0";
@@ -240,7 +240,7 @@
240 serial_2: serial@14c30000 { 240 serial_2: serial@14c30000 {
241 compatible = "samsung,exynos4210-uart"; 241 compatible = "samsung,exynos4210-uart";
242 reg = <0x14c30000 0x100>; 242 reg = <0x14c30000 0x100>;
243 interrupts = <0 457 0>; 243 interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&clock_peric1 PCLK_UART2>, 244 clocks = <&clock_peric1 PCLK_UART2>,
245 <&clock_peric1 SCLK_UART2>; 245 <&clock_peric1 SCLK_UART2>;
246 clock-names = "uart", "clk_uart_baud0"; 246 clock-names = "uart", "clk_uart_baud0";
@@ -250,7 +250,7 @@
250 serial_3: serial@14c40000 { 250 serial_3: serial@14c40000 {
251 compatible = "samsung,exynos4210-uart"; 251 compatible = "samsung,exynos4210-uart";
252 reg = <0x14c40000 0x100>; 252 reg = <0x14c40000 0x100>;
253 interrupts = <0 458 0>; 253 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&clock_peric1 PCLK_UART3>, 254 clocks = <&clock_peric1 PCLK_UART3>,
255 <&clock_peric1 SCLK_UART3>; 255 <&clock_peric1 SCLK_UART3>;
256 clock-names = "uart", "clk_uart_baud0"; 256 clock-names = "uart", "clk_uart_baud0";
@@ -264,62 +264,62 @@
264 wakeup-interrupt-controller { 264 wakeup-interrupt-controller {
265 compatible = "samsung,exynos7-wakeup-eint"; 265 compatible = "samsung,exynos7-wakeup-eint";
266 interrupt-parent = <&gic>; 266 interrupt-parent = <&gic>;
267 interrupts = <0 16 0>; 267 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
268 }; 268 };
269 }; 269 };
270 270
271 pinctrl_bus0: pinctrl@13470000 { 271 pinctrl_bus0: pinctrl@13470000 {
272 compatible = "samsung,exynos7-pinctrl"; 272 compatible = "samsung,exynos7-pinctrl";
273 reg = <0x13470000 0x1000>; 273 reg = <0x13470000 0x1000>;
274 interrupts = <0 383 0>; 274 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
275 }; 275 };
276 276
277 pinctrl_nfc: pinctrl@14cd0000 { 277 pinctrl_nfc: pinctrl@14cd0000 {
278 compatible = "samsung,exynos7-pinctrl"; 278 compatible = "samsung,exynos7-pinctrl";
279 reg = <0x14cd0000 0x1000>; 279 reg = <0x14cd0000 0x1000>;
280 interrupts = <0 473 0>; 280 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
281 }; 281 };
282 282
283 pinctrl_touch: pinctrl@14ce0000 { 283 pinctrl_touch: pinctrl@14ce0000 {
284 compatible = "samsung,exynos7-pinctrl"; 284 compatible = "samsung,exynos7-pinctrl";
285 reg = <0x14ce0000 0x1000>; 285 reg = <0x14ce0000 0x1000>;
286 interrupts = <0 474 0>; 286 interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
287 }; 287 };
288 288
289 pinctrl_ff: pinctrl@14c90000 { 289 pinctrl_ff: pinctrl@14c90000 {
290 compatible = "samsung,exynos7-pinctrl"; 290 compatible = "samsung,exynos7-pinctrl";
291 reg = <0x14c90000 0x1000>; 291 reg = <0x14c90000 0x1000>;
292 interrupts = <0 475 0>; 292 interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
293 }; 293 };
294 294
295 pinctrl_ese: pinctrl@14ca0000 { 295 pinctrl_ese: pinctrl@14ca0000 {
296 compatible = "samsung,exynos7-pinctrl"; 296 compatible = "samsung,exynos7-pinctrl";
297 reg = <0x14ca0000 0x1000>; 297 reg = <0x14ca0000 0x1000>;
298 interrupts = <0 476 0>; 298 interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
299 }; 299 };
300 300
301 pinctrl_fsys0: pinctrl@10e60000 { 301 pinctrl_fsys0: pinctrl@10e60000 {
302 compatible = "samsung,exynos7-pinctrl"; 302 compatible = "samsung,exynos7-pinctrl";
303 reg = <0x10e60000 0x1000>; 303 reg = <0x10e60000 0x1000>;
304 interrupts = <0 221 0>; 304 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
305 }; 305 };
306 306
307 pinctrl_fsys1: pinctrl@15690000 { 307 pinctrl_fsys1: pinctrl@15690000 {
308 compatible = "samsung,exynos7-pinctrl"; 308 compatible = "samsung,exynos7-pinctrl";
309 reg = <0x15690000 0x1000>; 309 reg = <0x15690000 0x1000>;
310 interrupts = <0 203 0>; 310 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
311 }; 311 };
312 312
313 pinctrl_bus1: pinctrl@14870000 { 313 pinctrl_bus1: pinctrl@14870000 {
314 compatible = "samsung,exynos7-pinctrl"; 314 compatible = "samsung,exynos7-pinctrl";
315 reg = <0x14870000 0x1000>; 315 reg = <0x14870000 0x1000>;
316 interrupts = <0 384 0>; 316 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
317 }; 317 };
318 318
319 hsi2c_0: hsi2c@13640000 { 319 hsi2c_0: hsi2c@13640000 {
320 compatible = "samsung,exynos7-hsi2c"; 320 compatible = "samsung,exynos7-hsi2c";
321 reg = <0x13640000 0x1000>; 321 reg = <0x13640000 0x1000>;
322 interrupts = <0 441 0>; 322 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
323 #address-cells = <1>; 323 #address-cells = <1>;
324 #size-cells = <0>; 324 #size-cells = <0>;
325 pinctrl-names = "default"; 325 pinctrl-names = "default";
@@ -332,7 +332,7 @@
332 hsi2c_1: hsi2c@13650000 { 332 hsi2c_1: hsi2c@13650000 {
333 compatible = "samsung,exynos7-hsi2c"; 333 compatible = "samsung,exynos7-hsi2c";
334 reg = <0x13650000 0x1000>; 334 reg = <0x13650000 0x1000>;
335 interrupts = <0 442 0>; 335 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
336 #address-cells = <1>; 336 #address-cells = <1>;
337 #size-cells = <0>; 337 #size-cells = <0>;
338 pinctrl-names = "default"; 338 pinctrl-names = "default";
@@ -345,7 +345,7 @@
345 hsi2c_2: hsi2c@14e60000 { 345 hsi2c_2: hsi2c@14e60000 {
346 compatible = "samsung,exynos7-hsi2c"; 346 compatible = "samsung,exynos7-hsi2c";
347 reg = <0x14e60000 0x1000>; 347 reg = <0x14e60000 0x1000>;
348 interrupts = <0 459 0>; 348 interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>;
349 #address-cells = <1>; 349 #address-cells = <1>;
350 #size-cells = <0>; 350 #size-cells = <0>;
351 pinctrl-names = "default"; 351 pinctrl-names = "default";
@@ -358,7 +358,7 @@
358 hsi2c_3: hsi2c@14e70000 { 358 hsi2c_3: hsi2c@14e70000 {
359 compatible = "samsung,exynos7-hsi2c"; 359 compatible = "samsung,exynos7-hsi2c";
360 reg = <0x14e70000 0x1000>; 360 reg = <0x14e70000 0x1000>;
361 interrupts = <0 460 0>; 361 interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
362 #address-cells = <1>; 362 #address-cells = <1>;
363 #size-cells = <0>; 363 #size-cells = <0>;
364 pinctrl-names = "default"; 364 pinctrl-names = "default";
@@ -371,7 +371,7 @@
371 hsi2c_4: hsi2c@13660000 { 371 hsi2c_4: hsi2c@13660000 {
372 compatible = "samsung,exynos7-hsi2c"; 372 compatible = "samsung,exynos7-hsi2c";
373 reg = <0x13660000 0x1000>; 373 reg = <0x13660000 0x1000>;
374 interrupts = <0 443 0>; 374 interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
375 #address-cells = <1>; 375 #address-cells = <1>;
376 #size-cells = <0>; 376 #size-cells = <0>;
377 pinctrl-names = "default"; 377 pinctrl-names = "default";
@@ -384,7 +384,7 @@
384 hsi2c_5: hsi2c@13670000 { 384 hsi2c_5: hsi2c@13670000 {
385 compatible = "samsung,exynos7-hsi2c"; 385 compatible = "samsung,exynos7-hsi2c";
386 reg = <0x13670000 0x1000>; 386 reg = <0x13670000 0x1000>;
387 interrupts = <0 444 0>; 387 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
388 #address-cells = <1>; 388 #address-cells = <1>;
389 #size-cells = <0>; 389 #size-cells = <0>;
390 pinctrl-names = "default"; 390 pinctrl-names = "default";
@@ -397,7 +397,7 @@
397 hsi2c_6: hsi2c@14e00000 { 397 hsi2c_6: hsi2c@14e00000 {
398 compatible = "samsung,exynos7-hsi2c"; 398 compatible = "samsung,exynos7-hsi2c";
399 reg = <0x14e00000 0x1000>; 399 reg = <0x14e00000 0x1000>;
400 interrupts = <0 461 0>; 400 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
401 #address-cells = <1>; 401 #address-cells = <1>;
402 #size-cells = <0>; 402 #size-cells = <0>;
403 pinctrl-names = "default"; 403 pinctrl-names = "default";
@@ -410,7 +410,7 @@
410 hsi2c_7: hsi2c@13e10000 { 410 hsi2c_7: hsi2c@13e10000 {
411 compatible = "samsung,exynos7-hsi2c"; 411 compatible = "samsung,exynos7-hsi2c";
412 reg = <0x13e10000 0x1000>; 412 reg = <0x13e10000 0x1000>;
413 interrupts = <0 462 0>; 413 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
414 #address-cells = <1>; 414 #address-cells = <1>;
415 #size-cells = <0>; 415 #size-cells = <0>;
416 pinctrl-names = "default"; 416 pinctrl-names = "default";
@@ -423,7 +423,7 @@
423 hsi2c_8: hsi2c@14e20000 { 423 hsi2c_8: hsi2c@14e20000 {
424 compatible = "samsung,exynos7-hsi2c"; 424 compatible = "samsung,exynos7-hsi2c";
425 reg = <0x14e20000 0x1000>; 425 reg = <0x14e20000 0x1000>;
426 interrupts = <0 463 0>; 426 interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>;
427 #address-cells = <1>; 427 #address-cells = <1>;
428 #size-cells = <0>; 428 #size-cells = <0>;
429 pinctrl-names = "default"; 429 pinctrl-names = "default";
@@ -436,7 +436,7 @@
436 hsi2c_9: hsi2c@13680000 { 436 hsi2c_9: hsi2c@13680000 {
437 compatible = "samsung,exynos7-hsi2c"; 437 compatible = "samsung,exynos7-hsi2c";
438 reg = <0x13680000 0x1000>; 438 reg = <0x13680000 0x1000>;
439 interrupts = <0 445 0>; 439 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
440 #address-cells = <1>; 440 #address-cells = <1>;
441 #size-cells = <0>; 441 #size-cells = <0>;
442 pinctrl-names = "default"; 442 pinctrl-names = "default";
@@ -449,7 +449,7 @@
449 hsi2c_10: hsi2c@13690000 { 449 hsi2c_10: hsi2c@13690000 {
450 compatible = "samsung,exynos7-hsi2c"; 450 compatible = "samsung,exynos7-hsi2c";
451 reg = <0x13690000 0x1000>; 451 reg = <0x13690000 0x1000>;
452 interrupts = <0 446 0>; 452 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
453 #address-cells = <1>; 453 #address-cells = <1>;
454 #size-cells = <0>; 454 #size-cells = <0>;
455 pinctrl-names = "default"; 455 pinctrl-names = "default";
@@ -462,7 +462,7 @@
462 hsi2c_11: hsi2c@136a0000 { 462 hsi2c_11: hsi2c@136a0000 {
463 compatible = "samsung,exynos7-hsi2c"; 463 compatible = "samsung,exynos7-hsi2c";
464 reg = <0x136a0000 0x1000>; 464 reg = <0x136a0000 0x1000>;
465 interrupts = <0 447 0>; 465 interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
466 #address-cells = <1>; 466 #address-cells = <1>;
467 #size-cells = <0>; 467 #size-cells = <0>;
468 pinctrl-names = "default"; 468 pinctrl-names = "default";
@@ -472,6 +472,16 @@
472 status = "disabled"; 472 status = "disabled";
473 }; 473 };
474 474
475 arm-pmu {
476 compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
477 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
481 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
482 <&cpu_atlas2>, <&cpu_atlas3>;
483 };
484
475 timer { 485 timer {
476 compatible = "arm,armv8-timer"; 486 compatible = "arm,armv8-timer";
477 interrupts = <GIC_PPI 13 487 interrupts = <GIC_PPI 13
@@ -499,7 +509,8 @@
499 rtc: rtc@10590000 { 509 rtc: rtc@10590000 {
500 compatible = "samsung,s3c6410-rtc"; 510 compatible = "samsung,s3c6410-rtc";
501 reg = <0x10590000 0x100>; 511 reg = <0x10590000 0x100>;
502 interrupts = <0 355 0>, <0 356 0>; 512 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&clock_ccore PCLK_RTC>; 514 clocks = <&clock_ccore PCLK_RTC>;
504 clock-names = "rtc"; 515 clock-names = "rtc";
505 status = "disabled"; 516 status = "disabled";
@@ -508,7 +519,7 @@
508 watchdog: watchdog@101d0000 { 519 watchdog: watchdog@101d0000 {
509 compatible = "samsung,exynos7-wdt"; 520 compatible = "samsung,exynos7-wdt";
510 reg = <0x101d0000 0x100>; 521 reg = <0x101d0000 0x100>;
511 interrupts = <0 110 0>; 522 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&clock_peris PCLK_WDT>; 523 clocks = <&clock_peris PCLK_WDT>;
513 clock-names = "watchdog"; 524 clock-names = "watchdog";
514 samsung,syscon-phandle = <&pmu_system_controller>; 525 samsung,syscon-phandle = <&pmu_system_controller>;
@@ -517,7 +528,7 @@
517 528
518 mmc_0: mmc@15740000 { 529 mmc_0: mmc@15740000 {
519 compatible = "samsung,exynos7-dw-mshc-smu"; 530 compatible = "samsung,exynos7-dw-mshc-smu";
520 interrupts = <0 201 0>; 531 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
521 #address-cells = <1>; 532 #address-cells = <1>;
522 #size-cells = <0>; 533 #size-cells = <0>;
523 reg = <0x15740000 0x2000>; 534 reg = <0x15740000 0x2000>;
@@ -530,7 +541,7 @@
530 541
531 mmc_1: mmc@15750000 { 542 mmc_1: mmc@15750000 {
532 compatible = "samsung,exynos7-dw-mshc"; 543 compatible = "samsung,exynos7-dw-mshc";
533 interrupts = <0 202 0>; 544 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
534 #address-cells = <1>; 545 #address-cells = <1>;
535 #size-cells = <0>; 546 #size-cells = <0>;
536 reg = <0x15750000 0x2000>; 547 reg = <0x15750000 0x2000>;
@@ -543,7 +554,7 @@
543 554
544 mmc_2: mmc@15560000 { 555 mmc_2: mmc@15560000 {
545 compatible = "samsung,exynos7-dw-mshc-smu"; 556 compatible = "samsung,exynos7-dw-mshc-smu";
546 interrupts = <0 216 0>; 557 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
547 #address-cells = <1>; 558 #address-cells = <1>;
548 #size-cells = <0>; 559 #size-cells = <0>;
549 reg = <0x15560000 0x2000>; 560 reg = <0x15560000 0x2000>;
@@ -557,7 +568,7 @@
557 adc: adc@13620000 { 568 adc: adc@13620000 {
558 compatible = "samsung,exynos7-adc"; 569 compatible = "samsung,exynos7-adc";
559 reg = <0x13620000 0x100>; 570 reg = <0x13620000 0x100>;
560 interrupts = <0 448 0>; 571 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&clock_peric0 PCLK_ADCIF>; 572 clocks = <&clock_peric0 PCLK_ADCIF>;
562 clock-names = "adc"; 573 clock-names = "adc";
563 #io-channel-cells = <1>; 574 #io-channel-cells = <1>;
@@ -577,7 +588,7 @@
577 tmuctrl_0: tmu@10060000 { 588 tmuctrl_0: tmu@10060000 {
578 compatible = "samsung,exynos7-tmu"; 589 compatible = "samsung,exynos7-tmu";
579 reg = <0x10060000 0x200>; 590 reg = <0x10060000 0x200>;
580 interrupts = <0 108 0>; 591 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&clock_peris PCLK_TMU>, 592 clocks = <&clock_peris PCLK_TMU>,
582 <&clock_peris SCLK_TMU>; 593 <&clock_peris SCLK_TMU>;
583 clock-names = "tmu_apbif", "tmu_sclk"; 594 clock-names = "tmu_apbif", "tmu_sclk";
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 1b7783db7de4..66027181fba4 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -1,5 +1,7 @@
1dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb 1dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
2dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb 2dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
3dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
4dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
3dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb 5dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
4dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb 6dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
5dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb 7dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
index dd9e91941df4..0989d635b558 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
@@ -45,7 +45,7 @@
45 */ 45 */
46 46
47/dts-v1/; 47/dts-v1/;
48/include/ "fsl-ls1043a.dtsi" 48#include "fsl-ls1043a.dtsi"
49 49
50/ { 50/ {
51 model = "LS1043A QDS Board"; 51 model = "LS1043A QDS Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index d2313e05fd22..c37110bc1506 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -45,7 +45,7 @@
45 */ 45 */
46 46
47/dts-v1/; 47/dts-v1/;
48/include/ "fsl-ls1043a.dtsi" 48#include "fsl-ls1043a.dtsi"
49 49
50/ { 50/ {
51 model = "LS1043A RDB Board"; 51 model = "LS1043A RDB Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 97d331ec2500..ec13a6ecb754 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -44,6 +44,8 @@
44 * OTHER DEALINGS IN THE SOFTWARE. 44 * OTHER DEALINGS IN THE SOFTWARE.
45 */ 45 */
46 46
47#include <dt-bindings/thermal/thermal.h>
48
47/ { 49/ {
48 compatible = "fsl,ls1043a"; 50 compatible = "fsl,ls1043a";
49 interrupt-parent = <&gic>; 51 interrupt-parent = <&gic>;
@@ -66,6 +68,7 @@
66 reg = <0x0>; 68 reg = <0x0>;
67 clocks = <&clockgen 1 0>; 69 clocks = <&clockgen 1 0>;
68 next-level-cache = <&l2>; 70 next-level-cache = <&l2>;
71 #cooling-cells = <2>;
69 }; 72 };
70 73
71 cpu1: cpu@1 { 74 cpu1: cpu@1 {
@@ -255,6 +258,81 @@
255 big-endian; 258 big-endian;
256 }; 259 };
257 260
261 tmu: tmu@1f00000 {
262 compatible = "fsl,qoriq-tmu";
263 reg = <0x0 0x1f00000 0x0 0x10000>;
264 interrupts = <0 33 0x4>;
265 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
266 fsl,tmu-calibration = <0x00000000 0x00000026
267 0x00000001 0x0000002d
268 0x00000002 0x00000032
269 0x00000003 0x00000039
270 0x00000004 0x0000003f
271 0x00000005 0x00000046
272 0x00000006 0x0000004d
273 0x00000007 0x00000054
274 0x00000008 0x0000005a
275 0x00000009 0x00000061
276 0x0000000a 0x0000006a
277 0x0000000b 0x00000071
278
279 0x00010000 0x00000025
280 0x00010001 0x0000002c
281 0x00010002 0x00000035
282 0x00010003 0x0000003d
283 0x00010004 0x00000045
284 0x00010005 0x0000004e
285 0x00010006 0x00000057
286 0x00010007 0x00000061
287 0x00010008 0x0000006b
288 0x00010009 0x00000076
289
290 0x00020000 0x00000029
291 0x00020001 0x00000033
292 0x00020002 0x0000003d
293 0x00020003 0x00000049
294 0x00020004 0x00000056
295 0x00020005 0x00000061
296 0x00020006 0x0000006d
297
298 0x00030000 0x00000021
299 0x00030001 0x0000002a
300 0x00030002 0x0000003c
301 0x00030003 0x0000004e>;
302 #thermal-sensor-cells = <1>;
303 };
304
305 thermal-zones {
306 cpu_thermal: cpu-thermal {
307 polling-delay-passive = <1000>;
308 polling-delay = <5000>;
309
310 thermal-sensors = <&tmu 3>;
311
312 trips {
313 cpu_alert: cpu-alert {
314 temperature = <85000>;
315 hysteresis = <2000>;
316 type = "passive";
317 };
318 cpu_crit: cpu-crit {
319 temperature = <95000>;
320 hysteresis = <2000>;
321 type = "critical";
322 };
323 };
324
325 cooling-maps {
326 map0 {
327 trip = <&cpu_alert>;
328 cooling-device =
329 <&cpu0 THERMAL_NO_LIMIT
330 THERMAL_NO_LIMIT>;
331 };
332 };
333 };
334 };
335
258 dspi0: dspi@2100000 { 336 dspi0: dspi@2100000 {
259 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; 337 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
260 #address-cells = <1>; 338 #address-cells = <1>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
new file mode 100644
index 000000000000..290e5b014414
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
@@ -0,0 +1,212 @@
1/*
2 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3 *
4 * Copyright 2016, Freescale Semiconductor, Inc.
5 *
6 * Shaohui Xie <Shaohui.Xie@nxp.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47/dts-v1/;
48
49#include "fsl-ls1046a.dtsi"
50
51/ {
52 model = "LS1046A QDS Board";
53 compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
54
55 aliases {
56 gpio0 = &gpio0;
57 gpio1 = &gpio1;
58 gpio2 = &gpio2;
59 gpio3 = &gpio3;
60 serial0 = &duart0;
61 serial1 = &duart1;
62 serial2 = &duart2;
63 serial3 = &duart3;
64 };
65
66 chosen {
67 stdout-path = "serial0:115200n8";
68 };
69};
70
71&dspi {
72 bus-num = <0>;
73 status = "okay";
74
75 flash@0 {
76 #address-cells = <1>;
77 #size-cells = <1>;
78 compatible = "n25q128a11", "jedec,spi-nor";
79 reg = <0>;
80 spi-max-frequency = <10000000>;
81 };
82
83 flash@1 {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 compatible = "sst25wf040b", "jedec,spi-nor";
87 spi-cpol;
88 spi-cpha;
89 reg = <1>;
90 spi-max-frequency = <10000000>;
91 };
92
93 flash@2 {
94 #address-cells = <1>;
95 #size-cells = <1>;
96 compatible = "en25s64", "jedec,spi-nor";
97 spi-cpol;
98 spi-cpha;
99 reg = <2>;
100 spi-max-frequency = <10000000>;
101 };
102};
103
104&duart0 {
105 status = "okay";
106};
107
108&duart1 {
109 status = "okay";
110};
111
112&i2c0 {
113 status = "okay";
114
115 pca9547@77 {
116 compatible = "nxp,pca9547";
117 reg = <0x77>;
118 #address-cells = <1>;
119 #size-cells = <0>;
120
121 i2c@2 {
122 #address-cells = <1>;
123 #size-cells = <0>;
124 reg = <0x2>;
125
126 ina220@40 {
127 compatible = "ti,ina220";
128 reg = <0x40>;
129 shunt-resistor = <1000>;
130 };
131
132 ina220@41 {
133 compatible = "ti,ina220";
134 reg = <0x41>;
135 shunt-resistor = <1000>;
136 };
137 };
138
139 i2c@3 {
140 #address-cells = <1>;
141 #size-cells = <0>;
142 reg = <0x3>;
143
144 rtc@51 {
145 compatible = "nxp,pcf2129";
146 reg = <0x51>;
147 /* IRQ10_B */
148 interrupts = <0 150 0x4>;
149 };
150
151 eeprom@56 {
152 compatible = "atmel,24c512";
153 reg = <0x56>;
154 };
155
156 eeprom@57 {
157 compatible = "atmel,24c512";
158 reg = <0x57>;
159 };
160
161 temp-sensor@4c {
162 compatible = "adi,adt7461a";
163 reg = <0x4c>;
164 };
165 };
166 };
167};
168
169&ifc {
170 #address-cells = <2>;
171 #size-cells = <1>;
172 /* NOR, NAND Flashes and FPGA on board */
173 ranges = <0x0 0x0 0x0 0x60000000 0x08000000
174 0x1 0x0 0x0 0x7e800000 0x00010000
175 0x2 0x0 0x0 0x7fb00000 0x00000100>;
176 status = "okay";
177
178 nor@0,0 {
179 compatible = "cfi-flash";
180 reg = <0x0 0x0 0x8000000>;
181 bank-width = <2>;
182 device-width = <1>;
183 };
184
185 nand@1,0 {
186 compatible = "fsl,ifc-nand";
187 reg = <0x1 0x0 0x10000>;
188 };
189
190 fpga: board-control@2,0 {
191 compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis";
192 reg = <0x2 0x0 0x0000100>;
193 };
194};
195
196&lpuart0 {
197 status = "okay";
198};
199
200&qspi {
201 num-cs = <2>;
202 bus-num = <0>;
203 status = "okay";
204
205 qflash0: s25fl128s@0 {
206 compatible = "spansion,m25p80";
207 #address-cells = <1>;
208 #size-cells = <1>;
209 spi-max-frequency = <20000000>;
210 reg = <0>;
211 };
212};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
new file mode 100644
index 000000000000..d1ccc000d05a
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -0,0 +1,150 @@
1/*
2 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3 *
4 * Copyright 2016, Freescale Semiconductor, Inc.
5 *
6 * Mingkai Hu <mingkai.hu@nxp.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47/dts-v1/;
48
49#include "fsl-ls1046a.dtsi"
50
51/ {
52 model = "LS1046A RDB Board";
53 compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
54
55 aliases {
56 serial0 = &duart0;
57 serial1 = &duart1;
58 serial2 = &duart2;
59 serial3 = &duart3;
60 };
61
62 chosen {
63 stdout-path = "serial0:115200n8";
64 };
65};
66
67&duart0 {
68 status = "okay";
69};
70
71&duart1 {
72 status = "okay";
73};
74
75&i2c0 {
76 status = "okay";
77
78 ina220@40 {
79 compatible = "ti,ina220";
80 reg = <0x40>;
81 shunt-resistor = <1000>;
82 };
83
84 temp-sensor@4c {
85 compatible = "adi,adt7461";
86 reg = <0x4c>;
87 };
88
89 eeprom@56 {
90 compatible = "atmel,24c512";
91 reg = <0x52>;
92 };
93
94 eeprom@57 {
95 compatible = "atmel,24c512";
96 reg = <0x53>;
97 };
98};
99
100&i2c3 {
101 status = "okay";
102
103 rtc@51 {
104 compatible = "nxp,pcf2129";
105 reg = <0x51>;
106 };
107};
108
109&ifc {
110 #address-cells = <2>;
111 #size-cells = <1>;
112 /* NAND Flashe and CPLD on board */
113 ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
114 0x2 0x0 0x0 0x7fb00000 0x00000100>;
115 status = "okay";
116
117 nand@0,0 {
118 compatible = "fsl,ifc-nand";
119 #address-cells = <1>;
120 #size-cells = <1>;
121 reg = <0x0 0x0 0x10000>;
122 };
123
124 cpld: board-control@2,0 {
125 compatible = "fsl,ls1046ardb-cpld";
126 reg = <0x2 0x0 0x0000100>;
127 };
128};
129
130&qspi {
131 num-cs = <2>;
132 bus-num = <0>;
133 status = "okay";
134
135 qflash0: s25fs512s@0 {
136 compatible = "spansion,m25p80";
137 #address-cells = <1>;
138 #size-cells = <1>;
139 spi-max-frequency = <20000000>;
140 reg = <0>;
141 };
142
143 qflash1: s25fs512s@1 {
144 compatible = "spansion,m25p80";
145 #address-cells = <1>;
146 #size-cells = <1>;
147 spi-max-frequency = <20000000>;
148 reg = <1>;
149 };
150};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
new file mode 100644
index 000000000000..38806ca53829
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -0,0 +1,515 @@
1/*
2 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3 *
4 * Copyright 2016, Freescale Semiconductor, Inc.
5 *
6 * Mingkai Hu <mingkai.hu@nxp.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47#include <dt-bindings/interrupt-controller/arm-gic.h>
48
49/ {
50 compatible = "fsl,ls1046a";
51 interrupt-parent = <&gic>;
52 #address-cells = <2>;
53 #size-cells = <2>;
54
55 aliases {
56 crypto = &crypto;
57 };
58
59 cpus {
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 cpu0: cpu@0 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a72";
66 reg = <0x0>;
67 clocks = <&clockgen 1 0>;
68 next-level-cache = <&l2>;
69 cpu-idle-states = <&CPU_PH20>;
70 };
71
72 cpu1: cpu@1 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a72";
75 reg = <0x1>;
76 clocks = <&clockgen 1 0>;
77 next-level-cache = <&l2>;
78 cpu-idle-states = <&CPU_PH20>;
79 };
80
81 cpu2: cpu@2 {
82 device_type = "cpu";
83 compatible = "arm,cortex-a72";
84 reg = <0x2>;
85 clocks = <&clockgen 1 0>;
86 next-level-cache = <&l2>;
87 cpu-idle-states = <&CPU_PH20>;
88 };
89
90 cpu3: cpu@3 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a72";
93 reg = <0x3>;
94 clocks = <&clockgen 1 0>;
95 next-level-cache = <&l2>;
96 cpu-idle-states = <&CPU_PH20>;
97 };
98
99 l2: l2-cache {
100 compatible = "cache";
101 };
102 };
103
104 idle-states {
105 /*
106 * PSCI node is not added default, U-boot will add missing
107 * parts if it determines to use PSCI.
108 */
109 entry-method = "arm,psci";
110
111 CPU_PH20: cpu-ph20 {
112 compatible = "arm,idle-state";
113 idle-state-name = "PH20";
114 arm,psci-suspend-param = <0x00010000>;
115 entry-latency-us = <1000>;
116 exit-latency-us = <1000>;
117 min-residency-us = <3000>;
118 };
119 };
120
121 memory@80000000 {
122 device_type = "memory";
123 };
124
125 sysclk: sysclk {
126 compatible = "fixed-clock";
127 #clock-cells = <0>;
128 clock-frequency = <100000000>;
129 clock-output-names = "sysclk";
130 };
131
132 reboot {
133 compatible ="syscon-reboot";
134 regmap = <&dcfg>;
135 offset = <0xb0>;
136 mask = <0x02>;
137 };
138
139 timer {
140 compatible = "arm,armv8-timer";
141 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
142 IRQ_TYPE_LEVEL_LOW)>,
143 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
144 IRQ_TYPE_LEVEL_LOW)>,
145 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
146 IRQ_TYPE_LEVEL_LOW)>,
147 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
148 IRQ_TYPE_LEVEL_LOW)>;
149 };
150
151 pmu {
152 compatible = "arm,cortex-a72-pmu";
153 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
157 interrupt-affinity = <&cpu0>,
158 <&cpu1>,
159 <&cpu2>,
160 <&cpu3>;
161 };
162
163 gic: interrupt-controller@1400000 {
164 compatible = "arm,gic-400";
165 #interrupt-cells = <3>;
166 interrupt-controller;
167 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
168 <0x0 0x1420000 0 0x20000>, /* GICC */
169 <0x0 0x1440000 0 0x20000>, /* GICH */
170 <0x0 0x1460000 0 0x20000>; /* GICV */
171 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
172 IRQ_TYPE_LEVEL_LOW)>;
173 };
174
175 soc {
176 compatible = "simple-bus";
177 #address-cells = <2>;
178 #size-cells = <2>;
179 ranges;
180
181 ddr: memory-controller@1080000 {
182 compatible = "fsl,qoriq-memory-controller";
183 reg = <0x0 0x1080000 0x0 0x1000>;
184 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
185 big-endian;
186 };
187
188 ifc: ifc@1530000 {
189 compatible = "fsl,ifc", "simple-bus";
190 reg = <0x0 0x1530000 0x0 0x10000>;
191 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
192 };
193
194 qspi: quadspi@1550000 {
195 compatible = "fsl,ls1021a-qspi";
196 #address-cells = <1>;
197 #size-cells = <0>;
198 reg = <0x0 0x1550000 0x0 0x10000>,
199 <0x0 0x40000000 0x0 0x10000000>;
200 reg-names = "QuadSPI", "QuadSPI-memory";
201 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
202 clock-names = "qspi_en", "qspi";
203 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
204 big-endian;
205 fsl,qspi-has-second-chip;
206 status = "disabled";
207 };
208
209 esdhc: esdhc@1560000 {
210 compatible = "fsl,esdhc";
211 reg = <0x0 0x1560000 0x0 0x10000>;
212 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
213 clock-frequency = <0>;
214 voltage-ranges = <1800 1800 3300 3300>;
215 sdhci,auto-cmd12;
216 big-endian;
217 bus-width = <4>;
218 };
219
220 scfg: scfg@1570000 {
221 compatible = "fsl,ls1046a-scfg", "syscon";
222 reg = <0x0 0x1570000 0x0 0x10000>;
223 big-endian;
224 };
225
226 crypto: crypto@1700000 {
227 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
228 "fsl,sec-v4.0";
229 fsl,sec-era = <8>;
230 #address-cells = <1>;
231 #size-cells = <1>;
232 ranges = <0x0 0x00 0x1700000 0x100000>;
233 reg = <0x00 0x1700000 0x0 0x100000>;
234 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
235
236 sec_jr0: jr@10000 {
237 compatible = "fsl,sec-v5.4-job-ring",
238 "fsl,sec-v5.0-job-ring",
239 "fsl,sec-v4.0-job-ring";
240 reg = <0x10000 0x10000>;
241 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
242 };
243
244 sec_jr1: jr@20000 {
245 compatible = "fsl,sec-v5.4-job-ring",
246 "fsl,sec-v5.0-job-ring",
247 "fsl,sec-v4.0-job-ring";
248 reg = <0x20000 0x10000>;
249 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
250 };
251
252 sec_jr2: jr@30000 {
253 compatible = "fsl,sec-v5.4-job-ring",
254 "fsl,sec-v5.0-job-ring",
255 "fsl,sec-v4.0-job-ring";
256 reg = <0x30000 0x10000>;
257 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
258 };
259
260 sec_jr3: jr@40000 {
261 compatible = "fsl,sec-v5.4-job-ring",
262 "fsl,sec-v5.0-job-ring",
263 "fsl,sec-v4.0-job-ring";
264 reg = <0x40000 0x10000>;
265 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
266 };
267 };
268
269 dcfg: dcfg@1ee0000 {
270 compatible = "fsl,ls1046a-dcfg", "syscon";
271 reg = <0x0 0x1ee0000 0x0 0x10000>;
272 big-endian;
273 };
274
275 clockgen: clocking@1ee1000 {
276 compatible = "fsl,ls1046a-clockgen";
277 reg = <0x0 0x1ee1000 0x0 0x1000>;
278 #clock-cells = <2>;
279 clocks = <&sysclk>;
280 };
281
282 dspi: dspi@2100000 {
283 compatible = "fsl,ls1021a-v1.0-dspi";
284 #address-cells = <1>;
285 #size-cells = <0>;
286 reg = <0x0 0x2100000 0x0 0x10000>;
287 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
288 clock-names = "dspi";
289 clocks = <&clockgen 4 1>;
290 spi-num-chipselects = <5>;
291 big-endian;
292 status = "disabled";
293 };
294
295 i2c0: i2c@2180000 {
296 compatible = "fsl,vf610-i2c";
297 #address-cells = <1>;
298 #size-cells = <0>;
299 reg = <0x0 0x2180000 0x0 0x10000>;
300 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&clockgen 4 1>;
302 dmas = <&edma0 1 39>,
303 <&edma0 1 38>;
304 dma-names = "tx", "rx";
305 status = "disabled";
306 };
307
308 i2c1: i2c@2190000 {
309 compatible = "fsl,vf610-i2c";
310 #address-cells = <1>;
311 #size-cells = <0>;
312 reg = <0x0 0x2190000 0x0 0x10000>;
313 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&clockgen 4 1>;
315 status = "disabled";
316 };
317
318 i2c2: i2c@21a0000 {
319 compatible = "fsl,vf610-i2c";
320 #address-cells = <1>;
321 #size-cells = <0>;
322 reg = <0x0 0x21a0000 0x0 0x10000>;
323 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&clockgen 4 1>;
325 status = "disabled";
326 };
327
328 i2c3: i2c@21b0000 {
329 compatible = "fsl,vf610-i2c";
330 #address-cells = <1>;
331 #size-cells = <0>;
332 reg = <0x0 0x21b0000 0x0 0x10000>;
333 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&clockgen 4 1>;
335 status = "disabled";
336 };
337
338 duart0: serial@21c0500 {
339 compatible = "fsl,ns16550", "ns16550a";
340 reg = <0x00 0x21c0500 0x0 0x100>;
341 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&clockgen 4 1>;
343 };
344
345 duart1: serial@21c0600 {
346 compatible = "fsl,ns16550", "ns16550a";
347 reg = <0x00 0x21c0600 0x0 0x100>;
348 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&clockgen 4 1>;
350 };
351
352 duart2: serial@21d0500 {
353 compatible = "fsl,ns16550", "ns16550a";
354 reg = <0x0 0x21d0500 0x0 0x100>;
355 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&clockgen 4 1>;
357 };
358
359 duart3: serial@21d0600 {
360 compatible = "fsl,ns16550", "ns16550a";
361 reg = <0x0 0x21d0600 0x0 0x100>;
362 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&clockgen 4 1>;
364 };
365
366 gpio0: gpio@2300000 {
367 compatible = "fsl,qoriq-gpio";
368 reg = <0x0 0x2300000 0x0 0x10000>;
369 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
370 gpio-controller;
371 #gpio-cells = <2>;
372 interrupt-controller;
373 #interrupt-cells = <2>;
374 };
375
376 gpio1: gpio@2310000 {
377 compatible = "fsl,qoriq-gpio";
378 reg = <0x0 0x2310000 0x0 0x10000>;
379 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
380 gpio-controller;
381 #gpio-cells = <2>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 };
385
386 gpio2: gpio@2320000 {
387 compatible = "fsl,qoriq-gpio";
388 reg = <0x0 0x2320000 0x0 0x10000>;
389 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
390 gpio-controller;
391 #gpio-cells = <2>;
392 interrupt-controller;
393 #interrupt-cells = <2>;
394 };
395
396 gpio3: gpio@2330000 {
397 compatible = "fsl,qoriq-gpio";
398 reg = <0x0 0x2330000 0x0 0x10000>;
399 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
400 gpio-controller;
401 #gpio-cells = <2>;
402 interrupt-controller;
403 #interrupt-cells = <2>;
404 };
405
406 lpuart0: serial@2950000 {
407 compatible = "fsl,ls1021a-lpuart";
408 reg = <0x0 0x2950000 0x0 0x1000>;
409 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&clockgen 4 0>;
411 clock-names = "ipg";
412 status = "disabled";
413 };
414
415 lpuart1: serial@2960000 {
416 compatible = "fsl,ls1021a-lpuart";
417 reg = <0x0 0x2960000 0x0 0x1000>;
418 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&clockgen 4 1>;
420 clock-names = "ipg";
421 status = "disabled";
422 };
423
424 lpuart2: serial@2970000 {
425 compatible = "fsl,ls1021a-lpuart";
426 reg = <0x0 0x2970000 0x0 0x1000>;
427 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&clockgen 4 1>;
429 clock-names = "ipg";
430 status = "disabled";
431 };
432
433 lpuart3: serial@2980000 {
434 compatible = "fsl,ls1021a-lpuart";
435 reg = <0x0 0x2980000 0x0 0x1000>;
436 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&clockgen 4 1>;
438 clock-names = "ipg";
439 status = "disabled";
440 };
441
442 lpuart4: serial@2990000 {
443 compatible = "fsl,ls1021a-lpuart";
444 reg = <0x0 0x2990000 0x0 0x1000>;
445 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&clockgen 4 1>;
447 clock-names = "ipg";
448 status = "disabled";
449 };
450
451 lpuart5: serial@29a0000 {
452 compatible = "fsl,ls1021a-lpuart";
453 reg = <0x0 0x29a0000 0x0 0x1000>;
454 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&clockgen 4 1>;
456 clock-names = "ipg";
457 status = "disabled";
458 };
459
460 wdog0: watchdog@2ad0000 {
461 compatible = "fsl,imx21-wdt";
462 reg = <0x0 0x2ad0000 0x0 0x10000>;
463 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&clockgen 4 1>;
465 big-endian;
466 };
467
468 edma0: edma@2c00000 {
469 #dma-cells = <2>;
470 compatible = "fsl,vf610-edma";
471 reg = <0x0 0x2c00000 0x0 0x10000>,
472 <0x0 0x2c10000 0x0 0x10000>,
473 <0x0 0x2c20000 0x0 0x10000>;
474 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
476 interrupt-names = "edma-tx", "edma-err";
477 dma-channels = <32>;
478 big-endian;
479 clock-names = "dmamux0", "dmamux1";
480 clocks = <&clockgen 4 1>,
481 <&clockgen 4 1>;
482 };
483
484 usb0: usb@2f00000 {
485 compatible = "snps,dwc3";
486 reg = <0x0 0x2f00000 0x0 0x10000>;
487 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
488 dr_mode = "host";
489 snps,quirk-frame-length-adjustment = <0x20>;
490 };
491
492 usb1: usb@3000000 {
493 compatible = "snps,dwc3";
494 reg = <0x0 0x3000000 0x0 0x10000>;
495 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
496 dr_mode = "host";
497 snps,quirk-frame-length-adjustment = <0x20>;
498 };
499
500 usb2: usb@3100000 {
501 compatible = "snps,dwc3";
502 reg = <0x0 0x3100000 0x0 0x10000>;
503 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
504 dr_mode = "host";
505 snps,quirk-frame-length-adjustment = <0x20>;
506 };
507
508 sata: sata@3200000 {
509 compatible = "fsl,ls1046a-ahci";
510 reg = <0x0 0x3200000 0x0 0x10000>;
511 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&clockgen 4 1>;
513 };
514 };
515};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
index b0dd010979e7..8bc1f8f6fcfc 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
@@ -46,7 +46,7 @@
46 46
47/dts-v1/; 47/dts-v1/;
48 48
49/include/ "fsl-ls2080a.dtsi" 49#include "fsl-ls2080a.dtsi"
50 50
51/ { 51/ {
52 model = "Freescale Layerscape 2080a QDS Board"; 52 model = "Freescale Layerscape 2080a QDS Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
index ad0ebb8a1949..265e0a8b107b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
@@ -46,7 +46,7 @@
46 46
47/dts-v1/; 47/dts-v1/;
48 48
49/include/ "fsl-ls2080a.dtsi" 49#include "fsl-ls2080a.dtsi"
50 50
51/ { 51/ {
52 model = "Freescale Layerscape 2080a RDB Board"; 52 model = "Freescale Layerscape 2080a RDB Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
index 505d038078a3..290604b0a603 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
@@ -46,7 +46,7 @@
46 46
47/dts-v1/; 47/dts-v1/;
48 48
49/include/ "fsl-ls2080a.dtsi" 49#include "fsl-ls2080a.dtsi"
50 50
51/ { 51/ {
52 model = "Freescale Layerscape 2080a software Simulator model"; 52 model = "Freescale Layerscape 2080a software Simulator model";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index d058e56db72d..e5935f28848c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -44,6 +44,8 @@
44 * OTHER DEALINGS IN THE SOFTWARE. 44 * OTHER DEALINGS IN THE SOFTWARE.
45 */ 45 */
46 46
47#include <dt-bindings/thermal/thermal.h>
48
47/ { 49/ {
48 compatible = "fsl,ls2080a"; 50 compatible = "fsl,ls2080a";
49 interrupt-parent = <&gic>; 51 interrupt-parent = <&gic>;
@@ -62,15 +64,16 @@
62 */ 64 */
63 65
64 /* We have 4 clusters having 2 Cortex-A57 cores each */ 66 /* We have 4 clusters having 2 Cortex-A57 cores each */
65 cpu@0 { 67 cpu0: cpu@0 {
66 device_type = "cpu"; 68 device_type = "cpu";
67 compatible = "arm,cortex-a57"; 69 compatible = "arm,cortex-a57";
68 reg = <0x0>; 70 reg = <0x0>;
69 clocks = <&clockgen 1 0>; 71 clocks = <&clockgen 1 0>;
70 next-level-cache = <&cluster0_l2>; 72 next-level-cache = <&cluster0_l2>;
73 #cooling-cells = <2>;
71 }; 74 };
72 75
73 cpu@1 { 76 cpu1: cpu@1 {
74 device_type = "cpu"; 77 device_type = "cpu";
75 compatible = "arm,cortex-a57"; 78 compatible = "arm,cortex-a57";
76 reg = <0x1>; 79 reg = <0x1>;
@@ -78,15 +81,16 @@
78 next-level-cache = <&cluster0_l2>; 81 next-level-cache = <&cluster0_l2>;
79 }; 82 };
80 83
81 cpu@100 { 84 cpu2: cpu@100 {
82 device_type = "cpu"; 85 device_type = "cpu";
83 compatible = "arm,cortex-a57"; 86 compatible = "arm,cortex-a57";
84 reg = <0x100>; 87 reg = <0x100>;
85 clocks = <&clockgen 1 1>; 88 clocks = <&clockgen 1 1>;
86 next-level-cache = <&cluster1_l2>; 89 next-level-cache = <&cluster1_l2>;
90 #cooling-cells = <2>;
87 }; 91 };
88 92
89 cpu@101 { 93 cpu3: cpu@101 {
90 device_type = "cpu"; 94 device_type = "cpu";
91 compatible = "arm,cortex-a57"; 95 compatible = "arm,cortex-a57";
92 reg = <0x101>; 96 reg = <0x101>;
@@ -94,15 +98,16 @@
94 next-level-cache = <&cluster1_l2>; 98 next-level-cache = <&cluster1_l2>;
95 }; 99 };
96 100
97 cpu@200 { 101 cpu4: cpu@200 {
98 device_type = "cpu"; 102 device_type = "cpu";
99 compatible = "arm,cortex-a57"; 103 compatible = "arm,cortex-a57";
100 reg = <0x200>; 104 reg = <0x200>;
101 clocks = <&clockgen 1 2>; 105 clocks = <&clockgen 1 2>;
102 next-level-cache = <&cluster2_l2>; 106 next-level-cache = <&cluster2_l2>;
107 #cooling-cells = <2>;
103 }; 108 };
104 109
105 cpu@201 { 110 cpu5: cpu@201 {
106 device_type = "cpu"; 111 device_type = "cpu";
107 compatible = "arm,cortex-a57"; 112 compatible = "arm,cortex-a57";
108 reg = <0x201>; 113 reg = <0x201>;
@@ -110,15 +115,16 @@
110 next-level-cache = <&cluster2_l2>; 115 next-level-cache = <&cluster2_l2>;
111 }; 116 };
112 117
113 cpu@300 { 118 cpu6: cpu@300 {
114 device_type = "cpu"; 119 device_type = "cpu";
115 compatible = "arm,cortex-a57"; 120 compatible = "arm,cortex-a57";
116 reg = <0x300>; 121 reg = <0x300>;
117 clocks = <&clockgen 1 3>; 122 clocks = <&clockgen 1 3>;
118 next-level-cache = <&cluster3_l2>; 123 next-level-cache = <&cluster3_l2>;
124 #cooling-cells = <2>;
119 }; 125 };
120 126
121 cpu@301 { 127 cpu7: cpu@301 {
122 device_type = "cpu"; 128 device_type = "cpu";
123 compatible = "arm,cortex-a57"; 129 compatible = "arm,cortex-a57";
124 reg = <0x301>; 130 reg = <0x301>;
@@ -222,6 +228,100 @@
222 little-endian; 228 little-endian;
223 }; 229 };
224 230
231 tmu: tmu@1f80000 {
232 compatible = "fsl,qoriq-tmu";
233 reg = <0x0 0x1f80000 0x0 0x10000>;
234 interrupts = <0 23 0x4>;
235 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
236 fsl,tmu-calibration = <0x00000000 0x00000026
237 0x00000001 0x0000002d
238 0x00000002 0x00000032
239 0x00000003 0x00000039
240 0x00000004 0x0000003f
241 0x00000005 0x00000046
242 0x00000006 0x0000004d
243 0x00000007 0x00000054
244 0x00000008 0x0000005a
245 0x00000009 0x00000061
246 0x0000000a 0x0000006a
247 0x0000000b 0x00000071
248
249 0x00010000 0x00000025
250 0x00010001 0x0000002c
251 0x00010002 0x00000035
252 0x00010003 0x0000003d
253 0x00010004 0x00000045
254 0x00010005 0x0000004e
255 0x00010006 0x00000057
256 0x00010007 0x00000061
257 0x00010008 0x0000006b
258 0x00010009 0x00000076
259
260 0x00020000 0x00000029
261 0x00020001 0x00000033
262 0x00020002 0x0000003d
263 0x00020003 0x00000049
264 0x00020004 0x00000056
265 0x00020005 0x00000061
266 0x00020006 0x0000006d
267
268 0x00030000 0x00000021
269 0x00030001 0x0000002a
270 0x00030002 0x0000003c
271 0x00030003 0x0000004e>;
272 little-endian;
273 #thermal-sensor-cells = <1>;
274 };
275
276 thermal-zones {
277 cpu_thermal: cpu-thermal {
278 polling-delay-passive = <1000>;
279 polling-delay = <5000>;
280
281 thermal-sensors = <&tmu 4>;
282
283 trips {
284 cpu_alert: cpu-alert {
285 temperature = <75000>;
286 hysteresis = <2000>;
287 type = "passive";
288 };
289 cpu_crit: cpu-crit {
290 temperature = <85000>;
291 hysteresis = <2000>;
292 type = "critical";
293 };
294 };
295
296 cooling-maps {
297 map0 {
298 trip = <&cpu_alert>;
299 cooling-device =
300 <&cpu0 THERMAL_NO_LIMIT
301 THERMAL_NO_LIMIT>;
302 };
303 map1 {
304 trip = <&cpu_alert>;
305 cooling-device =
306 <&cpu2 THERMAL_NO_LIMIT
307 THERMAL_NO_LIMIT>;
308 };
309 map2 {
310 trip = <&cpu_alert>;
311 cooling-device =
312 <&cpu4 THERMAL_NO_LIMIT
313 THERMAL_NO_LIMIT>;
314 };
315 map3 {
316 trip = <&cpu_alert>;
317 cooling-device =
318 <&cpu6 THERMAL_NO_LIMIT
319 THERMAL_NO_LIMIT>;
320 };
321 };
322 };
323 };
324
225 serial0: serial@21c0500 { 325 serial0: serial@21c0500 {
226 compatible = "fsl,ns16550", "ns16550a"; 326 compatible = "fsl,ns16550", "ns16550a";
227 reg = <0x0 0x21c0500 0x0 0x100>; 327 reg = <0x0 0x21c0500 0x0 0x100>;
diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile
index d5f43a06b1c1..c8b8f803cf90 100644
--- a/arch/arm64/boot/dts/hisilicon/Makefile
+++ b/arch/arm64/boot/dts/hisilicon/Makefile
@@ -1,6 +1,7 @@
1dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb 1dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
2dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb 2dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
3dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb 3dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb
4dtb-$(CONFIG_ARCH_HISI) += hip07-d05.dtb
4 5
5always := $(dtb-y) 6always := $(dtb-y)
6subdir-y := $(dts-dirs) 7subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
index f54b28359607..7c4114a67753 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
+++ b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
@@ -41,18 +41,10 @@
41 status = "ok"; 41 status = "ok";
42}; 42};
43 43
44&sas0 {
45 status = "ok";
46};
47
48&sas1 { 44&sas1 {
49 status = "ok"; 45 status = "ok";
50}; 46};
51 47
52&sas2 {
53 status = "ok";
54};
55
56&usb_ohci { 48&usb_ohci {
57 status = "ok"; 49 status = "ok";
58}; 50};
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index b548763366dd..a049b64f2101 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -318,11 +318,17 @@
318 #size-cells = <2>; 318 #size-cells = <2>;
319 ranges; 319 ranges;
320 320
321 refclk: refclk {
322 compatible = "fixed-clock";
323 clock-frequency = <50000000>;
324 #clock-cells = <0>;
325 };
326
321 usb_ohci: ohci@a7030000 { 327 usb_ohci: ohci@a7030000 {
322 compatible = "generic-ohci"; 328 compatible = "generic-ohci";
323 reg = <0x0 0xa7030000 0x0 0x10000>; 329 reg = <0x0 0xa7030000 0x0 0x10000>;
324 interrupt-parent = <&mbigen_usb>; 330 interrupt-parent = <&mbigen_usb>;
325 interrupts = <64 4>; 331 interrupts = <640 4>;
326 dma-coherent; 332 dma-coherent;
327 status = "disabled"; 333 status = "disabled";
328 }; 334 };
@@ -331,7 +337,7 @@
331 compatible = "generic-ehci"; 337 compatible = "generic-ehci";
332 reg = <0x0 0xa7020000 0x0 0x10000>; 338 reg = <0x0 0xa7020000 0x0 0x10000>;
333 interrupt-parent = <&mbigen_usb>; 339 interrupt-parent = <&mbigen_usb>;
334 interrupts = <65 4>; 340 interrupts = <641 4>;
335 dma-coherent; 341 dma-coherent;
336 status = "disabled"; 342 status = "disabled";
337 }; 343 };
@@ -508,7 +514,7 @@
508 }; 514 };
509 }; 515 };
510 516
511 eth0: ethernet@4{ 517 eth0: ethernet-4{
512 compatible = "hisilicon,hns-nic-v2"; 518 compatible = "hisilicon,hns-nic-v2";
513 ae-handle = <&dsaf0>; 519 ae-handle = <&dsaf0>;
514 port-idx-in-ae = <4>; 520 port-idx-in-ae = <4>;
@@ -517,7 +523,7 @@
517 dma-coherent; 523 dma-coherent;
518 }; 524 };
519 525
520 eth1: ethernet@5{ 526 eth1: ethernet-5{
521 compatible = "hisilicon,hns-nic-v2"; 527 compatible = "hisilicon,hns-nic-v2";
522 ae-handle = <&dsaf0>; 528 ae-handle = <&dsaf0>;
523 port-idx-in-ae = <5>; 529 port-idx-in-ae = <5>;
@@ -526,7 +532,7 @@
526 dma-coherent; 532 dma-coherent;
527 }; 533 };
528 534
529 eth2: ethernet@0{ 535 eth2: ethernet-0{
530 compatible = "hisilicon,hns-nic-v2"; 536 compatible = "hisilicon,hns-nic-v2";
531 ae-handle = <&dsaf0>; 537 ae-handle = <&dsaf0>;
532 port-idx-in-ae = <0>; 538 port-idx-in-ae = <0>;
@@ -535,7 +541,7 @@
535 dma-coherent; 541 dma-coherent;
536 }; 542 };
537 543
538 eth3: ethernet@1{ 544 eth3: ethernet-1{
539 compatible = "hisilicon,hns-nic-v2"; 545 compatible = "hisilicon,hns-nic-v2";
540 ae-handle = <&dsaf0>; 546 ae-handle = <&dsaf0>;
541 port-idx-in-ae = <1>; 547 port-idx-in-ae = <1>;
@@ -552,6 +558,7 @@
552 ctrl-reset-reg = <0xa60>; 558 ctrl-reset-reg = <0xa60>;
553 ctrl-reset-sts-reg = <0x5a30>; 559 ctrl-reset-sts-reg = <0x5a30>;
554 ctrl-clock-ena-reg = <0x338>; 560 ctrl-clock-ena-reg = <0x338>;
561 clocks = <&refclk 0>;
555 queue-count = <16>; 562 queue-count = <16>;
556 phy-count = <8>; 563 phy-count = <8>;
557 dma-coherent; 564 dma-coherent;
@@ -590,10 +597,11 @@
590 reg = <0 0xa2000000 0 0x10000>; 597 reg = <0 0xa2000000 0 0x10000>;
591 sas-addr = [50 01 88 20 16 00 00 00]; 598 sas-addr = [50 01 88 20 16 00 00 00];
592 hisilicon,sas-syscon = <&pcie_subctl>; 599 hisilicon,sas-syscon = <&pcie_subctl>;
593 am-max-trans; 600 hip06-sas-v2-quirk-amt;
594 ctrl-reset-reg = <0xa18>; 601 ctrl-reset-reg = <0xa18>;
595 ctrl-reset-sts-reg = <0x5a0c>; 602 ctrl-reset-sts-reg = <0x5a0c>;
596 ctrl-clock-ena-reg = <0x318>; 603 ctrl-clock-ena-reg = <0x318>;
604 clocks = <&refclk 0>;
597 queue-count = <16>; 605 queue-count = <16>;
598 phy-count = <8>; 606 phy-count = <8>;
599 dma-coherent; 607 dma-coherent;
@@ -635,6 +643,7 @@
635 ctrl-reset-reg = <0xae0>; 643 ctrl-reset-reg = <0xae0>;
636 ctrl-reset-sts-reg = <0x5a70>; 644 ctrl-reset-sts-reg = <0x5a70>;
637 ctrl-clock-ena-reg = <0x3a8>; 645 ctrl-clock-ena-reg = <0x3a8>;
646 clocks = <&refclk 0>;
638 queue-count = <16>; 647 queue-count = <16>;
639 phy-count = <9>; 648 phy-count = <9>;
640 dma-coherent; 649 dma-coherent;
diff --git a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
new file mode 100644
index 000000000000..e05844230583
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
@@ -0,0 +1,66 @@
1/**
2 * dts file for Hisilicon D05 Development Board
3 *
4 * Copyright (C) 2016 Hisilicon Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation.
9 *
10 */
11
12/dts-v1/;
13
14#include "hip07.dtsi"
15
16/ {
17 model = "Hisilicon Hip07 D05 Development Board";
18 compatible = "hisilicon,hip07-d05";
19
20 /* the mem node will be updated by UEFI. */
21 memory@0 {
22 device_type = "memory";
23 reg = <0x0 0x00000000 0x0 0x40000000>;
24 numa-node-id = <0>;
25 };
26
27 distance-map {
28 compatible = "numa-distance-map-v1";
29 distance-matrix = <0 0 10>,
30 <0 1 15>,
31 <0 2 20>,
32 <0 3 25>,
33 <1 0 15>,
34 <1 1 10>,
35 <1 2 25>,
36 <1 3 30>,
37 <2 0 20>,
38 <2 1 25>,
39 <2 2 10>,
40 <2 3 15>,
41 <3 0 25>,
42 <3 1 30>,
43 <3 2 15>,
44 <3 3 10>;
45 };
46
47 aliases {
48 serial0 = &uart0;
49 };
50
51 chosen {
52 stdout-path = "serial0:115200n8";
53 };
54};
55
56&uart0 {
57 status = "ok";
58};
59
60&usb_ohci {
61 status = "ok";
62};
63
64&usb_ehci {
65 status = "ok";
66};
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
new file mode 100644
index 000000000000..5144eb1c179d
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -0,0 +1,1059 @@
1/**
2 * dts file for Hisilicon D05 Development Board
3 *
4 * Copyright (C) 2016 Hisilicon Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation.
9 *
10 */
11
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
14/ {
15 compatible = "hisilicon,hip07-d05";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 psci {
21 compatible = "arm,psci-0.2";
22 method = "smc";
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu-map {
30 cluster0 {
31 core0 {
32 cpu = <&cpu0>;
33 };
34 core1 {
35 cpu = <&cpu1>;
36 };
37 core2 {
38 cpu = <&cpu2>;
39 };
40 core3 {
41 cpu = <&cpu3>;
42 };
43 };
44
45 cluster1 {
46 core0 {
47 cpu = <&cpu4>;
48 };
49 core1 {
50 cpu = <&cpu5>;
51 };
52 core2 {
53 cpu = <&cpu6>;
54 };
55 core3 {
56 cpu = <&cpu7>;
57 };
58 };
59
60 cluster2 {
61 core0 {
62 cpu = <&cpu8>;
63 };
64 core1 {
65 cpu = <&cpu9>;
66 };
67 core2 {
68 cpu = <&cpu10>;
69 };
70 core3 {
71 cpu = <&cpu11>;
72 };
73 };
74
75 cluster3 {
76 core0 {
77 cpu = <&cpu12>;
78 };
79 core1 {
80 cpu = <&cpu13>;
81 };
82 core2 {
83 cpu = <&cpu14>;
84 };
85 core3 {
86 cpu = <&cpu15>;
87 };
88 };
89
90 cluster4 {
91 core0 {
92 cpu = <&cpu16>;
93 };
94 core1 {
95 cpu = <&cpu17>;
96 };
97 core2 {
98 cpu = <&cpu18>;
99 };
100 core3 {
101 cpu = <&cpu19>;
102 };
103 };
104
105 cluster5 {
106 core0 {
107 cpu = <&cpu20>;
108 };
109 core1 {
110 cpu = <&cpu21>;
111 };
112 core2 {
113 cpu = <&cpu22>;
114 };
115 core3 {
116 cpu = <&cpu23>;
117 };
118 };
119
120 cluster6 {
121 core0 {
122 cpu = <&cpu24>;
123 };
124 core1 {
125 cpu = <&cpu25>;
126 };
127 core2 {
128 cpu = <&cpu26>;
129 };
130 core3 {
131 cpu = <&cpu27>;
132 };
133 };
134
135 cluster7 {
136 core0 {
137 cpu = <&cpu28>;
138 };
139 core1 {
140 cpu = <&cpu29>;
141 };
142 core2 {
143 cpu = <&cpu30>;
144 };
145 core3 {
146 cpu = <&cpu31>;
147 };
148 };
149
150 cluster8 {
151 core0 {
152 cpu = <&cpu32>;
153 };
154 core1 {
155 cpu = <&cpu33>;
156 };
157 core2 {
158 cpu = <&cpu34>;
159 };
160 core3 {
161 cpu = <&cpu35>;
162 };
163 };
164
165 cluster9 {
166 core0 {
167 cpu = <&cpu36>;
168 };
169 core1 {
170 cpu = <&cpu37>;
171 };
172 core2 {
173 cpu = <&cpu38>;
174 };
175 core3 {
176 cpu = <&cpu39>;
177 };
178 };
179
180 cluster10 {
181 core0 {
182 cpu = <&cpu40>;
183 };
184 core1 {
185 cpu = <&cpu41>;
186 };
187 core2 {
188 cpu = <&cpu42>;
189 };
190 core3 {
191 cpu = <&cpu43>;
192 };
193 };
194
195 cluster11 {
196 core0 {
197 cpu = <&cpu44>;
198 };
199 core1 {
200 cpu = <&cpu45>;
201 };
202 core2 {
203 cpu = <&cpu46>;
204 };
205 core3 {
206 cpu = <&cpu47>;
207 };
208 };
209
210 cluster12 {
211 core0 {
212 cpu = <&cpu48>;
213 };
214 core1 {
215 cpu = <&cpu49>;
216 };
217 core2 {
218 cpu = <&cpu50>;
219 };
220 core3 {
221 cpu = <&cpu51>;
222 };
223 };
224
225 cluster13 {
226 core0 {
227 cpu = <&cpu52>;
228 };
229 core1 {
230 cpu = <&cpu53>;
231 };
232 core2 {
233 cpu = <&cpu54>;
234 };
235 core3 {
236 cpu = <&cpu55>;
237 };
238 };
239
240 cluster14 {
241 core0 {
242 cpu = <&cpu56>;
243 };
244 core1 {
245 cpu = <&cpu57>;
246 };
247 core2 {
248 cpu = <&cpu58>;
249 };
250 core3 {
251 cpu = <&cpu59>;
252 };
253 };
254
255 cluster15 {
256 core0 {
257 cpu = <&cpu60>;
258 };
259 core1 {
260 cpu = <&cpu61>;
261 };
262 core2 {
263 cpu = <&cpu62>;
264 };
265 core3 {
266 cpu = <&cpu63>;
267 };
268 };
269 };
270
271 cpu0: cpu@10000 {
272 device_type = "cpu";
273 compatible = "arm,cortex-a72", "arm,armv8";
274 reg = <0x10000>;
275 enable-method = "psci";
276 next-level-cache = <&cluster0_l2>;
277 numa-node-id = <0>;
278 };
279
280 cpu1: cpu@10001 {
281 device_type = "cpu";
282 compatible = "arm,cortex-a72", "arm,armv8";
283 reg = <0x10001>;
284 enable-method = "psci";
285 next-level-cache = <&cluster0_l2>;
286 numa-node-id = <0>;
287 };
288
289 cpu2: cpu@10002 {
290 device_type = "cpu";
291 compatible = "arm,cortex-a72", "arm,armv8";
292 reg = <0x10002>;
293 enable-method = "psci";
294 next-level-cache = <&cluster0_l2>;
295 numa-node-id = <0>;
296 };
297
298 cpu3: cpu@10003 {
299 device_type = "cpu";
300 compatible = "arm,cortex-a72", "arm,armv8";
301 reg = <0x10003>;
302 enable-method = "psci";
303 next-level-cache = <&cluster0_l2>;
304 numa-node-id = <0>;
305 };
306
307 cpu4: cpu@10100 {
308 device_type = "cpu";
309 compatible = "arm,cortex-a72", "arm,armv8";
310 reg = <0x10100>;
311 enable-method = "psci";
312 next-level-cache = <&cluster1_l2>;
313 numa-node-id = <0>;
314 };
315
316 cpu5: cpu@10101 {
317 device_type = "cpu";
318 compatible = "arm,cortex-a72", "arm,armv8";
319 reg = <0x10101>;
320 enable-method = "psci";
321 next-level-cache = <&cluster1_l2>;
322 numa-node-id = <0>;
323 };
324
325 cpu6: cpu@10102 {
326 device_type = "cpu";
327 compatible = "arm,cortex-a72", "arm,armv8";
328 reg = <0x10102>;
329 enable-method = "psci";
330 next-level-cache = <&cluster1_l2>;
331 numa-node-id = <0>;
332 };
333
334 cpu7: cpu@10103 {
335 device_type = "cpu";
336 compatible = "arm,cortex-a72", "arm,armv8";
337 reg = <0x10103>;
338 enable-method = "psci";
339 next-level-cache = <&cluster1_l2>;
340 numa-node-id = <0>;
341 };
342
343 cpu8: cpu@10200 {
344 device_type = "cpu";
345 compatible = "arm,cortex-a72", "arm,armv8";
346 reg = <0x10200>;
347 enable-method = "psci";
348 next-level-cache = <&cluster2_l2>;
349 numa-node-id = <0>;
350 };
351
352 cpu9: cpu@10201 {
353 device_type = "cpu";
354 compatible = "arm,cortex-a72", "arm,armv8";
355 reg = <0x10201>;
356 enable-method = "psci";
357 next-level-cache = <&cluster2_l2>;
358 numa-node-id = <0>;
359 };
360
361 cpu10: cpu@10202 {
362 device_type = "cpu";
363 compatible = "arm,cortex-a72", "arm,armv8";
364 reg = <0x10202>;
365 enable-method = "psci";
366 next-level-cache = <&cluster2_l2>;
367 numa-node-id = <0>;
368 };
369
370 cpu11: cpu@10203 {
371 device_type = "cpu";
372 compatible = "arm,cortex-a72", "arm,armv8";
373 reg = <0x10203>;
374 enable-method = "psci";
375 next-level-cache = <&cluster2_l2>;
376 numa-node-id = <0>;
377 };
378
379 cpu12: cpu@10300 {
380 device_type = "cpu";
381 compatible = "arm,cortex-a72", "arm,armv8";
382 reg = <0x10300>;
383 enable-method = "psci";
384 next-level-cache = <&cluster3_l2>;
385 numa-node-id = <0>;
386 };
387
388 cpu13: cpu@10301 {
389 device_type = "cpu";
390 compatible = "arm,cortex-a72", "arm,armv8";
391 reg = <0x10301>;
392 enable-method = "psci";
393 next-level-cache = <&cluster3_l2>;
394 numa-node-id = <0>;
395 };
396
397 cpu14: cpu@10302 {
398 device_type = "cpu";
399 compatible = "arm,cortex-a72", "arm,armv8";
400 reg = <0x10302>;
401 enable-method = "psci";
402 next-level-cache = <&cluster3_l2>;
403 numa-node-id = <0>;
404 };
405
406 cpu15: cpu@10303 {
407 device_type = "cpu";
408 compatible = "arm,cortex-a72", "arm,armv8";
409 reg = <0x10303>;
410 enable-method = "psci";
411 next-level-cache = <&cluster3_l2>;
412 numa-node-id = <0>;
413 };
414
415 cpu16: cpu@30000 {
416 device_type = "cpu";
417 compatible = "arm,cortex-a72", "arm,armv8";
418 reg = <0x30000>;
419 enable-method = "psci";
420 next-level-cache = <&cluster4_l2>;
421 numa-node-id = <1>;
422 };
423
424 cpu17: cpu@30001 {
425 device_type = "cpu";
426 compatible = "arm,cortex-a72", "arm,armv8";
427 reg = <0x30001>;
428 enable-method = "psci";
429 next-level-cache = <&cluster4_l2>;
430 numa-node-id = <1>;
431 };
432
433 cpu18: cpu@30002 {
434 device_type = "cpu";
435 compatible = "arm,cortex-a72", "arm,armv8";
436 reg = <0x30002>;
437 enable-method = "psci";
438 next-level-cache = <&cluster4_l2>;
439 numa-node-id = <1>;
440 };
441
442 cpu19: cpu@30003 {
443 device_type = "cpu";
444 compatible = "arm,cortex-a72", "arm,armv8";
445 reg = <0x30003>;
446 enable-method = "psci";
447 next-level-cache = <&cluster4_l2>;
448 numa-node-id = <1>;
449 };
450
451 cpu20: cpu@30100 {
452 device_type = "cpu";
453 compatible = "arm,cortex-a72", "arm,armv8";
454 reg = <0x30100>;
455 enable-method = "psci";
456 next-level-cache = <&cluster5_l2>;
457 numa-node-id = <1>;
458 };
459
460 cpu21: cpu@30101 {
461 device_type = "cpu";
462 compatible = "arm,cortex-a72", "arm,armv8";
463 reg = <0x30101>;
464 enable-method = "psci";
465 next-level-cache = <&cluster5_l2>;
466 numa-node-id = <1>;
467 };
468
469 cpu22: cpu@30102 {
470 device_type = "cpu";
471 compatible = "arm,cortex-a72", "arm,armv8";
472 reg = <0x30102>;
473 enable-method = "psci";
474 next-level-cache = <&cluster5_l2>;
475 numa-node-id = <1>;
476 };
477
478 cpu23: cpu@30103 {
479 device_type = "cpu";
480 compatible = "arm,cortex-a72", "arm,armv8";
481 reg = <0x30103>;
482 enable-method = "psci";
483 next-level-cache = <&cluster5_l2>;
484 numa-node-id = <1>;
485 };
486
487 cpu24: cpu@30200 {
488 device_type = "cpu";
489 compatible = "arm,cortex-a72", "arm,armv8";
490 reg = <0x30200>;
491 enable-method = "psci";
492 next-level-cache = <&cluster6_l2>;
493 numa-node-id = <1>;
494 };
495
496 cpu25: cpu@30201 {
497 device_type = "cpu";
498 compatible = "arm,cortex-a72", "arm,armv8";
499 reg = <0x30201>;
500 enable-method = "psci";
501 next-level-cache = <&cluster6_l2>;
502 numa-node-id = <1>;
503 };
504
505 cpu26: cpu@30202 {
506 device_type = "cpu";
507 compatible = "arm,cortex-a72", "arm,armv8";
508 reg = <0x30202>;
509 enable-method = "psci";
510 next-level-cache = <&cluster6_l2>;
511 numa-node-id = <1>;
512 };
513
514 cpu27: cpu@30203 {
515 device_type = "cpu";
516 compatible = "arm,cortex-a72", "arm,armv8";
517 reg = <0x30203>;
518 enable-method = "psci";
519 next-level-cache = <&cluster6_l2>;
520 numa-node-id = <1>;
521 };
522
523 cpu28: cpu@30300 {
524 device_type = "cpu";
525 compatible = "arm,cortex-a72", "arm,armv8";
526 reg = <0x30300>;
527 enable-method = "psci";
528 next-level-cache = <&cluster7_l2>;
529 numa-node-id = <1>;
530 };
531
532 cpu29: cpu@30301 {
533 device_type = "cpu";
534 compatible = "arm,cortex-a72", "arm,armv8";
535 reg = <0x30301>;
536 enable-method = "psci";
537 next-level-cache = <&cluster7_l2>;
538 numa-node-id = <1>;
539 };
540
541 cpu30: cpu@30302 {
542 device_type = "cpu";
543 compatible = "arm,cortex-a72", "arm,armv8";
544 reg = <0x30302>;
545 enable-method = "psci";
546 next-level-cache = <&cluster7_l2>;
547 numa-node-id = <1>;
548 };
549
550 cpu31: cpu@30303 {
551 device_type = "cpu";
552 compatible = "arm,cortex-a72", "arm,armv8";
553 reg = <0x30303>;
554 enable-method = "psci";
555 next-level-cache = <&cluster7_l2>;
556 numa-node-id = <1>;
557 };
558
559 cpu32: cpu@50000 {
560 device_type = "cpu";
561 compatible = "arm,cortex-a72", "arm,armv8";
562 reg = <0x50000>;
563 enable-method = "psci";
564 next-level-cache = <&cluster8_l2>;
565 numa-node-id = <2>;
566 };
567
568 cpu33: cpu@50001 {
569 device_type = "cpu";
570 compatible = "arm,cortex-a72", "arm,armv8";
571 reg = <0x50001>;
572 enable-method = "psci";
573 next-level-cache = <&cluster8_l2>;
574 numa-node-id = <2>;
575 };
576
577 cpu34: cpu@50002 {
578 device_type = "cpu";
579 compatible = "arm,cortex-a72", "arm,armv8";
580 reg = <0x50002>;
581 enable-method = "psci";
582 next-level-cache = <&cluster8_l2>;
583 numa-node-id = <2>;
584 };
585
586 cpu35: cpu@50003 {
587 device_type = "cpu";
588 compatible = "arm,cortex-a72", "arm,armv8";
589 reg = <0x50003>;
590 enable-method = "psci";
591 next-level-cache = <&cluster8_l2>;
592 numa-node-id = <2>;
593 };
594
595 cpu36: cpu@50100 {
596 device_type = "cpu";
597 compatible = "arm,cortex-a72", "arm,armv8";
598 reg = <0x50100>;
599 enable-method = "psci";
600 next-level-cache = <&cluster9_l2>;
601 numa-node-id = <2>;
602 };
603
604 cpu37: cpu@50101 {
605 device_type = "cpu";
606 compatible = "arm,cortex-a72", "arm,armv8";
607 reg = <0x50101>;
608 enable-method = "psci";
609 next-level-cache = <&cluster9_l2>;
610 numa-node-id = <2>;
611 };
612
613 cpu38: cpu@50102 {
614 device_type = "cpu";
615 compatible = "arm,cortex-a72", "arm,armv8";
616 reg = <0x50102>;
617 enable-method = "psci";
618 next-level-cache = <&cluster9_l2>;
619 numa-node-id = <2>;
620 };
621
622 cpu39: cpu@50103 {
623 device_type = "cpu";
624 compatible = "arm,cortex-a72", "arm,armv8";
625 reg = <0x50103>;
626 enable-method = "psci";
627 next-level-cache = <&cluster9_l2>;
628 numa-node-id = <2>;
629 };
630
631 cpu40: cpu@50200 {
632 device_type = "cpu";
633 compatible = "arm,cortex-a72", "arm,armv8";
634 reg = <0x50200>;
635 enable-method = "psci";
636 next-level-cache = <&cluster10_l2>;
637 numa-node-id = <2>;
638 };
639
640 cpu41: cpu@50201 {
641 device_type = "cpu";
642 compatible = "arm,cortex-a72", "arm,armv8";
643 reg = <0x50201>;
644 enable-method = "psci";
645 next-level-cache = <&cluster10_l2>;
646 numa-node-id = <2>;
647 };
648
649 cpu42: cpu@50202 {
650 device_type = "cpu";
651 compatible = "arm,cortex-a72", "arm,armv8";
652 reg = <0x50202>;
653 enable-method = "psci";
654 next-level-cache = <&cluster10_l2>;
655 numa-node-id = <2>;
656 };
657
658 cpu43: cpu@50203 {
659 device_type = "cpu";
660 compatible = "arm,cortex-a72", "arm,armv8";
661 reg = <0x50203>;
662 enable-method = "psci";
663 next-level-cache = <&cluster10_l2>;
664 numa-node-id = <2>;
665 };
666
667 cpu44: cpu@50300 {
668 device_type = "cpu";
669 compatible = "arm,cortex-a72", "arm,armv8";
670 reg = <0x50300>;
671 enable-method = "psci";
672 next-level-cache = <&cluster11_l2>;
673 numa-node-id = <2>;
674 };
675
676 cpu45: cpu@50301 {
677 device_type = "cpu";
678 compatible = "arm,cortex-a72", "arm,armv8";
679 reg = <0x50301>;
680 enable-method = "psci";
681 next-level-cache = <&cluster11_l2>;
682 numa-node-id = <2>;
683 };
684
685 cpu46: cpu@50302 {
686 device_type = "cpu";
687 compatible = "arm,cortex-a72", "arm,armv8";
688 reg = <0x50302>;
689 enable-method = "psci";
690 next-level-cache = <&cluster11_l2>;
691 numa-node-id = <2>;
692 };
693
694 cpu47: cpu@50303 {
695 device_type = "cpu";
696 compatible = "arm,cortex-a72", "arm,armv8";
697 reg = <0x50303>;
698 enable-method = "psci";
699 next-level-cache = <&cluster11_l2>;
700 numa-node-id = <2>;
701 };
702
703 cpu48: cpu@70000 {
704 device_type = "cpu";
705 compatible = "arm,cortex-a72", "arm,armv8";
706 reg = <0x70000>;
707 enable-method = "psci";
708 next-level-cache = <&cluster12_l2>;
709 numa-node-id = <3>;
710 };
711
712 cpu49: cpu@70001 {
713 device_type = "cpu";
714 compatible = "arm,cortex-a72", "arm,armv8";
715 reg = <0x70001>;
716 enable-method = "psci";
717 next-level-cache = <&cluster12_l2>;
718 numa-node-id = <3>;
719 };
720
721 cpu50: cpu@70002 {
722 device_type = "cpu";
723 compatible = "arm,cortex-a72", "arm,armv8";
724 reg = <0x70002>;
725 enable-method = "psci";
726 next-level-cache = <&cluster12_l2>;
727 numa-node-id = <3>;
728 };
729
730 cpu51: cpu@70003 {
731 device_type = "cpu";
732 compatible = "arm,cortex-a72", "arm,armv8";
733 reg = <0x70003>;
734 enable-method = "psci";
735 next-level-cache = <&cluster12_l2>;
736 numa-node-id = <3>;
737 };
738
739 cpu52: cpu@70100 {
740 device_type = "cpu";
741 compatible = "arm,cortex-a72", "arm,armv8";
742 reg = <0x70100>;
743 enable-method = "psci";
744 next-level-cache = <&cluster13_l2>;
745 numa-node-id = <3>;
746 };
747
748 cpu53: cpu@70101 {
749 device_type = "cpu";
750 compatible = "arm,cortex-a72", "arm,armv8";
751 reg = <0x70101>;
752 enable-method = "psci";
753 next-level-cache = <&cluster13_l2>;
754 numa-node-id = <3>;
755 };
756
757 cpu54: cpu@70102 {
758 device_type = "cpu";
759 compatible = "arm,cortex-a72", "arm,armv8";
760 reg = <0x70102>;
761 enable-method = "psci";
762 next-level-cache = <&cluster13_l2>;
763 numa-node-id = <3>;
764 };
765
766 cpu55: cpu@70103 {
767 device_type = "cpu";
768 compatible = "arm,cortex-a72", "arm,armv8";
769 reg = <0x70103>;
770 enable-method = "psci";
771 next-level-cache = <&cluster13_l2>;
772 numa-node-id = <3>;
773 };
774
775 cpu56: cpu@70200 {
776 device_type = "cpu";
777 compatible = "arm,cortex-a72", "arm,armv8";
778 reg = <0x70200>;
779 enable-method = "psci";
780 next-level-cache = <&cluster14_l2>;
781 numa-node-id = <3>;
782 };
783
784 cpu57: cpu@70201 {
785 device_type = "cpu";
786 compatible = "arm,cortex-a72", "arm,armv8";
787 reg = <0x70201>;
788 enable-method = "psci";
789 next-level-cache = <&cluster14_l2>;
790 numa-node-id = <3>;
791 };
792
793 cpu58: cpu@70202 {
794 device_type = "cpu";
795 compatible = "arm,cortex-a72", "arm,armv8";
796 reg = <0x70202>;
797 enable-method = "psci";
798 next-level-cache = <&cluster14_l2>;
799 numa-node-id = <3>;
800 };
801
802 cpu59: cpu@70203 {
803 device_type = "cpu";
804 compatible = "arm,cortex-a72", "arm,armv8";
805 reg = <0x70203>;
806 enable-method = "psci";
807 next-level-cache = <&cluster14_l2>;
808 numa-node-id = <3>;
809 };
810
811 cpu60: cpu@70300 {
812 device_type = "cpu";
813 compatible = "arm,cortex-a72", "arm,armv8";
814 reg = <0x70300>;
815 enable-method = "psci";
816 next-level-cache = <&cluster15_l2>;
817 numa-node-id = <3>;
818 };
819
820 cpu61: cpu@70301 {
821 device_type = "cpu";
822 compatible = "arm,cortex-a72", "arm,armv8";
823 reg = <0x70301>;
824 enable-method = "psci";
825 next-level-cache = <&cluster15_l2>;
826 numa-node-id = <3>;
827 };
828
829 cpu62: cpu@70302 {
830 device_type = "cpu";
831 compatible = "arm,cortex-a72", "arm,armv8";
832 reg = <0x70302>;
833 enable-method = "psci";
834 next-level-cache = <&cluster15_l2>;
835 numa-node-id = <3>;
836 };
837
838 cpu63: cpu@70303 {
839 device_type = "cpu";
840 compatible = "arm,cortex-a72", "arm,armv8";
841 reg = <0x70303>;
842 enable-method = "psci";
843 next-level-cache = <&cluster15_l2>;
844 numa-node-id = <3>;
845 };
846
847 cluster0_l2: l2-cache0 {
848 compatible = "cache";
849 };
850
851 cluster1_l2: l2-cache1 {
852 compatible = "cache";
853 };
854
855 cluster2_l2: l2-cache2 {
856 compatible = "cache";
857 };
858
859 cluster3_l2: l2-cache3 {
860 compatible = "cache";
861 };
862
863 cluster4_l2: l2-cache4 {
864 compatible = "cache";
865 };
866
867 cluster5_l2: l2-cache5 {
868 compatible = "cache";
869 };
870
871 cluster6_l2: l2-cache6 {
872 compatible = "cache";
873 };
874
875 cluster7_l2: l2-cache7 {
876 compatible = "cache";
877 };
878
879 cluster8_l2: l2-cache8 {
880 compatible = "cache";
881 };
882
883 cluster9_l2: l2-cache9 {
884 compatible = "cache";
885 };
886
887 cluster10_l2: l2-cache10 {
888 compatible = "cache";
889 };
890
891 cluster11_l2: l2-cache11 {
892 compatible = "cache";
893 };
894
895 cluster12_l2: l2-cache12 {
896 compatible = "cache";
897 };
898
899 cluster13_l2: l2-cache13 {
900 compatible = "cache";
901 };
902
903 cluster14_l2: l2-cache14 {
904 compatible = "cache";
905 };
906
907 cluster15_l2: l2-cache15 {
908 compatible = "cache";
909 };
910 };
911
912 gic: interrupt-controller@4d000000 {
913 compatible = "arm,gic-v3";
914 #interrupt-cells = <3>;
915 #address-cells = <2>;
916 #size-cells = <2>;
917 ranges;
918 interrupt-controller;
919 #redistributor-regions = <4>;
920 redistributor-stride = <0x0 0x40000>;
921 reg = <0x0 0x4d000000 0x0 0x10000>, /* GICD */
922 <0x0 0x4d100000 0x0 0x400000>, /* p0 GICR node 0 */
923 <0x0 0x6d100000 0x0 0x400000>, /* p0 GICR node 1 */
924 <0x400 0x4d100000 0x0 0x400000>, /* p1 GICR node 2 */
925 <0x400 0x6d100000 0x0 0x400000>, /* p1 GICR node 3 */
926 <0x0 0xfe000000 0x0 0x10000>, /* GICC */
927 <0x0 0xfe010000 0x0 0x10000>, /* GICH */
928 <0x0 0xfe020000 0x0 0x10000>; /* GICV */
929 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
930
931 p0_its_peri_a: interrupt-controller@4c000000 {
932 compatible = "arm,gic-v3-its";
933 msi-controller;
934 #msi-cells = <1>;
935 reg = <0x0 0x4c000000 0x0 0x40000>;
936 };
937
938 p0_its_peri_b: interrupt-controller@6c000000 {
939 compatible = "arm,gic-v3-its";
940 msi-controller;
941 #msi-cells = <1>;
942 reg = <0x0 0x6c000000 0x0 0x40000>;
943 };
944
945 p0_its_dsa_a: interrupt-controller@c6000000 {
946 compatible = "arm,gic-v3-its";
947 msi-controller;
948 #msi-cells = <1>;
949 reg = <0x0 0xc6000000 0x0 0x40000>;
950 };
951
952 p0_its_dsa_b: interrupt-controller@8,c6000000 {
953 compatible = "arm,gic-v3-its";
954 msi-controller;
955 #msi-cells = <1>;
956 reg = <0x8 0xc6000000 0x0 0x40000>;
957 };
958
959 p1_its_peri_a: interrupt-controller@400,4c000000 {
960 compatible = "arm,gic-v3-its";
961 msi-controller;
962 #msi-cells = <1>;
963 reg = <0x400 0x4c000000 0x0 0x40000>;
964 };
965
966 p1_its_peri_b: interrupt-controller@400,6c000000 {
967 compatible = "arm,gic-v3-its";
968 msi-controller;
969 #msi-cells = <1>;
970 reg = <0x400 0x6c000000 0x0 0x40000>;
971 };
972
973 p1_its_dsa_a: interrupt-controller@400,c6000000 {
974 compatible = "arm,gic-v3-its";
975 msi-controller;
976 #msi-cells = <1>;
977 reg = <0x400 0xc6000000 0x0 0x40000>;
978 };
979
980 p1_its_dsa_b: interrupt-controller@408,c6000000 {
981 compatible = "arm,gic-v3-its";
982 msi-controller;
983 #msi-cells = <1>;
984 reg = <0x408 0xc6000000 0x0 0x40000>;
985 };
986 };
987
988 timer {
989 compatible = "arm,armv8-timer";
990 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
991 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
992 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
993 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
994 };
995
996 pmu {
997 compatible = "arm,cortex-a72-pmu";
998 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
999 };
1000
1001 p0_mbigen_peri_b: interrupt-controller@60080000 {
1002 compatible = "hisilicon,mbigen-v2";
1003 reg = <0x0 0x60080000 0x0 0x10000>;
1004
1005 mbigen_uart: uart_intc {
1006 msi-parent = <&p0_its_peri_b 0x120c7>;
1007 interrupt-controller;
1008 #interrupt-cells = <2>;
1009 num-pins = <1>;
1010 };
1011 };
1012
1013 p0_mbigen_pcie_a: interrupt-controller@a0080000 {
1014 compatible = "hisilicon,mbigen-v2";
1015 reg = <0x0 0xa0080000 0x0 0x10000>;
1016
1017 mbigen_usb: intc_usb {
1018 msi-parent = <&p0_its_dsa_a 0x40080>;
1019 interrupt-controller;
1020 #interrupt-cells = <2>;
1021 num-pins = <2>;
1022 };
1023 };
1024
1025 soc {
1026 compatible = "simple-bus";
1027 #address-cells = <2>;
1028 #size-cells = <2>;
1029 ranges;
1030
1031 uart0: uart@602b0000 {
1032 compatible = "arm,sbsa-uart";
1033 reg = <0x0 0x602b0000 0x0 0x1000>;
1034 interrupt-parent = <&mbigen_uart>;
1035 interrupts = <807 4>;
1036 current-speed = <115200>;
1037 reg-io-width = <4>;
1038 status = "disabled";
1039 };
1040
1041 usb_ohci: ohci@a7030000 {
1042 compatible = "generic-ohci";
1043 reg = <0x0 0xa7030000 0x0 0x10000>;
1044 interrupt-parent = <&mbigen_usb>;
1045 interrupts = <640 4>;
1046 dma-coherent;
1047 status = "disabled";
1048 };
1049
1050 usb_ehci: ehci@a7020000 {
1051 compatible = "generic-ehci";
1052 reg = <0x0 0xa7020000 0x0 0x10000>;
1053 interrupt-parent = <&mbigen_usb>;
1054 interrupts = <641 4>;
1055 dma-coherent;
1056 status = "disabled";
1057 };
1058 };
1059};
diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
index cf3953124cef..1690883b931a 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-stb.dtb
4 4
5# Mvebu SoC Family 5# Mvebu SoC Family
6dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb 6dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb
7dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb
7dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb 8dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb
8dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb 9dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb
9 10
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index a59d36cd6caf..89de0a751093 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -56,7 +56,7 @@
56 stdout-path = "serial0:115200n8"; 56 stdout-path = "serial0:115200n8";
57 }; 57 };
58 58
59 memory { 59 memory@0 {
60 device_type = "memory"; 60 device_type = "memory";
61 reg = <0x00000000 0x00000000 0x00000000 0x20000000>; 61 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
62 }; 62 };
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
new file mode 100644
index 000000000000..83178d909fc2
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
@@ -0,0 +1,82 @@
1/*
2 * Device Tree file for Globalscale Marvell ESPRESSOBin Board
3 * Copyright (C) 2016 Marvell
4 *
5 * Romain Perier <romain.perier@free-electrons.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This file is distributed in the hope that it will be useful
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46/dts-v1/;
47
48#include "armada-372x.dtsi"
49
50/ {
51 model = "Globalscale Marvell ESPRESSOBin Board";
52 compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710";
53
54 chosen {
55 stdout-path = "serial0:115200n8";
56 };
57
58 memory@0 {
59 device_type = "memory";
60 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
61 };
62};
63
64/* J9 */
65&pcie0 {
66 status = "okay";
67};
68
69/* J6 */
70&sata {
71 status = "okay";
72};
73
74/* Exported on the micro USB connector J5 through an FTDI */
75&uart0 {
76 status = "okay";
77};
78
79/* J7 */
80&usb3 {
81 status = "okay";
82};
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index 3b8eb45bdc76..bab5c6ff5745 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -91,7 +91,7 @@
91 #size-cells = <2>; 91 #size-cells = <2>;
92 ranges; 92 ranges;
93 93
94 internal-regs { 94 internal-regs@d0000000 {
95 #address-cells = <1>; 95 #address-cells = <1>;
96 #size-cells = <1>; 96 #size-cells = <1>;
97 compatible = "simple-bus"; 97 compatible = "simple-bus";
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 7b6136182ad0..a749ba2edec4 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -71,7 +71,7 @@
71 interrupt-parent = <&gic>; 71 interrupt-parent = <&gic>;
72 ranges; 72 ranges;
73 73
74 config-space { 74 config-space@f0000000 {
75 #address-cells = <1>; 75 #address-cells = <1>;
76 #size-cells = <1>; 76 #size-cells = <1>;
77 compatible = "simple-bus"; 77 compatible = "simple-bus";
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index 93ec8fef82a1..05222f749a45 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -52,7 +52,7 @@
52 interrupt-parent = <&gic>; 52 interrupt-parent = <&gic>;
53 ranges; 53 ranges;
54 54
55 config-space { 55 config-space@f2000000 {
56 #address-cells = <1>; 56 #address-cells = <1>;
57 #size-cells = <1>; 57 #size-cells = <1>;
58 compatible = "simple-bus"; 58 compatible = "simple-bus";
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index ee8db0556791..638820ce977d 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -52,7 +52,7 @@
52 interrupt-parent = <&gic>; 52 interrupt-parent = <&gic>;
53 ranges; 53 ranges;
54 54
55 config-space { 55 config-space@f4000000 {
56 #address-cells = <1>; 56 #address-cells = <1>;
57 #size-cells = <1>; 57 #size-cells = <1>;
58 compatible = "simple-bus"; 58 compatible = "simple-bus";
diff --git a/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts b/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts
index 0d70d39fa8d2..fae6c6924705 100644
--- a/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts
+++ b/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts
@@ -54,7 +54,7 @@
54 stdout-path = "serial0:115200n8"; 54 stdout-path = "serial0:115200n8";
55 }; 55 };
56 56
57 memory { 57 memory@1000000 {
58 device_type = "memory"; 58 device_type = "memory";
59 /* the first 16MB is for firmwares' usage */ 59 /* the first 16MB is for firmwares' usage */
60 reg = <0 0x01000000 0 0x7f000000>; 60 reg = <0 0x01000000 0 0x7f000000>;
diff --git a/arch/arm64/boot/dts/marvell/berlin4ct-stb.dts b/arch/arm64/boot/dts/marvell/berlin4ct-stb.dts
index 348c37ecf069..d47edad13e68 100644
--- a/arch/arm64/boot/dts/marvell/berlin4ct-stb.dts
+++ b/arch/arm64/boot/dts/marvell/berlin4ct-stb.dts
@@ -54,7 +54,7 @@
54 stdout-path = "serial0:115200n8"; 54 stdout-path = "serial0:115200n8";
55 }; 55 };
56 56
57 memory { 57 memory@1000000 {
58 device_type = "memory"; 58 device_type = "memory";
59 /* the first 16MB is for firmwares' usage */ 59 /* the first 16MB is for firmwares' usage */
60 reg = <0 0x01000000 0 0x7f000000>; 60 reg = <0 0x01000000 0 0x7f000000>;
diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
index 85c23facb9fe..d6b800fd26d0 100644
--- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
+++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
@@ -142,7 +142,7 @@
142 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 142 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
143 }; 143 };
144 144
145 soc { 145 soc@f7000000 {
146 compatible = "simple-bus"; 146 compatible = "simple-bus";
147 #address-cells = <1>; 147 #address-cells = <1>;
148 #size-cells = <1>; 148 #size-cells = <1>;
diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile
index 0f7cdf3e05c1..18941458cb4d 100644
--- a/arch/arm64/boot/dts/nvidia/Makefile
+++ b/arch/arm64/boot/dts/nvidia/Makefile
@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb
3dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb 3dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb
4dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb 4dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb
5dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb 5dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb
6dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb
6 7
7always := $(dtb-y) 8always := $(dtb-y)
8clean-files := *.dtb 9clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
new file mode 100644
index 000000000000..0d3c0996d832
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
@@ -0,0 +1,8 @@
1/dts-v1/;
2
3#include "tegra186-p3310.dtsi"
4
5/ {
6 model = "NVIDIA Tegra186 P2771-0000 Development Board";
7 compatible = "nvidia,p2771-0000", "nvidia,tegra186";
8};
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
new file mode 100644
index 000000000000..1abe2eceb3d1
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -0,0 +1,64 @@
1#include "tegra186.dtsi"
2
3/ {
4 model = "NVIDIA Tegra186 P3310 Processor Module";
5 compatible = "nvidia,p3310", "nvidia,tegra186";
6
7 aliases {
8 serial0 = &uarta;
9 };
10
11 chosen {
12 bootargs = "earlycon console=ttyS0,115200n8";
13 stdout-path = "serial0:115200n8";
14 };
15
16 memory {
17 device_type = "memory";
18 reg = <0x0 0x80000000 0x2 0x00000000>;
19 };
20
21 serial@3100000 {
22 status = "okay";
23 };
24
25 hsp@3c00000 {
26 status = "okay";
27 };
28
29 cpus {
30 cpu@0 {
31 enable-method = "psci";
32 };
33
34 cpu@1 {
35 enable-method = "psci";
36 };
37
38 cpu@2 {
39 enable-method = "psci";
40 };
41
42 cpu@3 {
43 enable-method = "psci";
44 };
45
46 cpu@4 {
47 enable-method = "psci";
48 };
49
50 cpu@5 {
51 enable-method = "psci";
52 };
53 };
54
55 bpmp {
56 status = "okay";
57 };
58
59 psci {
60 compatible = "arm,psci-1.0";
61 status = "okay";
62 method = "smc";
63 };
64};
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
new file mode 100644
index 000000000000..a918e10240fd
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -0,0 +1,398 @@
1#include <dt-bindings/gpio/tegra186-gpio.h>
2#include <dt-bindings/interrupt-controller/arm-gic.h>
3
4/ {
5 compatible = "nvidia,tegra186";
6 interrupt-parent = <&gic>;
7 #address-cells = <2>;
8 #size-cells = <2>;
9
10 gpio: gpio@2200000 {
11 compatible = "nvidia,tegra186-gpio";
12 reg-names = "security", "gpio";
13 reg = <0x0 0x2200000 0x0 0x10000>,
14 <0x0 0x2210000 0x0 0x10000>;
15 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
16 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
17 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
18 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
19 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
20 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
21 #interrupt-cells = <2>;
22 interrupt-controller;
23 #gpio-cells = <2>;
24 gpio-controller;
25 };
26
27 uarta: serial@3100000 {
28 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
29 reg = <0x0 0x03100000 0x0 0x40>;
30 reg-shift = <2>;
31 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
32 clocks = <&bpmp 55>;
33 clock-names = "serial";
34 resets = <&bpmp 47>;
35 reset-names = "serial";
36 status = "disabled";
37 };
38
39 uartb: serial@3110000 {
40 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
41 reg = <0x0 0x03110000 0x0 0x40>;
42 reg-shift = <2>;
43 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
44 clocks = <&bpmp 56>;
45 clock-names = "serial";
46 resets = <&bpmp 48>;
47 reset-names = "serial";
48 status = "disabled";
49 };
50
51 uartd: serial@3130000 {
52 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
53 reg = <0x0 0x03130000 0x0 0x40>;
54 reg-shift = <2>;
55 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
56 clocks = <&bpmp 77>;
57 clock-names = "serial";
58 resets = <&bpmp 50>;
59 reset-names = "serial";
60 status = "disabled";
61 };
62
63 uarte: serial@3140000 {
64 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
65 reg = <0x0 0x03140000 0x0 0x40>;
66 reg-shift = <2>;
67 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
68 clocks = <&bpmp 194>;
69 clock-names = "serial";
70 resets = <&bpmp 132>;
71 reset-names = "serial";
72 status = "disabled";
73 };
74
75 uartf: serial@3150000 {
76 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
77 reg = <0x0 0x03150000 0x0 0x40>;
78 reg-shift = <2>;
79 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
80 clocks = <&bpmp 195>;
81 clock-names = "serial";
82 resets = <&bpmp 111>;
83 reset-names = "serial";
84 status = "disabled";
85 };
86
87 gen1_i2c: i2c@3160000 {
88 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
89 reg = <0x0 0x03160000 0x0 0x10000>;
90 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
91 #address-cells = <1>;
92 #size-cells = <0>;
93 clocks = <&bpmp 47>;
94 clock-names = "div-clk";
95 resets = <&bpmp 19>;
96 reset-names = "i2c";
97 status = "disabled";
98 };
99
100 cam_i2c: i2c@3180000 {
101 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
102 reg = <0x0 0x03180000 0x0 0x10000>;
103 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
104 #address-cells = <1>;
105 #size-cells = <0>;
106 clocks = <&bpmp 75>;
107 clock-names = "div-clk";
108 resets = <&bpmp 21>;
109 reset-names = "i2c";
110 status = "disabled";
111 };
112
113 /* shares pads with dpaux1 */
114 dp_aux_ch1_i2c: i2c@3190000 {
115 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
116 reg = <0x0 0x03190000 0x0 0x10000>;
117 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
118 #address-cells = <1>;
119 #size-cells = <0>;
120 clocks = <&bpmp 86>;
121 clock-names = "div-clk";
122 resets = <&bpmp 22>;
123 reset-names = "i2c";
124 status = "disabled";
125 };
126
127 /* controlled by BPMP, should not be enabled */
128 pwr_i2c: i2c@31a0000 {
129 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
130 reg = <0x0 0x031a0000 0x0 0x10000>;
131 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
132 #address-cells = <1>;
133 #size-cells = <0>;
134 clocks = <&bpmp 48>;
135 clock-names = "div-clk";
136 resets = <&bpmp 23>;
137 reset-names = "i2c";
138 status = "disabled";
139 };
140
141 /* shares pads with dpaux0 */
142 dp_aux_ch0_i2c: i2c@31b0000 {
143 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
144 reg = <0x0 0x031b0000 0x0 0x10000>;
145 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
146 #address-cells = <1>;
147 #size-cells = <0>;
148 clocks = <&bpmp 125>;
149 clock-names = "div-clk";
150 resets = <&bpmp 24>;
151 reset-names = "i2c";
152 status = "disabled";
153 };
154
155 gen7_i2c: i2c@31c0000 {
156 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
157 reg = <0x0 0x031c0000 0x0 0x10000>;
158 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
159 #address-cells = <1>;
160 #size-cells = <0>;
161 clocks = <&bpmp 182>;
162 clock-names = "div-clk";
163 resets = <&bpmp 81>;
164 reset-names = "i2c";
165 status = "disabled";
166 };
167
168 gen9_i2c: i2c@31e0000 {
169 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
170 reg = <0x0 0x031e0000 0x0 0x10000>;
171 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
172 #address-cells = <1>;
173 #size-cells = <0>;
174 clocks = <&bpmp 183>;
175 clock-names = "div-clk";
176 resets = <&bpmp 83>;
177 reset-names = "i2c";
178 status = "disabled";
179 };
180
181 sdmmc1: sdhci@3400000 {
182 compatible = "nvidia,tegra186-sdhci";
183 reg = <0x0 0x03400000 0x0 0x10000>;
184 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&bpmp 52>;
186 clock-names = "sdhci";
187 resets = <&bpmp 33>;
188 reset-names = "sdhci";
189 status = "disabled";
190 };
191
192 sdmmc2: sdhci@3420000 {
193 compatible = "nvidia,tegra186-sdhci";
194 reg = <0x0 0x03420000 0x0 0x10000>;
195 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&bpmp 53>;
197 clock-names = "sdhci";
198 resets = <&bpmp 34>;
199 reset-names = "sdhci";
200 status = "disabled";
201 };
202
203 sdmmc3: sdhci@3440000 {
204 compatible = "nvidia,tegra186-sdhci";
205 reg = <0x0 0x03440000 0x0 0x10000>;
206 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&bpmp 76>;
208 clock-names = "sdhci";
209 resets = <&bpmp 35>;
210 reset-names = "sdhci";
211 status = "disabled";
212 };
213
214 sdmmc4: sdhci@3460000 {
215 compatible = "nvidia,tegra186-sdhci";
216 reg = <0x0 0x03460000 0x0 0x10000>;
217 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&bpmp 54>;
219 clock-names = "sdhci";
220 resets = <&bpmp 36>;
221 reset-names = "sdhci";
222 status = "disabled";
223 };
224
225 gic: interrupt-controller@3881000 {
226 compatible = "arm,gic-400";
227 #interrupt-cells = <3>;
228 interrupt-controller;
229 reg = <0x0 0x03881000 0x0 0x1000>,
230 <0x0 0x03882000 0x0 0x2000>;
231 interrupts = <GIC_PPI 9
232 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
233 interrupt-parent = <&gic>;
234 };
235
236 hsp_top0: hsp@3c00000 {
237 compatible = "nvidia,tegra186-hsp";
238 reg = <0x0 0x03c00000 0x0 0xa0000>;
239 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
240 interrupt-names = "doorbell";
241 #mbox-cells = <2>;
242 status = "disabled";
243 };
244
245 gen2_i2c: i2c@c240000 {
246 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
247 reg = <0x0 0x0c240000 0x0 0x10000>;
248 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
249 #address-cells = <1>;
250 #size-cells = <0>;
251 clocks = <&bpmp 218>;
252 clock-names = "div-clk";
253 resets = <&bpmp 20>;
254 reset-names = "i2c";
255 status = "disabled";
256 };
257
258 gen8_i2c: i2c@c250000 {
259 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
260 reg = <0x0 0x0c250000 0x0 0x10000>;
261 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
262 #address-cells = <1>;
263 #size-cells = <0>;
264 clocks = <&bpmp 219>;
265 clock-names = "div-clk";
266 resets = <&bpmp 82>;
267 reset-names = "i2c";
268 status = "disabled";
269 };
270
271 uartc: serial@c280000 {
272 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
273 reg = <0x0 0x0c280000 0x0 0x40>;
274 reg-shift = <2>;
275 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&bpmp 215>;
277 clock-names = "serial";
278 resets = <&bpmp 49>;
279 reset-names = "serial";
280 status = "disabled";
281 };
282
283 uartg: serial@c290000 {
284 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
285 reg = <0x0 0x0c290000 0x0 0x40>;
286 reg-shift = <2>;
287 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&bpmp 216>;
289 clock-names = "serial";
290 resets = <&bpmp 112>;
291 reset-names = "serial";
292 status = "disabled";
293 };
294
295 gpio_aon: gpio@c2f0000 {
296 compatible = "nvidia,tegra186-gpio-aon";
297 reg-names = "security", "gpio";
298 reg = <0x0 0xc2f0000 0x0 0x1000>,
299 <0x0 0xc2f1000 0x0 0x1000>;
300 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
301 gpio-controller;
302 #gpio-cells = <2>;
303 interrupt-controller;
304 #interrupt-cells = <2>;
305 };
306
307 sysram@30000000 {
308 compatible = "nvidia,tegra186-sysram", "mmio-sram";
309 reg = <0x0 0x30000000 0x0 0x50000>;
310 #address-cells = <2>;
311 #size-cells = <2>;
312 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
313
314 cpu_bpmp_tx: shmem@4e000 {
315 compatible = "nvidia,tegra186-bpmp-shmem";
316 reg = <0x0 0x4e000 0x0 0x1000>;
317 label = "cpu-bpmp-tx";
318 pool;
319 };
320
321 cpu_bpmp_rx: shmem@4f000 {
322 compatible = "nvidia,tegra186-bpmp-shmem";
323 reg = <0x0 0x4f000 0x0 0x1000>;
324 label = "cpu-bpmp-rx";
325 pool;
326 };
327 };
328
329 cpus {
330 #address-cells = <1>;
331 #size-cells = <0>;
332
333 cpu@0 {
334 compatible = "nvidia,tegra186-denver", "arm,armv8";
335 device_type = "cpu";
336 reg = <0x000>;
337 };
338
339 cpu@1 {
340 compatible = "nvidia,tegra186-denver", "arm,armv8";
341 device_type = "cpu";
342 reg = <0x001>;
343 };
344
345 cpu@2 {
346 compatible = "arm,cortex-a57", "arm,armv8";
347 device_type = "cpu";
348 reg = <0x100>;
349 };
350
351 cpu@3 {
352 compatible = "arm,cortex-a57", "arm,armv8";
353 device_type = "cpu";
354 reg = <0x101>;
355 };
356
357 cpu@4 {
358 compatible = "arm,cortex-a57", "arm,armv8";
359 device_type = "cpu";
360 reg = <0x102>;
361 };
362
363 cpu@5 {
364 compatible = "arm,cortex-a57", "arm,armv8";
365 device_type = "cpu";
366 reg = <0x103>;
367 };
368 };
369
370 bpmp: bpmp {
371 compatible = "nvidia,tegra186-bpmp";
372 mboxes = <&hsp_top0 0 19>;
373 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
374 #clock-cells = <1>;
375 #reset-cells = <1>;
376
377 bpmp_i2c: i2c {
378 compatible = "nvidia,tegra186-bpmp-i2c";
379 nvidia,bpmp-bus-id = <5>;
380 #address-cells = <1>;
381 #size-cells = <0>;
382 status = "disabled";
383 };
384 };
385
386 timer {
387 compatible = "arm,armv8-timer";
388 interrupts = <GIC_PPI 13
389 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
390 <GIC_PPI 14
391 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
392 <GIC_PPI 11
393 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
394 <GIC_PPI 10
395 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
396 interrupt-parent = <&gic>;
397 };
398};
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 5dd05de5619b..cc0f02d9dd02 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -1,6 +1,9 @@
1dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb msm8916-mtp.dtb 1dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
2dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
3dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb 2dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
3dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
4dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
5dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
6dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
4 7
5always := $(dtb-y) 8always := $(dtb-y)
6subdir-y := $(dts-dirs) 9subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index bb062b547110..08bd5ebafb4e 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -15,6 +15,7 @@
15#include "pm8916.dtsi" 15#include "pm8916.dtsi"
16#include "apq8016-sbc-soc-pins.dtsi" 16#include "apq8016-sbc-soc-pins.dtsi"
17#include "apq8016-sbc-pmic-pins.dtsi" 17#include "apq8016-sbc-pmic-pins.dtsi"
18#include <dt-bindings/sound/apq8016-lpass.h>
18 19
19/ { 20/ {
20 aliases { 21 aliases {
@@ -251,6 +252,60 @@
251 vddio-supply = <&pm8916_l6>; 252 vddio-supply = <&pm8916_l6>;
252 }; 253 };
253 }; 254 };
255
256 lpass_codec: codec{
257 status = "okay";
258 };
259
260 /*
261 Internal Codec
262 playback - Primary MI2S
263 capture - Ter MI2S
264
265 External Primary:
266 playback - secondary MI2S
267 capture - Quat MI2S
268
269 External Secondary:
270 playback - Quat MI2S
271 capture - Quat MI2S
272
273 */
274
275 sound: sound {
276 compatible = "qcom,apq8016-sbc-sndcard";
277 reg = <0x07702000 0x4>, <0x07702004 0x4>;
278 reg-names = "mic-iomux", "spkr-iomux";
279
280 status = "okay";
281 pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>;
282 pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>;
283 pinctrl-names = "default", "sleep";
284 qcom,model = "DB410c";
285 qcom,audio-routing =
286 "AMIC2", "MIC BIAS Internal2",
287 "AMIC3", "MIC BIAS External1";
288
289 internal-codec-playback-dai-link@0 { /* I2S - Internal codec */
290 link-name = "WCD";
291 cpu { /* PRIMARY */
292 sound-dai = <&lpass MI2S_PRIMARY>;
293 };
294 codec {
295 sound-dai = <&lpass_codec 0>, <&wcd_codec 0>;
296 };
297 };
298
299 internal-codec-capture-dai-link@0 { /* I2S - Internal codec */
300 link-name = "WCD-Capture";
301 cpu { /* PRIMARY */
302 sound-dai = <&lpass MI2S_TERTIARY>;
303 };
304 codec {
305 sound-dai = <&lpass_codec 1>, <&wcd_codec 1>;
306 };
307 };
308 };
254 }; 309 };
255 310
256 usb2513 { 311 usb2513 {
@@ -278,6 +333,12 @@
278 }; 333 };
279}; 334};
280 335
336&wcd_codec {
337 status = "okay";
338 clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>;
339 clock-names = "mclk";
340};
341
281&smd_rpm_regulators { 342&smd_rpm_regulators {
282 vdd_l1_l2_l3-supply = <&pm8916_s3>; 343 vdd_l1_l2_l3-supply = <&pm8916_s3>;
283 vdd_l5-supply = <&pm8916_s3>; 344 vdd_l5-supply = <&pm8916_s3>;
@@ -308,8 +369,8 @@
308 }; 369 };
309 370
310 l2 { 371 l2 {
311 regulator-min-microvolt = <375000>; 372 regulator-min-microvolt = <1200000>;
312 regulator-max-microvolt = <1525000>; 373 regulator-max-microvolt = <1200000>;
313 }; 374 };
314 375
315 l3 { 376 l3 {
@@ -328,8 +389,8 @@
328 }; 389 };
329 390
330 l6 { 391 l6 {
331 regulator-min-microvolt = <1750000>; 392 regulator-min-microvolt = <1800000>;
332 regulator-max-microvolt = <3337000>; 393 regulator-max-microvolt = <1800000>;
333 }; 394 };
334 395
335 l7 { 396 l7 {
@@ -388,8 +449,8 @@
388 }; 449 };
389 450
390 l17 { 451 l17 {
391 regulator-min-microvolt = <1750000>; 452 regulator-min-microvolt = <3300000>;
392 regulator-max-microvolt = <3337000>; 453 regulator-max-microvolt = <3300000>;
393 }; 454 };
394 455
395 l18 { 456 l18 {
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
new file mode 100644
index 000000000000..0de95171d6d0
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
@@ -0,0 +1,15 @@
1
2#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
3&pm8994_gpios {
4
5 pinctrl-names = "default";
6 pinctrl-0 = <&ls_exp_gpio_f>;
7
8 ls_exp_gpio_f: pm8916_mpp4 {
9 pinconf {
10 pins = "gpio5";
11 output-low;
12 power-source = <2>; // PM8994_GPIO_S4, 1.8V
13 };
14 };
15};
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index afb218cffc60..422959b87d12 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -12,7 +12,9 @@
12 */ 12 */
13 13
14#include "msm8996.dtsi" 14#include "msm8996.dtsi"
15#include "pm8994.dtsi"
15#include "apq8096-db820c-pins.dtsi" 16#include "apq8096-db820c-pins.dtsi"
17#include "apq8096-db820c-pmic-pins.dtsi"
16 18
17/ { 19/ {
18 aliases { 20 aliases {
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 466ca5705c99..f8ff327667c5 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -77,7 +77,7 @@
77 no-map; 77 no-map;
78 }; 78 };
79 79
80 mpss@86800000 { 80 mpss_mem: mpss@86800000 {
81 reg = <0x0 0x86800000 0x0 0x2b00000>; 81 reg = <0x0 0x86800000 0x0 0x2b00000>;
82 no-map; 82 no-map;
83 }; 83 };
@@ -504,6 +504,15 @@
504 reg-names = "lpass-lpaif"; 504 reg-names = "lpass-lpaif";
505 }; 505 };
506 506
507 lpass_codec: codec{
508 compatible = "qcom,msm8916-wcd-digital-codec";
509 reg = <0x0771c000 0x400>;
510 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
511 <&gcc GCC_CODEC_DIGCODEC_CLK>;
512 clock-names = "ahbix-clk", "mclk";
513 #sound-dai-cells = <1>;
514 };
515
507 sdhc_1: sdhci@07824000 { 516 sdhc_1: sdhci@07824000 {
508 compatible = "qcom,sdhci-msm-v4"; 517 compatible = "qcom,sdhci-msm-v4";
509 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 518 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
@@ -512,8 +521,10 @@
512 interrupts = <0 123 0>, <0 138 0>; 521 interrupts = <0 123 0>, <0 138 0>;
513 interrupt-names = "hc_irq", "pwr_irq"; 522 interrupt-names = "hc_irq", "pwr_irq";
514 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 523 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
515 <&gcc GCC_SDCC1_AHB_CLK>; 524 <&gcc GCC_SDCC1_AHB_CLK>,
516 clock-names = "core", "iface"; 525 <&xo_board>;
526 clock-names = "core", "iface", "xo";
527 mmc-ddr-1_8v;
517 bus-width = <8>; 528 bus-width = <8>;
518 non-removable; 529 non-removable;
519 status = "disabled"; 530 status = "disabled";
@@ -527,8 +538,9 @@
527 interrupts = <0 125 0>, <0 221 0>; 538 interrupts = <0 125 0>, <0 221 0>;
528 interrupt-names = "hc_irq", "pwr_irq"; 539 interrupt-names = "hc_irq", "pwr_irq";
529 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 540 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
530 <&gcc GCC_SDCC2_AHB_CLK>; 541 <&gcc GCC_SDCC2_AHB_CLK>,
531 clock-names = "core", "iface"; 542 <&xo_board>;
543 clock-names = "core", "iface", "xo";
532 bus-width = <4>; 544 bus-width = <4>;
533 status = "disabled"; 545 status = "disabled";
534 }; 546 };
@@ -801,6 +813,49 @@
801 clock-names = "iface_clk"; 813 clock-names = "iface_clk";
802 }; 814 };
803 }; 815 };
816
817
818 hexagon@4080000 {
819 compatible = "qcom,q6v5-pil";
820 reg = <0x04080000 0x100>,
821 <0x04020000 0x040>;
822
823 reg-names = "qdsp6", "rmb";
824
825 interrupts-extended = <&intc 0 24 1>,
826 <&hexagon_smp2p_in 0 0>,
827 <&hexagon_smp2p_in 1 0>,
828 <&hexagon_smp2p_in 2 0>,
829 <&hexagon_smp2p_in 3 0>;
830 interrupt-names = "wdog", "fatal", "ready",
831 "handover", "stop-ack";
832
833 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
834 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
835 <&gcc GCC_BOOT_ROM_AHB_CLK>;
836 clock-names = "iface", "bus", "mem";
837
838 qcom,smem-states = <&hexagon_smp2p_out 0>;
839 qcom,smem-state-names = "stop";
840
841 resets = <&scm 0>;
842 reset-names = "mss_restart";
843
844 mx-supply = <&pm8916_l3>;
845 pll-supply = <&pm8916_l7>;
846
847 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
848
849 status = "disabled";
850
851 mba {
852 memory-region = <&mba_mem>;
853 };
854
855 mpss {
856 memory-region = <&mpss_mem>;
857 };
858 };
804 }; 859 };
805 860
806 smd { 861 smd {
@@ -848,6 +903,14 @@
848 }; 903 };
849 }; 904 };
850 }; 905 };
906
907 hexagon {
908 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
909
910 qcom,smd-edge = <0>;
911 qcom,ipc = <&apcs 8 12>;
912 qcom,remote-pid = <1>;
913 };
851 }; 914 };
852 915
853 hexagon-smp2p { 916 hexagon-smp2p {
diff --git a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts
new file mode 100644
index 000000000000..454213391671
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts
@@ -0,0 +1,41 @@
1/* Copyright (c) 2015, LGE Inc. All rights reserved.
2 * Copyright (c) 2016, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/dts-v1/;
15
16#include "msm8992.dtsi"
17
18/ {
19 model = "LG Nexus 5X";
20 compatible = "lg,bullhead", "qcom,msm8992";
21 /* required for bootloader to select correct board */
22 qcom,board-id = <0xb64 0>;
23 qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
24
25 aliases {
26 serial0 = &blsp1_uart2;
27 };
28
29 chosen {
30 stdout-path = "serial0:115200n8";
31 };
32
33 soc {
34 serial@f991e000 {
35 status = "okay";
36 pinctrl-names = "default", "sleep";
37 pinctrl-0 = <&blsp1_uart2_default>;
38 pinctrl-1 = <&blsp1_uart2_sleep>;
39 };
40 };
41};
diff --git a/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
new file mode 100644
index 000000000000..d2a26f0f8d73
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
@@ -0,0 +1,38 @@
1/*
2 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14&msmgpio {
15 blsp1_uart2_default: blsp1_uart2_default {
16 pinmux {
17 function = "blsp_uart2";
18 pins = "gpio4", "gpio5";
19 };
20 pinconf {
21 pins = "gpio4", "gpio5";
22 drive-strength = <16>;
23 bias-disable;
24 };
25 };
26
27 blsp1_uart2_sleep: blsp1_uart2_sleep {
28 pinmux {
29 function = "gpio";
30 pins = "gpio4", "gpio5";
31 };
32 pinconf {
33 pins = "gpio4", "gpio5";
34 drive-strength = <2>;
35 bias-pull-down;
36 };
37 };
38};
diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi
new file mode 100644
index 000000000000..44b2d37d8c4b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi
@@ -0,0 +1,184 @@
1/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/clock/qcom,gcc-msm8994.h>
15
16/ {
17 model = "Qualcomm Technologies, Inc. MSM 8992";
18 compatible = "qcom,msm8992";
19 // msm-id needed by bootloader for selecting correct blob
20 qcom,msm-id = <251 0>, <252 0>;
21 interrupt-parent = <&intc>;
22
23 #address-cells = <2>;
24 #size-cells = <2>;
25
26 chosen { };
27
28 cpus {
29 #address-cells = <2>;
30 #size-cells = <0>;
31 cpu-map {
32 cluster0 {
33 core0 {
34 cpu = <&CPU0>;
35 };
36 };
37 };
38
39 CPU0: cpu@0 {
40 device_type = "cpu";
41 compatible = "arm,cortex-a53", "arm,armv8";
42 reg = <0x0 0x0>;
43 next-level-cache = <&L2_0>;
44 L2_0: l2-cache {
45 compatible = "cache";
46 cache-level = <2>;
47 };
48 };
49 };
50
51 timer {
52 compatible = "arm,armv8-timer";
53 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
54 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
55 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
56 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
57 };
58
59 xo_board: xo_board {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <19200000>;
63 };
64
65 sleep_clk: sleep_clk {
66 compatible = "fixed-clock";
67 #clock-cells = <0>;
68 clock-frequency = <32768>;
69 };
70
71 soc {
72 #address-cells = <1>;
73 #size-cells = <1>;
74 ranges = <0 0 0 0xffffffff>;
75 compatible = "simple-bus";
76
77 intc: interrupt-controller@f9000000 {
78 compatible = "qcom,msm-qgic2";
79 interrupt-controller;
80 #interrupt-cells = <3>;
81 reg = <0xf9000000 0x1000>,
82 <0xf9002000 0x1000>;
83 };
84
85 timer@f9020000 {
86 #address-cells = <1>;
87 #size-cells = <1>;
88 ranges;
89 compatible = "arm,armv7-timer-mem";
90 reg = <0xf9020000 0x1000>;
91
92 frame@f9021000 {
93 frame-number = <0>;
94 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
96 reg = <0xf9021000 0x1000>,
97 <0xf9022000 0x1000>;
98 };
99
100 frame@f9023000 {
101 frame-number = <1>;
102 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
103 reg = <0xf9023000 0x1000>;
104 status = "disabled";
105 };
106
107 frame@f9024000 {
108 frame-number = <2>;
109 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
110 reg = <0xf9024000 0x1000>;
111 status = "disabled";
112 };
113
114 frame@f9025000 {
115 frame-number = <3>;
116 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
117 reg = <0xf9025000 0x1000>;
118 status = "disabled";
119 };
120
121 frame@f9026000 {
122 frame-number = <4>;
123 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
124 reg = <0xf9026000 0x1000>;
125 status = "disabled";
126 };
127
128 frame@f9027000 {
129 frame-number = <5>;
130 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
131 reg = <0xf9027000 0x1000>;
132 status = "disabled";
133 };
134
135 frame@f9028000 {
136 frame-number = <6>;
137 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
138 reg = <0xf9028000 0x1000>;
139 status = "disabled";
140 };
141 };
142
143 restart@fc4ab000 {
144 compatible = "qcom,pshold";
145 reg = <0xfc4ab000 0x4>;
146 };
147
148 msmgpio: pinctrl@fd510000 {
149 compatible = "qcom,msm8994-pinctrl";
150 reg = <0xfd510000 0x4000>;
151 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
152 gpio-controller;
153 #gpio-cells = <2>;
154 interrupt-controller;
155 #interrupt-cells = <2>;
156 };
157
158 blsp1_uart2: serial@f991e000 {
159 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
160 reg = <0xf991e000 0x1000>;
161 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>;
162 status = "disabled";
163 clock-names = "core", "iface";
164 clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
165 <&clock_gcc GCC_BLSP1_AHB_CLK>;
166 };
167
168 clock_gcc: clock-controller@fc400000 {
169 compatible = "qcom,gcc-msm8994";
170 #clock-cells = <1>;
171 #reset-cells = <1>;
172 #power-domain-cells = <1>;
173 reg = <0xfc400000 0x2000>;
174 };
175 };
176
177 memory {
178 device_type = "memory";
179 reg = <0 0 0 0>; // bootloader will update
180 };
181};
182
183
184#include "msm8992-pins.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts
new file mode 100644
index 000000000000..dfa08f513dc4
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts
@@ -0,0 +1,40 @@
1/* Copyright (c) 2015, Huawei Inc. All rights reserved.
2 * Copyright (c) 2016, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/dts-v1/;
15
16#include "msm8994.dtsi"
17
18/ {
19 model = "Huawei Nexus 6P";
20 compatible = "huawei,angler", "qcom,msm8994";
21 /* required for bootloader to select correct board */
22 qcom,board-id = <8026 0>;
23
24 aliases {
25 serial0 = &blsp1_uart2;
26 };
27
28 chosen {
29 stdout-path = "serial0:115200n8";
30 };
31
32 soc {
33 serial@f991e000 {
34 status = "okay";
35 pinctrl-names = "default", "sleep";
36 pinctrl-0 = <&blsp1_uart2_default>;
37 pinctrl-1 = <&blsp1_uart2_sleep>;
38 };
39 };
40};
diff --git a/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
new file mode 100644
index 000000000000..0e4eea0df25d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
@@ -0,0 +1,38 @@
1/*
2 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14&msmgpio {
15 blsp1_uart2_default: blsp1_uart2_default {
16 pinmux {
17 function = "blsp_uart2";
18 pins = "gpio4", "gpio5";
19 };
20 pinconf {
21 pins = "gpio4", "gpio5";
22 drive-strength = <16>;
23 bias-disable;
24 };
25 };
26
27 blsp1_uart2_sleep: blsp1_uart2_sleep {
28 pinmux {
29 function = "gpio";
30 pins = "gpio4", "gpio5";
31 };
32 pinconf {
33 pins = "gpio4", "gpio5";
34 drive-strength = <2>;
35 bias-pull-down;
36 };
37 };
38};
diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
new file mode 100644
index 000000000000..f33c41d01c86
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
@@ -0,0 +1,216 @@
1/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/clock/qcom,gcc-msm8994.h>
15
16/ {
17 model = "Qualcomm Technologies, Inc. MSM 8994";
18 compatible = "qcom,msm8994";
19 // msm-id and pmic-id are required by bootloader for
20 // proper selection of dt blob
21 qcom,msm-id = <207 0x20000>;
22 qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
23 interrupt-parent = <&intc>;
24
25 #address-cells = <2>;
26 #size-cells = <2>;
27
28 chosen { };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33 cpu-map {
34 cluster0 {
35 core0 {
36 cpu = <&CPU0>;
37 };
38 };
39 };
40
41 CPU0: cpu@0 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a53", "arm,armv8";
44 reg = <0x0>;
45 next-level-cache = <&L2_0>;
46 L2_0: l2-cache {
47 compatible = "cache";
48 cache-level = <2>;
49 };
50 };
51 };
52
53 timer {
54 compatible = "arm,armv8-timer";
55 interrupts = <1 2 0xff08>,
56 <1 3 0xff08>,
57 <1 4 0xff08>,
58 <1 1 0xff08>;
59 };
60
61 soc: soc {
62
63 #address-cells = <1>;
64 #size-cells = <1>;
65 ranges = <0 0 0 0xffffffff>;
66 compatible = "simple-bus";
67
68 intc: interrupt-controller@f9000000 {
69 compatible = "qcom,msm-qgic2";
70 interrupt-controller;
71 #interrupt-cells = <3>;
72 reg = <0xf9000000 0x1000>,
73 <0xf9002000 0x1000>;
74 };
75
76 timer@f9020000 {
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges;
80 compatible = "arm,armv7-timer-mem";
81 reg = <0xf9020000 0x1000>;
82
83 frame@f9021000 {
84 frame-number = <0>;
85 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
87 reg = <0xf9021000 0x1000>,
88 <0xf9022000 0x1000>;
89 };
90
91 frame@f9023000 {
92 frame-number = <1>;
93 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
94 reg = <0xf9023000 0x1000>;
95 status = "disabled";
96 };
97
98 frame@f9024000 {
99 frame-number = <2>;
100 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
101 reg = <0xf9024000 0x1000>;
102 status = "disabled";
103 };
104
105 frame@f9025000 {
106 frame-number = <3>;
107 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
108 reg = <0xf9025000 0x1000>;
109 status = "disabled";
110 };
111
112 frame@f9026000 {
113 frame-number = <4>;
114 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
115 reg = <0xf9026000 0x1000>;
116 status = "disabled";
117 };
118
119 frame@f9027000 {
120 frame-number = <5>;
121 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
122 reg = <0xf9027000 0x1000>;
123 status = "disabled";
124 };
125
126 frame@f9028000 {
127 frame-number = <6>;
128 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
129 reg = <0xf9028000 0x1000>;
130 status = "disabled";
131 };
132 };
133
134 restart@fc4ab000 {
135 compatible = "qcom,pshold";
136 reg = <0xfc4ab000 0x4>;
137 };
138
139 msmgpio: pinctrl@fd510000 {
140 compatible = "qcom,msm8994-pinctrl";
141 reg = <0xfd510000 0x4000>;
142 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
143 gpio-controller;
144 #gpio-cells = <2>;
145 interrupt-controller;
146 #interrupt-cells = <2>;
147 };
148
149 blsp1_uart2: serial@f991e000 {
150 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
151 reg = <0xf991e000 0x1000>;
152 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
153 status = "disabled";
154 clock-names = "core", "iface";
155 clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
156 <&clock_gcc GCC_BLSP1_AHB_CLK>;
157 };
158
159 tcsr_mutex_regs: syscon@fd484000 {
160 compatible = "syscon";
161 reg = <0xfd484000 0x2000>;
162 };
163
164 clock_gcc: clock-controller@fc400000 {
165 compatible = "qcom,gcc-msm8994";
166 #clock-cells = <1>;
167 #reset-cells = <1>;
168 #power-domain-cells = <1>;
169 reg = <0xfc400000 0x2000>;
170 };
171 };
172
173 memory {
174 device_type = "memory";
175 // We expect the bootloader to fill in the reg
176 reg = <0 0 0 0>;
177 };
178
179 xo_board: xo_board {
180 compatible = "fixed-clock";
181 #clock-cells = <0>;
182 clock-frequency = <19200000>;
183 };
184
185 sleep_clk: sleep_clk {
186 compatible = "fixed-clock";
187 #clock-cells = <0>;
188 clock-frequency = <32768>;
189 };
190
191 reserved-memory {
192 #address-cells = <2>;
193 #size-cells = <2>;
194 ranges;
195
196 smem_mem: smem_region@6a00000 {
197 reg = <0x0 0x6a00000 0x0 0x200000>;
198 no-map;
199 };
200 };
201
202 tcsr_mutex: hwlock {
203 compatible = "qcom,tcsr-mutex";
204 syscon = <&tcsr_mutex_regs 0 0x80>;
205 #hwlock-cells = <1>;
206 };
207
208 qcom,smem@6a00000 {
209 compatible = "qcom,smem";
210 memory-region = <&smem_mem>;
211 hwlocks = <&tcsr_mutex 3>;
212 };
213};
214
215
216#include "msm8994-pins.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 338f82a7fdc7..9d1d7ad9b075 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -30,6 +30,42 @@
30 reg = <0 0 0 0>; 30 reg = <0 0 0 0>;
31 }; 31 };
32 32
33 reserved-memory {
34 #address-cells = <2>;
35 #size-cells = <2>;
36 ranges;
37
38 mba_region: mba@91500000 {
39 reg = <0x0 0x91500000 0x0 0x200000>;
40 no-map;
41 };
42
43 slpi_region: slpi@90b00000 {
44 reg = <0x0 0x90b00000 0x0 0xa00000>;
45 no-map;
46 };
47
48 venus_region: venus@90400000 {
49 reg = <0x0 0x90400000 0x0 0x700000>;
50 no-map;
51 };
52
53 adsp_region: adsp@8ea00000 {
54 reg = <0x0 0x8ea00000 0x0 0x1a00000>;
55 no-map;
56 };
57
58 mpss_region: mpss@88800000 {
59 reg = <0x0 0x88800000 0x0 0x6200000>;
60 no-map;
61 };
62
63 smem_mem: smem-mem@86000000 {
64 reg = <0x0 0x86000000 0x0 0x200000>;
65 no-map;
66 };
67 };
68
33 cpus { 69 cpus {
34 #address-cells = <2>; 70 #address-cells = <2>;
35 #size-cells = <0>; 71 #size-cells = <0>;
@@ -192,14 +228,14 @@
192 }; 228 };
193 229
194 clocks { 230 clocks {
195 xo_board { 231 xo_board: xo_board {
196 compatible = "fixed-clock"; 232 compatible = "fixed-clock";
197 #clock-cells = <0>; 233 #clock-cells = <0>;
198 clock-frequency = <19200000>; 234 clock-frequency = <19200000>;
199 clock-output-names = "xo_board"; 235 clock-output-names = "xo_board";
200 }; 236 };
201 237
202 sleep_clk { 238 sleep_clk: sleep_clk {
203 compatible = "fixed-clock"; 239 compatible = "fixed-clock";
204 #clock-cells = <0>; 240 #clock-cells = <0>;
205 clock-frequency = <32764>; 241 clock-frequency = <32764>;
@@ -212,12 +248,29 @@
212 method = "smc"; 248 method = "smc";
213 }; 249 };
214 250
251 tcsr_mutex: hwlock {
252 compatible = "qcom,tcsr-mutex";
253 syscon = <&tcsr_mutex_regs 0 0x1000>;
254 #hwlock-cells = <1>;
255 };
256
257 smem {
258 compatible = "qcom,smem";
259 memory-region = <&smem_mem>;
260 hwlocks = <&tcsr_mutex 3>;
261 };
262
215 soc: soc { 263 soc: soc {
216 #address-cells = <1>; 264 #address-cells = <1>;
217 #size-cells = <1>; 265 #size-cells = <1>;
218 ranges = <0 0 0 0xffffffff>; 266 ranges = <0 0 0 0xffffffff>;
219 compatible = "simple-bus"; 267 compatible = "simple-bus";
220 268
269 tcsr_mutex_regs: syscon@740000 {
270 compatible = "syscon";
271 reg = <0x740000 0x20000>;
272 };
273
221 intc: interrupt-controller@9bc0000 { 274 intc: interrupt-controller@9bc0000 {
222 compatible = "arm,gic-v3"; 275 compatible = "arm,gic-v3";
223 #interrupt-cells = <3>; 276 #interrupt-cells = <3>;
@@ -229,6 +282,11 @@
229 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 282 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
230 }; 283 };
231 284
285 apcs: syscon@9820000 {
286 compatible = "syscon";
287 reg = <0x9820000 0x1000>;
288 };
289
232 gcc: clock-controller@300000 { 290 gcc: clock-controller@300000 {
233 compatible = "qcom,gcc-msm8996"; 291 compatible = "qcom,gcc-msm8996";
234 #clock-cells = <1>; 292 #clock-cells = <1>;
@@ -347,9 +405,10 @@
347 interrupts = <0 125 0>, <0 221 0>; 405 interrupts = <0 125 0>, <0 221 0>;
348 interrupt-names = "hc_irq", "pwr_irq"; 406 interrupt-names = "hc_irq", "pwr_irq";
349 407
350 clock-names = "iface", "core"; 408 clock-names = "iface", "core", "xo";
351 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 409 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
352 <&gcc GCC_SDCC2_APPS_CLK>; 410 <&gcc GCC_SDCC2_APPS_CLK>,
411 <&xo_board>;
353 bus-width = <4>; 412 bus-width = <4>;
354 }; 413 };
355 414
@@ -458,5 +517,29 @@
458 <825000000>; 517 <825000000>;
459 }; 518 };
460 }; 519 };
520
521 adsp-smp2p {
522 compatible = "qcom,smp2p";
523 qcom,smem = <443>, <429>;
524
525 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
526
527 qcom,ipc = <&apcs 16 10>;
528
529 qcom,local-pid = <0>;
530 qcom,remote-pid = <2>;
531
532 adsp_smp2p_out: master-kernel {
533 qcom,entry-name = "master-kernel";
534 #qcom,state-cells = <1>;
535 };
536
537 adsp_smp2p_in: slave-kernel {
538 qcom,entry-name = "slave-kernel";
539
540 interrupt-controller;
541 #interrupt-cells = <2>;
542 };
543 };
461}; 544};
462#include "msm8996-pins.dtsi" 545#include "msm8996-pins.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi
index f71679b15d54..53deebf9f515 100644
--- a/arch/arm64/boot/dts/qcom/pm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi
@@ -91,9 +91,52 @@
91 }; 91 };
92 92
93 pm8916_1: pm8916@1 { 93 pm8916_1: pm8916@1 {
94 compatible = "qcom,spmi-pmic"; 94 compatible = "qcom,pm8916", "qcom,spmi-pmic";
95 reg = <0x1 SPMI_USID>; 95 reg = <0x1 SPMI_USID>;
96 #address-cells = <1>; 96 #address-cells = <1>;
97 #size-cells = <0>; 97 #size-cells = <0>;
98
99 wcd_codec: codec@f000 {
100 compatible = "qcom,pm8916-wcd-analog-codec";
101 reg = <0xf000 0x200>;
102 reg-names = "pmic-codec-core";
103 clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>;
104 clock-names = "mclk";
105 interrupt-parent = <&spmi_bus>;
106 interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>,
107 <0x1 0xf0 0x1 IRQ_TYPE_NONE>,
108 <0x1 0xf0 0x2 IRQ_TYPE_NONE>,
109 <0x1 0xf0 0x3 IRQ_TYPE_NONE>,
110 <0x1 0xf0 0x4 IRQ_TYPE_NONE>,
111 <0x1 0xf0 0x5 IRQ_TYPE_NONE>,
112 <0x1 0xf0 0x6 IRQ_TYPE_NONE>,
113 <0x1 0xf0 0x7 IRQ_TYPE_NONE>,
114 <0x1 0xf1 0x0 IRQ_TYPE_NONE>,
115 <0x1 0xf1 0x1 IRQ_TYPE_NONE>,
116 <0x1 0xf1 0x2 IRQ_TYPE_NONE>,
117 <0x1 0xf1 0x3 IRQ_TYPE_NONE>,
118 <0x1 0xf1 0x4 IRQ_TYPE_NONE>,
119 <0x1 0xf1 0x5 IRQ_TYPE_NONE>;
120 interrupt-names = "cdc_spk_cnp_int",
121 "cdc_spk_clip_int",
122 "cdc_spk_ocp_int",
123 "mbhc_ins_rem_det1",
124 "mbhc_but_rel_det",
125 "mbhc_but_press_det",
126 "mbhc_ins_rem_det",
127 "mbhc_switch_int",
128 "cdc_ear_ocp_int",
129 "cdc_hphr_ocp_int",
130 "cdc_hphl_ocp_det",
131 "cdc_ear_cnp_int",
132 "cdc_hphr_cnp_int",
133 "cdc_hphl_cnp_int";
134 vdd-cdc-io-supply = <&pm8916_l5>;
135 vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>;
136 vdd-micbias-supply = <&pm8916_l13>;
137 #sound-dai-cells = <1>;
138
139 };
140
98 }; 141 };
99}; 142};
diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi
index 1222d2e904f6..0f1866024ae3 100644
--- a/arch/arm64/boot/dts/qcom/pm8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi
@@ -29,6 +29,7 @@
29 <0 0xcc 0 IRQ_TYPE_NONE>, 29 <0 0xcc 0 IRQ_TYPE_NONE>,
30 <0 0xcd 0 IRQ_TYPE_NONE>, 30 <0 0xcd 0 IRQ_TYPE_NONE>,
31 <0 0xce 0 IRQ_TYPE_NONE>, 31 <0 0xce 0 IRQ_TYPE_NONE>,
32 <0 0xcf 0 IRQ_TYPE_NONE>,
32 <0 0xd0 0 IRQ_TYPE_NONE>, 33 <0 0xd0 0 IRQ_TYPE_NONE>,
33 <0 0xd1 0 IRQ_TYPE_NONE>, 34 <0 0xd1 0 IRQ_TYPE_NONE>,
34 <0 0xd2 0 IRQ_TYPE_NONE>, 35 <0 0xd2 0 IRQ_TYPE_NONE>,
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index eb72830ec9eb..1618e0a3c81d 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -1,5 +1,5 @@
1dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb 1dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
2dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb 2dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
3 3
4always := $(dtb-y) 4always := $(dtb-y)
5clean-files := *.dtb 5clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index bcb11a868343..6ffb0517421a 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Device Tree Source for the H3ULCB board 2 * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board
3 * 3 *
4 * Copyright (C) 2016 Renesas Electronics Corp. 4 * Copyright (C) 2016 Renesas Electronics Corp.
5 * Copyright (C) 2016 Cogent Embedded, Inc. 5 * Copyright (C) 2016 Cogent Embedded, Inc.
@@ -62,6 +62,24 @@
62 clock-frequency = <24576000>; 62 clock-frequency = <24576000>;
63 }; 63 };
64 64
65 reg_1p8v: regulator0 {
66 compatible = "regulator-fixed";
67 regulator-name = "fixed-1.8V";
68 regulator-min-microvolt = <1800000>;
69 regulator-max-microvolt = <1800000>;
70 regulator-boot-on;
71 regulator-always-on;
72 };
73
74 reg_3p3v: regulator1 {
75 compatible = "regulator-fixed";
76 regulator-name = "fixed-3.3V";
77 regulator-min-microvolt = <3300000>;
78 regulator-max-microvolt = <3300000>;
79 regulator-boot-on;
80 regulator-always-on;
81 };
82
65 vcc_sdhi0: regulator-vcc-sdhi0 { 83 vcc_sdhi0: regulator-vcc-sdhi0 {
66 compatible = "regulator-fixed"; 84 compatible = "regulator-fixed";
67 85
@@ -145,18 +163,30 @@
145 function = "avb"; 163 function = "avb";
146 }; 164 };
147 165
148 sdhi0_pins_3v3: sd0_3v3 { 166 sdhi0_pins: sd0 {
149 groups = "sdhi0_data4", "sdhi0_ctrl"; 167 groups = "sdhi0_data4", "sdhi0_ctrl";
150 function = "sdhi0"; 168 function = "sdhi0";
151 power-source = <3300>; 169 power-source = <3300>;
152 }; 170 };
153 171
154 sdhi0_pins_1v8: sd0_1v8 { 172 sdhi0_pins_uhs: sd0 {
155 groups = "sdhi0_data4", "sdhi0_ctrl"; 173 groups = "sdhi0_data4", "sdhi0_ctrl";
156 function = "sdhi0"; 174 function = "sdhi0";
157 power-source = <1800>; 175 power-source = <1800>;
158 }; 176 };
159 177
178 sdhi2_pins: sd2 {
179 groups = "sdhi2_data8", "sdhi2_ctrl";
180 function = "sdhi2";
181 power-source = <3300>;
182 };
183
184 sdhi2_pins_uhs: sd2_uhs {
185 groups = "sdhi2_data8", "sdhi2_ctrl";
186 function = "sdhi2";
187 power-source = <1800>;
188 };
189
160 sound_pins: sound { 190 sound_pins: sound {
161 groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; 191 groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
162 function = "ssi"; 192 function = "ssi";
@@ -261,8 +291,8 @@
261}; 291};
262 292
263&sdhi0 { 293&sdhi0 {
264 pinctrl-0 = <&sdhi0_pins_3v3>; 294 pinctrl-0 = <&sdhi0_pins>;
265 pinctrl-1 = <&sdhi0_pins_1v8>; 295 pinctrl-1 = <&sdhi0_pins_uhs>;
266 pinctrl-names = "default", "state_uhs"; 296 pinctrl-names = "default", "state_uhs";
267 297
268 vmmc-supply = <&vcc_sdhi0>; 298 vmmc-supply = <&vcc_sdhi0>;
@@ -273,6 +303,19 @@
273 status = "okay"; 303 status = "okay";
274}; 304};
275 305
306&sdhi2 {
307 /* used for on-board 8bit eMMC */
308 pinctrl-0 = <&sdhi2_pins>;
309 pinctrl-1 = <&sdhi2_pins_uhs>;
310 pinctrl-names = "default", "state_uhs";
311
312 vmmc-supply = <&reg_3p3v>;
313 vqmmc-supply = <&reg_1p8v>;
314 bus-width = <8>;
315 non-removable;
316 status = "okay";
317};
318
276&ssi1 { 319&ssi1 {
277 shared-pin; 320 shared-pin;
278}; 321};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index b1eab6876f8c..bcaf4008d32d 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -62,6 +62,24 @@
62 clock-frequency = <24576000>; 62 clock-frequency = <24576000>;
63 }; 63 };
64 64
65 reg_1p8v: regulator0 {
66 compatible = "regulator-fixed";
67 regulator-name = "fixed-1.8V";
68 regulator-min-microvolt = <1800000>;
69 regulator-max-microvolt = <1800000>;
70 regulator-boot-on;
71 regulator-always-on;
72 };
73
74 reg_3p3v: regulator1 {
75 compatible = "regulator-fixed";
76 regulator-name = "fixed-3.3V";
77 regulator-min-microvolt = <3300000>;
78 regulator-max-microvolt = <3300000>;
79 regulator-boot-on;
80 regulator-always-on;
81 };
82
65 vcc_sdhi0: regulator-vcc-sdhi0 { 83 vcc_sdhi0: regulator-vcc-sdhi0 {
66 compatible = "regulator-fixed"; 84 compatible = "regulator-fixed";
67 85
@@ -191,6 +209,10 @@
191 remote-endpoint = <&adv7123_in>; 209 remote-endpoint = <&adv7123_in>;
192 }; 210 };
193 }; 211 };
212 port@3 {
213 lvds_connector: endpoint {
214 };
215 };
194 }; 216 };
195}; 217};
196 218
@@ -237,11 +259,37 @@
237 sdhi0_pins: sd0 { 259 sdhi0_pins: sd0 {
238 groups = "sdhi0_data4", "sdhi0_ctrl"; 260 groups = "sdhi0_data4", "sdhi0_ctrl";
239 function = "sdhi0"; 261 function = "sdhi0";
262 power-source = <3300>;
263 };
264
265 sdhi0_pins_uhs: sd0_uhs {
266 groups = "sdhi0_data4", "sdhi0_ctrl";
267 function = "sdhi0";
268 power-source = <1800>;
269 };
270
271 sdhi2_pins: sd2 {
272 groups = "sdhi2_data8", "sdhi2_ctrl";
273 function = "sdhi2";
274 power-source = <3300>;
275 };
276
277 sdhi2_pins_uhs: sd2_uhs {
278 groups = "sdhi2_data8", "sdhi2_ctrl";
279 function = "sdhi2";
280 power-source = <1800>;
240 }; 281 };
241 282
242 sdhi3_pins: sd3 { 283 sdhi3_pins: sd3 {
243 groups = "sdhi3_data4", "sdhi3_ctrl"; 284 groups = "sdhi3_data4", "sdhi3_ctrl";
244 function = "sdhi3"; 285 function = "sdhi3";
286 power-source = <3300>;
287 };
288
289 sdhi3_pins_uhs: sd3_uhs {
290 groups = "sdhi3_data4", "sdhi3_ctrl";
291 function = "sdhi3";
292 power-source = <1800>;
245 }; 293 };
246 294
247 sound_pins: sound { 295 sound_pins: sound {
@@ -261,8 +309,20 @@
261 }; 309 };
262 310
263 usb1_pins: usb1 { 311 usb1_pins: usb1 {
264 groups = "usb1"; 312 mux {
265 function = "usb1"; 313 groups = "usb1";
314 function = "usb1";
315 };
316
317 ovc {
318 pins = "GP_6_27";
319 bias-pull-up;
320 };
321
322 pwen {
323 pins = "GP_6_26";
324 bias-pull-down;
325 };
266 }; 326 };
267 327
268 usb2_pins: usb2 { 328 usb2_pins: usb2 {
@@ -371,25 +431,42 @@
371 431
372&sdhi0 { 432&sdhi0 {
373 pinctrl-0 = <&sdhi0_pins>; 433 pinctrl-0 = <&sdhi0_pins>;
374 pinctrl-names = "default"; 434 pinctrl-1 = <&sdhi0_pins_uhs>;
435 pinctrl-names = "default", "state_uhs";
375 436
376 vmmc-supply = <&vcc_sdhi0>; 437 vmmc-supply = <&vcc_sdhi0>;
377 vqmmc-supply = <&vccq_sdhi0>; 438 vqmmc-supply = <&vccq_sdhi0>;
378 cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; 439 cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
379 wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; 440 wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
380 bus-width = <4>; 441 bus-width = <4>;
442 sd-uhs-sdr50;
443 status = "okay";
444};
445
446&sdhi2 {
447 /* used for on-board 8bit eMMC */
448 pinctrl-0 = <&sdhi2_pins>;
449 pinctrl-1 = <&sdhi2_pins_uhs>;
450 pinctrl-names = "default", "state_uhs";
451
452 vmmc-supply = <&reg_3p3v>;
453 vqmmc-supply = <&reg_1p8v>;
454 bus-width = <8>;
455 non-removable;
381 status = "okay"; 456 status = "okay";
382}; 457};
383 458
384&sdhi3 { 459&sdhi3 {
385 pinctrl-0 = <&sdhi3_pins>; 460 pinctrl-0 = <&sdhi3_pins>;
386 pinctrl-names = "default"; 461 pinctrl-1 = <&sdhi3_pins_uhs>;
462 pinctrl-names = "default", "state_uhs";
387 463
388 vmmc-supply = <&vcc_sdhi3>; 464 vmmc-supply = <&vcc_sdhi3>;
389 vqmmc-supply = <&vccq_sdhi3>; 465 vqmmc-supply = <&vccq_sdhi3>;
390 cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; 466 cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
391 wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; 467 wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
392 bus-width = <4>; 468 bus-width = <4>;
469 sd-uhs-sdr50;
393 status = "okay"; 470 status = "okay";
394}; 471};
395 472
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 625dda713548..bbf594bce930 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -326,6 +326,11 @@
326 reg = <0 0xe6160000 0 0x0200>; 326 reg = <0 0xe6160000 0 0x0200>;
327 }; 327 };
328 328
329 prr: chipid@fff00044 {
330 compatible = "renesas,prr";
331 reg = <0 0xfff00044 0 4>;
332 };
333
329 sysc: system-controller@e6180000 { 334 sysc: system-controller@e6180000 {
330 compatible = "renesas,r8a7795-sysc"; 335 compatible = "renesas,r8a7795-sysc";
331 reg = <0 0xe6180000 0 0x0400>; 336 reg = <0 0xe6180000 0 0x0400>;
@@ -1311,28 +1316,28 @@
1311 }; 1316 };
1312 1317
1313 fcpvb1: fcp@fe92f000 { 1318 fcpvb1: fcp@fe92f000 {
1314 compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; 1319 compatible = "renesas,fcpv";
1315 reg = <0 0xfe92f000 0 0x200>; 1320 reg = <0 0xfe92f000 0 0x200>;
1316 clocks = <&cpg CPG_MOD 606>; 1321 clocks = <&cpg CPG_MOD 606>;
1317 power-domains = <&sysc R8A7795_PD_A3VP>; 1322 power-domains = <&sysc R8A7795_PD_A3VP>;
1318 }; 1323 };
1319 1324
1320 fcpf0: fcp@fe950000 { 1325 fcpf0: fcp@fe950000 {
1321 compatible = "renesas,r8a7795-fcpf", "renesas,fcpf"; 1326 compatible = "renesas,fcpf";
1322 reg = <0 0xfe950000 0 0x200>; 1327 reg = <0 0xfe950000 0 0x200>;
1323 clocks = <&cpg CPG_MOD 615>; 1328 clocks = <&cpg CPG_MOD 615>;
1324 power-domains = <&sysc R8A7795_PD_A3VP>; 1329 power-domains = <&sysc R8A7795_PD_A3VP>;
1325 }; 1330 };
1326 1331
1327 fcpf1: fcp@fe951000 { 1332 fcpf1: fcp@fe951000 {
1328 compatible = "renesas,r8a7795-fcpf", "renesas,fcpf"; 1333 compatible = "renesas,fcpf";
1329 reg = <0 0xfe951000 0 0x200>; 1334 reg = <0 0xfe951000 0 0x200>;
1330 clocks = <&cpg CPG_MOD 614>; 1335 clocks = <&cpg CPG_MOD 614>;
1331 power-domains = <&sysc R8A7795_PD_A3VP>; 1336 power-domains = <&sysc R8A7795_PD_A3VP>;
1332 }; 1337 };
1333 1338
1334 fcpf2: fcp@fe952000 { 1339 fcpf2: fcp@fe952000 {
1335 compatible = "renesas,r8a7795-fcpf", "renesas,fcpf"; 1340 compatible = "renesas,fcpf";
1336 reg = <0 0xfe952000 0 0x200>; 1341 reg = <0 0xfe952000 0 0x200>;
1337 clocks = <&cpg CPG_MOD 613>; 1342 clocks = <&cpg CPG_MOD 613>;
1338 power-domains = <&sysc R8A7795_PD_A3VP>; 1343 power-domains = <&sysc R8A7795_PD_A3VP>;
@@ -1349,7 +1354,7 @@
1349 }; 1354 };
1350 1355
1351 fcpvb0: fcp@fe96f000 { 1356 fcpvb0: fcp@fe96f000 {
1352 compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; 1357 compatible = "renesas,fcpv";
1353 reg = <0 0xfe96f000 0 0x200>; 1358 reg = <0 0xfe96f000 0 0x200>;
1354 clocks = <&cpg CPG_MOD 607>; 1359 clocks = <&cpg CPG_MOD 607>;
1355 power-domains = <&sysc R8A7795_PD_A3VP>; 1360 power-domains = <&sysc R8A7795_PD_A3VP>;
@@ -1366,7 +1371,7 @@
1366 }; 1371 };
1367 1372
1368 fcpvi0: fcp@fe9af000 { 1373 fcpvi0: fcp@fe9af000 {
1369 compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; 1374 compatible = "renesas,fcpv";
1370 reg = <0 0xfe9af000 0 0x200>; 1375 reg = <0 0xfe9af000 0 0x200>;
1371 clocks = <&cpg CPG_MOD 611>; 1376 clocks = <&cpg CPG_MOD 611>;
1372 power-domains = <&sysc R8A7795_PD_A3VP>; 1377 power-domains = <&sysc R8A7795_PD_A3VP>;
@@ -1383,7 +1388,7 @@
1383 }; 1388 };
1384 1389
1385 fcpvi1: fcp@fe9bf000 { 1390 fcpvi1: fcp@fe9bf000 {
1386 compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; 1391 compatible = "renesas,fcpv";
1387 reg = <0 0xfe9bf000 0 0x200>; 1392 reg = <0 0xfe9bf000 0 0x200>;
1388 clocks = <&cpg CPG_MOD 610>; 1393 clocks = <&cpg CPG_MOD 610>;
1389 power-domains = <&sysc R8A7795_PD_A3VP>; 1394 power-domains = <&sysc R8A7795_PD_A3VP>;
@@ -1400,7 +1405,7 @@
1400 }; 1405 };
1401 1406
1402 fcpvi2: fcp@fe9cf000 { 1407 fcpvi2: fcp@fe9cf000 {
1403 compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; 1408 compatible = "renesas,fcpv";
1404 reg = <0 0xfe9cf000 0 0x200>; 1409 reg = <0 0xfe9cf000 0 0x200>;
1405 clocks = <&cpg CPG_MOD 609>; 1410 clocks = <&cpg CPG_MOD 609>;
1406 power-domains = <&sysc R8A7795_PD_A3VP>; 1411 power-domains = <&sysc R8A7795_PD_A3VP>;
@@ -1417,7 +1422,7 @@
1417 }; 1422 };
1418 1423
1419 fcpvd0: fcp@fea27000 { 1424 fcpvd0: fcp@fea27000 {
1420 compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; 1425 compatible = "renesas,fcpv";
1421 reg = <0 0xfea27000 0 0x200>; 1426 reg = <0 0xfea27000 0 0x200>;
1422 clocks = <&cpg CPG_MOD 603>; 1427 clocks = <&cpg CPG_MOD 603>;
1423 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1428 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -1434,7 +1439,7 @@
1434 }; 1439 };
1435 1440
1436 fcpvd1: fcp@fea2f000 { 1441 fcpvd1: fcp@fea2f000 {
1437 compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; 1442 compatible = "renesas,fcpv";
1438 reg = <0 0xfea2f000 0 0x200>; 1443 reg = <0 0xfea2f000 0 0x200>;
1439 clocks = <&cpg CPG_MOD 602>; 1444 clocks = <&cpg CPG_MOD 602>;
1440 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1445 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -1451,7 +1456,7 @@
1451 }; 1456 };
1452 1457
1453 fcpvd2: fcp@fea37000 { 1458 fcpvd2: fcp@fea37000 {
1454 compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; 1459 compatible = "renesas,fcpv";
1455 reg = <0 0xfea37000 0 0x200>; 1460 reg = <0 0xfea37000 0 0x200>;
1456 clocks = <&cpg CPG_MOD 601>; 1461 clocks = <&cpg CPG_MOD 601>;
1457 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1462 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -1468,7 +1473,7 @@
1468 }; 1473 };
1469 1474
1470 fcpvd3: fcp@fea3f000 { 1475 fcpvd3: fcp@fea3f000 {
1471 compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; 1476 compatible = "renesas,fcpv";
1472 reg = <0 0xfea3f000 0 0x200>; 1477 reg = <0 0xfea3f000 0 0x200>;
1473 clocks = <&cpg CPG_MOD 600>; 1478 clocks = <&cpg CPG_MOD 600>;
1474 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1479 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
new file mode 100644
index 000000000000..c3f064ac2cb4
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -0,0 +1,189 @@
1/*
2 * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board
3 *
4 * Copyright (C) 2016 Renesas Electronics Corp.
5 * Copyright (C) 2016 Cogent Embedded, Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12/dts-v1/;
13#include "r8a7796.dtsi"
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/input/input.h>
16
17/ {
18 model = "Renesas M3ULCB board based on r8a7796";
19 compatible = "renesas,m3ulcb", "renesas,r8a7796";
20
21 aliases {
22 serial0 = &scif2;
23 };
24
25 chosen {
26 stdout-path = "serial0:115200n8";
27 };
28
29 memory@48000000 {
30 device_type = "memory";
31 /* first 128MB is reserved for secure area. */
32 reg = <0x0 0x48000000 0x0 0x38000000>;
33 };
34
35 leds {
36 compatible = "gpio-leds";
37
38 led5 {
39 gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
40 };
41 led6 {
42 gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
43 };
44 };
45
46 keyboard {
47 compatible = "gpio-keys";
48
49 key-1 {
50 linux,code = <KEY_1>;
51 label = "SW3";
52 wakeup-source;
53 debounce-interval = <20>;
54 gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
55 };
56 };
57
58 reg_1p8v: regulator0 {
59 compatible = "regulator-fixed";
60 regulator-name = "fixed-1.8V";
61 regulator-min-microvolt = <1800000>;
62 regulator-max-microvolt = <1800000>;
63 regulator-boot-on;
64 regulator-always-on;
65 };
66
67 reg_3p3v: regulator1 {
68 compatible = "regulator-fixed";
69 regulator-name = "fixed-3.3V";
70 regulator-min-microvolt = <3300000>;
71 regulator-max-microvolt = <3300000>;
72 regulator-boot-on;
73 regulator-always-on;
74 };
75
76 vcc_sdhi0: regulator-vcc-sdhi0 {
77 compatible = "regulator-fixed";
78
79 regulator-name = "SDHI0 Vcc";
80 regulator-min-microvolt = <3300000>;
81 regulator-max-microvolt = <3300000>;
82
83 gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
84 enable-active-high;
85 };
86
87 vccq_sdhi0: regulator-vccq-sdhi0 {
88 compatible = "regulator-gpio";
89
90 regulator-name = "SDHI0 VccQ";
91 regulator-min-microvolt = <1800000>;
92 regulator-max-microvolt = <3300000>;
93
94 gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
95 gpios-states = <1>;
96 states = <3300000 1
97 1800000 0>;
98 };
99};
100
101&extal_clk {
102 clock-frequency = <16666666>;
103};
104
105&extalr_clk {
106 clock-frequency = <32768>;
107};
108
109&pfc {
110 pinctrl-0 = <&scif_clk_pins>;
111 pinctrl-names = "default";
112
113 scif2_pins: scif2 {
114 groups = "scif2_data_a";
115 function = "scif2";
116 };
117
118 scif_clk_pins: scif_clk {
119 groups = "scif_clk_a";
120 function = "scif_clk";
121 };
122
123 sdhi0_pins: sd0 {
124 groups = "sdhi0_data4", "sdhi0_ctrl";
125 function = "sdhi0";
126 power-source = <3300>;
127 };
128
129 sdhi0_pins_uhs: sd0_uhs {
130 groups = "sdhi0_data4", "sdhi0_ctrl";
131 function = "sdhi0";
132 power-source = <1800>;
133 };
134
135 sdhi2_pins: sd2 {
136 groups = "sdhi2_data8", "sdhi2_ctrl";
137 function = "sdhi2";
138 power-source = <3300>;
139 };
140
141 sdhi2_pins_uhs: sd2_uhs {
142 groups = "sdhi2_data8", "sdhi2_ctrl";
143 function = "sdhi2";
144 power-source = <1800>;
145 };
146};
147
148&sdhi0 {
149 pinctrl-0 = <&sdhi0_pins>;
150 pinctrl-1 = <&sdhi0_pins_uhs>;
151 pinctrl-names = "default", "state_uhs";
152
153 vmmc-supply = <&vcc_sdhi0>;
154 vqmmc-supply = <&vccq_sdhi0>;
155 cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
156 bus-width = <4>;
157 sd-uhs-sdr50;
158 status = "okay";
159};
160
161&sdhi2 {
162 /* used for on-board 8bit eMMC */
163 pinctrl-0 = <&sdhi2_pins>;
164 pinctrl-1 = <&sdhi2_pins_uhs>;
165 pinctrl-names = "default", "state_uhs";
166
167 vmmc-supply = <&reg_3p3v>;
168 vqmmc-supply = <&reg_1p8v>;
169 bus-width = <8>;
170 non-removable;
171 status = "okay";
172};
173
174&scif2 {
175 pinctrl-0 = <&scif2_pins>;
176 pinctrl-names = "default";
177
178 status = "okay";
179};
180
181&scif_clk {
182 clock-frequency = <14745600>;
183 status = "okay";
184};
185
186&wdt0 {
187 timeout-sec = <60>;
188 status = "okay";
189};
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
index 13db7d61c26c..f35e96ca7d60 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -10,6 +10,7 @@
10 10
11/dts-v1/; 11/dts-v1/;
12#include "r8a7796.dtsi" 12#include "r8a7796.dtsi"
13#include <dt-bindings/gpio/gpio.h>
13 14
14/ { 15/ {
15 model = "Renesas Salvator-X board based on r8a7796"; 16 model = "Renesas Salvator-X board based on r8a7796";
@@ -29,6 +30,72 @@
29 /* first 128MB is reserved for secure area. */ 30 /* first 128MB is reserved for secure area. */
30 reg = <0x0 0x48000000 0x0 0x78000000>; 31 reg = <0x0 0x48000000 0x0 0x78000000>;
31 }; 32 };
33
34 reg_1p8v: regulator0 {
35 compatible = "regulator-fixed";
36 regulator-name = "fixed-1.8V";
37 regulator-min-microvolt = <1800000>;
38 regulator-max-microvolt = <1800000>;
39 regulator-boot-on;
40 regulator-always-on;
41 };
42
43 reg_3p3v: regulator1 {
44 compatible = "regulator-fixed";
45 regulator-name = "fixed-3.3V";
46 regulator-min-microvolt = <3300000>;
47 regulator-max-microvolt = <3300000>;
48 regulator-boot-on;
49 regulator-always-on;
50 };
51
52 vcc_sdhi0: regulator-vcc-sdhi0 {
53 compatible = "regulator-fixed";
54
55 regulator-name = "SDHI0 Vcc";
56 regulator-min-microvolt = <3300000>;
57 regulator-max-microvolt = <3300000>;
58
59 gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
60 enable-active-high;
61 };
62
63 vccq_sdhi0: regulator-vccq-sdhi0 {
64 compatible = "regulator-gpio";
65
66 regulator-name = "SDHI0 VccQ";
67 regulator-min-microvolt = <1800000>;
68 regulator-max-microvolt = <3300000>;
69
70 gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
71 gpios-states = <1>;
72 states = <3300000 1
73 1800000 0>;
74 };
75
76 vcc_sdhi3: regulator-vcc-sdhi3 {
77 compatible = "regulator-fixed";
78
79 regulator-name = "SDHI3 Vcc";
80 regulator-min-microvolt = <3300000>;
81 regulator-max-microvolt = <3300000>;
82
83 gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
84 enable-active-high;
85 };
86
87 vccq_sdhi3: regulator-vccq-sdhi3 {
88 compatible = "regulator-gpio";
89
90 regulator-name = "SDHI3 VccQ";
91 regulator-min-microvolt = <1800000>;
92 regulator-max-microvolt = <3300000>;
93
94 gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
95 gpios-states = <1>;
96 states = <3300000 1
97 1800000 0>;
98 };
32}; 99};
33 100
34&pfc { 101&pfc {
@@ -43,12 +110,98 @@
43 groups = "scif_clk_a"; 110 groups = "scif_clk_a";
44 function = "scif_clk"; 111 function = "scif_clk";
45 }; 112 };
113
114 i2c2_pins: i2c2 {
115 groups = "i2c2_a";
116 function = "i2c2";
117 };
118
119 sdhi0_pins: sd0 {
120 groups = "sdhi0_data4", "sdhi0_ctrl";
121 function = "sdhi0";
122 power-source = <3300>;
123 };
124
125 sdhi0_pins_uhs: sd0_uhs {
126 groups = "sdhi0_data4", "sdhi0_ctrl";
127 function = "sdhi0";
128 power-source = <1800>;
129 };
130
131 sdhi2_pins: sd2 {
132 groups = "sdhi2_data8", "sdhi2_ctrl";
133 function = "sdhi2";
134 power-source = <3300>;
135 };
136
137 sdhi2_pins_uhs: sd2_uhs {
138 groups = "sdhi2_data8", "sdhi2_ctrl";
139 function = "sdhi2";
140 power-source = <1800>;
141 };
142
143 sdhi3_pins: sd3 {
144 groups = "sdhi3_data4", "sdhi3_ctrl";
145 function = "sdhi3";
146 power-source = <3300>;
147 };
148
149 sdhi3_pins_uhs: sd3_uhs {
150 groups = "sdhi3_data4", "sdhi3_ctrl";
151 function = "sdhi3";
152 power-source = <1800>;
153 };
46}; 154};
47 155
48&extal_clk { 156&extal_clk {
49 clock-frequency = <16666666>; 157 clock-frequency = <16666666>;
50}; 158};
51 159
160&extalr_clk {
161 clock-frequency = <32768>;
162};
163
164&sdhi0 {
165 pinctrl-0 = <&sdhi0_pins>;
166 pinctrl-1 = <&sdhi0_pins_uhs>;
167 pinctrl-names = "default", "state_uhs";
168
169 vmmc-supply = <&vcc_sdhi0>;
170 vqmmc-supply = <&vccq_sdhi0>;
171 cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
172 wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
173 bus-width = <4>;
174 sd-uhs-sdr50;
175 status = "okay";
176};
177
178&sdhi2 {
179 /* used for on-board 8bit eMMC */
180 pinctrl-0 = <&sdhi2_pins>;
181 pinctrl-1 = <&sdhi2_pins_uhs>;
182 pinctrl-names = "default", "state_uhs";
183
184 vmmc-supply = <&reg_3p3v>;
185 vqmmc-supply = <&reg_1p8v>;
186 bus-width = <8>;
187 non-removable;
188 status = "okay";
189};
190
191&sdhi3 {
192 pinctrl-0 = <&sdhi3_pins>;
193 pinctrl-1 = <&sdhi3_pins_uhs>;
194 pinctrl-names = "default", "state_uhs";
195
196 vmmc-supply = <&vcc_sdhi3>;
197 vqmmc-supply = <&vccq_sdhi3>;
198 cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
199 wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
200 bus-width = <4>;
201 sd-uhs-sdr50;
202 status = "okay";
203};
204
52&scif2 { 205&scif2 {
53 pinctrl-0 = <&scif2_pins>; 206 pinctrl-0 = <&scif2_pins>;
54 pinctrl-names = "default"; 207 pinctrl-names = "default";
@@ -60,6 +213,13 @@
60 status = "okay"; 213 status = "okay";
61}; 214};
62 215
216&i2c2 {
217 pinctrl-0 = <&i2c2_pins>;
218 pinctrl-names = "default";
219
220 status = "okay";
221};
222
63&wdt0 { 223&wdt0 {
64 timeout-sec = <60>; 224 timeout-sec = <60>;
65 status = "okay"; 225 status = "okay";
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 75c8c55a8248..28ba59a00cd8 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -17,6 +17,16 @@
17 #address-cells = <2>; 17 #address-cells = <2>;
18 #size-cells = <2>; 18 #size-cells = <2>;
19 19
20 aliases {
21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
24 i2c3 = &i2c3;
25 i2c4 = &i2c4;
26 i2c5 = &i2c5;
27 i2c6 = &i2c6;
28 };
29
20 psci { 30 psci {
21 compatible = "arm,psci-0.2"; 31 compatible = "arm,psci-0.2";
22 method = "smc"; 32 method = "smc";
@@ -238,12 +248,118 @@
238 reg = <0 0xe6160000 0 0x0200>; 248 reg = <0 0xe6160000 0 0x0200>;
239 }; 249 };
240 250
251 prr: chipid@fff00044 {
252 compatible = "renesas,prr";
253 reg = <0 0xfff00044 0 4>;
254 };
255
241 sysc: system-controller@e6180000 { 256 sysc: system-controller@e6180000 {
242 compatible = "renesas,r8a7796-sysc"; 257 compatible = "renesas,r8a7796-sysc";
243 reg = <0 0xe6180000 0 0x0400>; 258 reg = <0 0xe6180000 0 0x0400>;
244 #power-domain-cells = <1>; 259 #power-domain-cells = <1>;
245 }; 260 };
246 261
262 i2c0: i2c@e6500000 {
263 #address-cells = <1>;
264 #size-cells = <0>;
265 compatible = "renesas,i2c-r8a7796";
266 reg = <0 0xe6500000 0 0x40>;
267 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&cpg CPG_MOD 931>;
269 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
270 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
271 <&dmac2 0x91>, <&dmac2 0x90>;
272 dma-names = "tx", "rx", "tx", "rx";
273 i2c-scl-internal-delay-ns = <110>;
274 status = "disabled";
275 };
276
277 i2c1: i2c@e6508000 {
278 #address-cells = <1>;
279 #size-cells = <0>;
280 compatible = "renesas,i2c-r8a7796";
281 reg = <0 0xe6508000 0 0x40>;
282 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&cpg CPG_MOD 930>;
284 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
285 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
286 <&dmac2 0x93>, <&dmac2 0x92>;
287 dma-names = "tx", "rx", "tx", "rx";
288 i2c-scl-internal-delay-ns = <6>;
289 status = "disabled";
290 };
291
292 i2c2: i2c@e6510000 {
293 #address-cells = <1>;
294 #size-cells = <0>;
295 compatible = "renesas,i2c-r8a7796";
296 reg = <0 0xe6510000 0 0x40>;
297 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&cpg CPG_MOD 929>;
299 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
300 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
301 <&dmac2 0x95>, <&dmac2 0x94>;
302 dma-names = "tx", "rx", "tx", "rx";
303 i2c-scl-internal-delay-ns = <6>;
304 status = "disabled";
305 };
306
307 i2c3: i2c@e66d0000 {
308 #address-cells = <1>;
309 #size-cells = <0>;
310 compatible = "renesas,i2c-r8a7796";
311 reg = <0 0xe66d0000 0 0x40>;
312 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&cpg CPG_MOD 928>;
314 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
315 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
316 dma-names = "tx", "rx";
317 i2c-scl-internal-delay-ns = <110>;
318 status = "disabled";
319 };
320
321 i2c4: i2c@e66d8000 {
322 #address-cells = <1>;
323 #size-cells = <0>;
324 compatible = "renesas,i2c-r8a7796";
325 reg = <0 0xe66d8000 0 0x40>;
326 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&cpg CPG_MOD 927>;
328 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
329 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
330 dma-names = "tx", "rx";
331 i2c-scl-internal-delay-ns = <110>;
332 status = "disabled";
333 };
334
335 i2c5: i2c@e66e0000 {
336 #address-cells = <1>;
337 #size-cells = <0>;
338 compatible = "renesas,i2c-r8a7796";
339 reg = <0 0xe66e0000 0 0x40>;
340 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&cpg CPG_MOD 919>;
342 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
343 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
344 dma-names = "tx", "rx";
345 i2c-scl-internal-delay-ns = <110>;
346 status = "disabled";
347 };
348
349 i2c6: i2c@e66e8000 {
350 #address-cells = <1>;
351 #size-cells = <0>;
352 compatible = "renesas,i2c-r8a7796";
353 reg = <0 0xe66e8000 0 0x40>;
354 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&cpg CPG_MOD 918>;
356 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
357 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
358 dma-names = "tx", "rx";
359 i2c-scl-internal-delay-ns = <6>;
360 status = "disabled";
361 };
362
247 scif2: serial@e6e88000 { 363 scif2: serial@e6e88000 {
248 compatible = "renesas,scif-r8a7796", 364 compatible = "renesas,scif-r8a7796",
249 "renesas,rcar-gen3-scif", "renesas,scif"; 365 "renesas,rcar-gen3-scif", "renesas,scif";
@@ -256,5 +372,144 @@
256 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 372 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
257 status = "disabled"; 373 status = "disabled";
258 }; 374 };
375
376 dmac0: dma-controller@e6700000 {
377 compatible = "renesas,dmac-r8a7796",
378 "renesas,rcar-dmac";
379 reg = <0 0xe6700000 0 0x10000>;
380 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
381 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
382 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
383 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
384 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
385 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
386 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
387 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
388 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
389 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
390 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
391 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
392 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
393 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
394 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
395 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
396 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
397 interrupt-names = "error",
398 "ch0", "ch1", "ch2", "ch3",
399 "ch4", "ch5", "ch6", "ch7",
400 "ch8", "ch9", "ch10", "ch11",
401 "ch12", "ch13", "ch14", "ch15";
402 clocks = <&cpg CPG_MOD 219>;
403 clock-names = "fck";
404 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
405 #dma-cells = <1>;
406 dma-channels = <16>;
407 };
408
409 dmac1: dma-controller@e7300000 {
410 compatible = "renesas,dmac-r8a7796",
411 "renesas,rcar-dmac";
412 reg = <0 0xe7300000 0 0x10000>;
413 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
414 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
415 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
416 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
417 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
418 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
419 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
420 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
421 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
422 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
423 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
424 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
425 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
426 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
427 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
428 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
429 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
430 interrupt-names = "error",
431 "ch0", "ch1", "ch2", "ch3",
432 "ch4", "ch5", "ch6", "ch7",
433 "ch8", "ch9", "ch10", "ch11",
434 "ch12", "ch13", "ch14", "ch15";
435 clocks = <&cpg CPG_MOD 218>;
436 clock-names = "fck";
437 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
438 #dma-cells = <1>;
439 dma-channels = <16>;
440 };
441
442 dmac2: dma-controller@e7310000 {
443 compatible = "renesas,dmac-r8a7796",
444 "renesas,rcar-dmac";
445 reg = <0 0xe7310000 0 0x10000>;
446 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
447 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
448 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
449 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
450 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
451 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
452 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
453 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
454 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
455 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
456 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
457 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
458 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
459 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
460 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
461 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
462 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
463 interrupt-names = "error",
464 "ch0", "ch1", "ch2", "ch3",
465 "ch4", "ch5", "ch6", "ch7",
466 "ch8", "ch9", "ch10", "ch11",
467 "ch12", "ch13", "ch14", "ch15";
468 clocks = <&cpg CPG_MOD 217>;
469 clock-names = "fck";
470 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
471 #dma-cells = <1>;
472 dma-channels = <16>;
473 };
474
475 sdhi0: sd@ee100000 {
476 compatible = "renesas,sdhi-r8a7796";
477 reg = <0 0xee100000 0 0x2000>;
478 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&cpg CPG_MOD 314>;
480 max-frequency = <200000000>;
481 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
482 status = "disabled";
483 };
484
485 sdhi1: sd@ee120000 {
486 compatible = "renesas,sdhi-r8a7796";
487 reg = <0 0xee120000 0 0x2000>;
488 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&cpg CPG_MOD 313>;
490 max-frequency = <200000000>;
491 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
492 status = "disabled";
493 };
494
495 sdhi2: sd@ee140000 {
496 compatible = "renesas,sdhi-r8a7796";
497 reg = <0 0xee140000 0 0x2000>;
498 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
499 clocks = <&cpg CPG_MOD 312>;
500 max-frequency = <200000000>;
501 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
502 status = "disabled";
503 };
504
505 sdhi3: sd@ee160000 {
506 compatible = "renesas,sdhi-r8a7796";
507 reg = <0 0xee160000 0 0x2000>;
508 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&cpg CPG_MOD 311>;
510 max-frequency = <200000000>;
511 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
512 status = "disabled";
513 };
259 }; 514 };
260}; 515};
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 87669f656454..3a862894ea44 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -1,6 +1,7 @@
1dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb 1dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
2dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb 2dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
3dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb 3dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb
4dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb
4dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb 5dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
5dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb 6dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
6 7
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
index ea0a8eceefd4..ff5a40399d02 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
@@ -344,7 +344,7 @@
344&sdmmc { 344&sdmmc {
345 bus-width = <4>; 345 bus-width = <4>;
346 clock-frequency = <50000000>; 346 clock-frequency = <50000000>;
347 clock-freq-min-max = <400000 50000000>; 347 max-frequency = <50000000>;
348 cap-sd-highspeed; 348 cap-sd-highspeed;
349 card-detect-delay = <200>; 349 card-detect-delay = <200>;
350 num-slots = <1>; 350 num-slots = <1>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
new file mode 100644
index 000000000000..85f7a243d744
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
@@ -0,0 +1,314 @@
1/*
2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/dts-v1/;
44#include "rk3368.dtsi"
45#include <dt-bindings/input/input.h>
46
47/ {
48 model = "Rockchip PX5 EVB";
49 compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
50
51 chosen {
52 stdout-path = "serial4:115200n8";
53 };
54
55 memory@0 {
56 reg = <0x0 0x0 0x0 0x80000000>;
57 device_type = "memory";
58 };
59
60 keys: gpio-keys {
61 compatible = "gpio-keys";
62 pinctrl-names = "default";
63 pinctrl-0 = <&pwr_key>;
64
65 power {
66 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
67 label = "GPIO Power";
68 linux,code = <KEY_POWER>;
69 wakeup-source;
70 };
71 };
72
73 vcc_sys: vcc-sys-regulator {
74 compatible = "regulator-fixed";
75 regulator-name = "vcc_sys";
76 regulator-min-microvolt = <5000000>;
77 regulator-max-microvolt = <5000000>;
78 regulator-always-on;
79 regulator-boot-on;
80 };
81};
82
83&emmc {
84 status = "okay";
85 bus-width = <8>;
86 cap-mmc-highspeed;
87 clock-frequency = <150000000>;
88 disable-wp;
89 keep-power-in-suspend;
90 mmc-hs200-1_8v;
91 no-sdio;
92 no-sd;
93 non-removable;
94 num-slots = <1>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
97 vmmc-supply = <&vcc_io>;
98 vqmmc-supply = <&vcc18_flash>;
99};
100
101&i2c0 {
102 status = "okay";
103
104 rk808: pmic@1b {
105 compatible = "rockchip,rk808";
106 reg = <0x1b>;
107 interrupt-parent = <&gpio0>;
108 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
109 pinctrl-names = "default";
110 pinctrl-0 = <&pmic_int>, <&pmic_sleep>;
111 rockchip,system-power-controller;
112 vcc1-supply = <&vcc_sys>;
113 vcc2-supply = <&vcc_sys>;
114 vcc3-supply = <&vcc_sys>;
115 vcc4-supply = <&vcc_sys>;
116 vcc6-supply = <&vcc_sys>;
117 vcc7-supply = <&vcc_sys>;
118 vcc8-supply = <&vcc_io>;
119 vcc9-supply = <&vcc_sys>;
120 vcc10-supply = <&vcc_sys>;
121 vcc11-supply = <&vcc_sys>;
122 vcc12-supply = <&vcc_io>;
123 clock-output-names = "xin32k", "rk808-clkout2";
124 #clock-cells = <1>;
125
126 regulators {
127 vdd_cpu: DCDC_REG1 {
128 regulator-always-on;
129 regulator-boot-on;
130 regulator-min-microvolt = <700000>;
131 regulator-max-microvolt = <1500000>;
132 regulator-name = "vdd_cpu";
133 };
134
135 vdd_log: DCDC_REG2 {
136 regulator-always-on;
137 regulator-boot-on;
138 regulator-min-microvolt = <700000>;
139 regulator-max-microvolt = <1500000>;
140 regulator-name = "vdd_log";
141 };
142
143 vcc_ddr: DCDC_REG3 {
144 regulator-always-on;
145 regulator-boot-on;
146 regulator-name = "vcc_ddr";
147 };
148
149 vcc_io: DCDC_REG4 {
150 regulator-always-on;
151 regulator-boot-on;
152 regulator-min-microvolt = <3300000>;
153 regulator-max-microvolt = <3300000>;
154 regulator-name = "vcc_io";
155 };
156
157 vcc18_flash: LDO_REG1 {
158 regulator-always-on;
159 regulator-boot-on;
160 regulator-min-microvolt = <1800000>;
161 regulator-max-microvolt = <1800000>;
162 regulator-name = "vcc18_flash";
163 };
164
165 vcca_33: LDO_REG2 {
166 regulator-always-on;
167 regulator-boot-on;
168 regulator-min-microvolt = <3300000>;
169 regulator-max-microvolt = <3300000>;
170 regulator-name = "vcca_33";
171 };
172
173 vdd_10: LDO_REG3 {
174 regulator-always-on;
175 regulator-boot-on;
176 regulator-min-microvolt = <1000000>;
177 regulator-max-microvolt = <1000000>;
178 regulator-name = "vdd_10";
179 };
180
181 avdd_33: LDO_REG4 {
182 regulator-min-microvolt = <3300000>;
183 regulator-max-microvolt = <3300000>;
184 regulator-name = "avdd_33";
185 };
186
187 vccio_sd: LDO_REG5 {
188 regulator-always-on;
189 regulator-boot-on;
190 regulator-min-microvolt = <1800000>;
191 regulator-max-microvolt = <3300000>;
192 regulator-name = "vccio_sd";
193 };
194
195 vdd10_lcd: LDO_REG6 {
196 regulator-always-on;
197 regulator-boot-on;
198 regulator-min-microvolt = <1000000>;
199 regulator-max-microvolt = <1000000>;
200 regulator-name = "vdd10_lcd";
201 };
202
203 vcc_18: LDO_REG7 {
204 regulator-always-on;
205 regulator-boot-on;
206 regulator-min-microvolt = <1800000>;
207 regulator-max-microvolt = <1800000>;
208 regulator-name = "vcc_18";
209 };
210
211 vcc18_lcd: LDO_REG8 {
212 regulator-always-on;
213 regulator-boot-on;
214 regulator-min-microvolt = <1800000>;
215 regulator-max-microvolt = <1800000>;
216 regulator-name = "vcc18_lcd";
217 };
218
219 vcc_sd: SWITCH_REG1 {
220 regulator-name = "vcc_sd";
221 };
222
223 vcc33_lcd: SWITCH_REG2 {
224 regulator-always-on;
225 regulator-boot-on;
226 regulator-name = "vcc33_lcd";
227 };
228 };
229 };
230};
231
232&i2c1 {
233 status = "okay";
234
235 accelerometer@18 {
236 compatible = "bosch,bma250";
237 reg = <0x18>;
238 interrupt-parent = <&gpio2>;
239 interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
240 };
241};
242
243&i2c2 {
244 status = "okay";
245
246 gsl1680: touchscreen@40 {
247 compatible = "silead,gsl1680";
248 reg = <0x40>;
249 interrupt-parent = <&gpio3>;
250 interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
251 power-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
252 touchscreen-size-x = <800>;
253 touchscreen-size-y = <1280>;
254 silead,max-fingers = <5>;
255 };
256};
257
258&pinctrl {
259 keys {
260 pwr_key: pwr-key {
261 rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_none>;
262 };
263 };
264
265 pmic {
266 pmic_sleep: pmic-sleep {
267 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
268 };
269
270 pmic_int: pmic-int {
271 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
272 };
273 };
274};
275
276&sdmmc {
277 status = "okay";
278 bus-width = <4>;
279 cap-mmc-highspeed;
280 cap-sd-highspeed;
281 card-detect-delay = <200>;
282 no-emmc;
283 no-sdio;
284 num-slots = <1>;
285 sd-uhs-sdr12;
286 sd-uhs-sdr25;
287 pinctrl-names = "default";
288 pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_bus4>, <&sdmmc_cd>;
289 rockchip,default-sample-phase = <90>;
290 vmmc-supply = <&vcc_sd>;
291 vqmmc-supply = <&vccio_sd>;
292};
293
294&tsadc {
295 status = "okay";
296 rockchip,hw-tshut-mode = <0>; /* CRU */
297 rockchip,hw-tshut-polarity = <1>; /* high */
298};
299
300&uart4 {
301 status = "okay";
302};
303
304&usb_host0_ehci {
305 status = "okay";
306};
307
308&usb_otg {
309 status = "okay";
310};
311
312&wdt {
313 status = "okay";
314};
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index df231c4df5a5..a635adc47e74 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -231,7 +231,7 @@
231 sdmmc: dwmmc@ff0c0000 { 231 sdmmc: dwmmc@ff0c0000 {
232 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 232 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
233 reg = <0x0 0xff0c0000 0x0 0x4000>; 233 reg = <0x0 0xff0c0000 0x0 0x4000>;
234 clock-freq-min-max = <400000 150000000>; 234 max-frequency = <150000000>;
235 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 235 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
236 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 236 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
237 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 237 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
@@ -243,7 +243,7 @@
243 sdio0: dwmmc@ff0d0000 { 243 sdio0: dwmmc@ff0d0000 {
244 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 244 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
245 reg = <0x0 0xff0d0000 0x0 0x4000>; 245 reg = <0x0 0xff0d0000 0x0 0x4000>;
246 clock-freq-min-max = <400000 150000000>; 246 max-frequency = <150000000>;
247 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 247 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
248 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 248 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
249 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 249 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
@@ -255,7 +255,7 @@
255 emmc: dwmmc@ff0f0000 { 255 emmc: dwmmc@ff0f0000 {
256 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 256 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
257 reg = <0x0 0xff0f0000 0x0 0x4000>; 257 reg = <0x0 0xff0f0000 0x0 0x4000>;
258 clock-freq-min-max = <400000 150000000>; 258 max-frequency = <150000000>;
259 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 259 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
260 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 260 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
261 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 261 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
@@ -315,16 +315,16 @@
315 status = "disabled"; 315 status = "disabled";
316 }; 316 };
317 317
318 i2c1: i2c@ff140000 { 318 i2c2: i2c@ff140000 {
319 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 319 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
320 reg = <0x0 0xff140000 0x0 0x1000>; 320 reg = <0x0 0xff140000 0x0 0x1000>;
321 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 321 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
322 #address-cells = <1>; 322 #address-cells = <1>;
323 #size-cells = <0>; 323 #size-cells = <0>;
324 clock-names = "i2c"; 324 clock-names = "i2c";
325 clocks = <&cru PCLK_I2C1>; 325 clocks = <&cru PCLK_I2C2>;
326 pinctrl-names = "default"; 326 pinctrl-names = "default";
327 pinctrl-0 = <&i2c1_xfer>; 327 pinctrl-0 = <&i2c2_xfer>;
328 status = "disabled"; 328 status = "disabled";
329 }; 329 };
330 330
@@ -553,16 +553,16 @@
553 status = "disabled"; 553 status = "disabled";
554 }; 554 };
555 555
556 i2c2: i2c@ff660000 { 556 i2c1: i2c@ff660000 {
557 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 557 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
558 reg = <0x0 0xff660000 0x0 0x1000>; 558 reg = <0x0 0xff660000 0x0 0x1000>;
559 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 559 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
560 #address-cells = <1>; 560 #address-cells = <1>;
561 #size-cells = <0>; 561 #size-cells = <0>;
562 clock-names = "i2c"; 562 clock-names = "i2c";
563 clocks = <&cru PCLK_I2C2>; 563 clocks = <&cru PCLK_I2C1>;
564 pinctrl-names = "default"; 564 pinctrl-names = "default";
565 pinctrl-0 = <&i2c2_xfer>; 565 pinctrl-0 = <&i2c1_xfer>;
566 status = "disabled"; 566 status = "disabled";
567 }; 567 };
568 568
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
index 8e82497925fe..3040a989d699 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
@@ -49,6 +49,46 @@
49 compatible = "rockchip,rk3399-evb", "rockchip,rk3399", 49 compatible = "rockchip,rk3399-evb", "rockchip,rk3399",
50 "google,rk3399evb-rev2"; 50 "google,rk3399evb-rev2";
51 51
52 backlight: backlight {
53 compatible = "pwm-backlight";
54 brightness-levels = <
55 0 1 2 3 4 5 6 7
56 8 9 10 11 12 13 14 15
57 16 17 18 19 20 21 22 23
58 24 25 26 27 28 29 30 31
59 32 33 34 35 36 37 38 39
60 40 41 42 43 44 45 46 47
61 48 49 50 51 52 53 54 55
62 56 57 58 59 60 61 62 63
63 64 65 66 67 68 69 70 71
64 72 73 74 75 76 77 78 79
65 80 81 82 83 84 85 86 87
66 88 89 90 91 92 93 94 95
67 96 97 98 99 100 101 102 103
68 104 105 106 107 108 109 110 111
69 112 113 114 115 116 117 118 119
70 120 121 122 123 124 125 126 127
71 128 129 130 131 132 133 134 135
72 136 137 138 139 140 141 142 143
73 144 145 146 147 148 149 150 151
74 152 153 154 155 156 157 158 159
75 160 161 162 163 164 165 166 167
76 168 169 170 171 172 173 174 175
77 176 177 178 179 180 181 182 183
78 184 185 186 187 188 189 190 191
79 192 193 194 195 196 197 198 199
80 200 201 202 203 204 205 206 207
81 208 209 210 211 212 213 214 215
82 216 217 218 219 220 221 222 223
83 224 225 226 227 228 229 230 231
84 232 233 234 235 236 237 238 239
85 240 241 242 243 244 245 246 247
86 248 249 250 251 252 253 254 255>;
87 default-brightness-level = <200>;
88 enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
89 pwms = <&pwm0 0 25000 0>;
90 };
91
52 clkin_gmac: external-gmac-clock { 92 clkin_gmac: external-gmac-clock {
53 compatible = "fixed-clock"; 93 compatible = "fixed-clock";
54 clock-frequency = <125000000>; 94 clock-frequency = <125000000>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 1e24e455700b..c928015d39a2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -236,7 +236,7 @@
236 "rockchip,rk3288-dw-mshc"; 236 "rockchip,rk3288-dw-mshc";
237 reg = <0x0 0xfe310000 0x0 0x4000>; 237 reg = <0x0 0xfe310000 0x0 0x4000>;
238 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 238 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
239 clock-freq-min-max = <400000 150000000>; 239 max-frequency = <150000000>;
240 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 240 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
241 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 241 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
242 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 242 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
@@ -249,11 +249,12 @@
249 "rockchip,rk3288-dw-mshc"; 249 "rockchip,rk3288-dw-mshc";
250 reg = <0x0 0xfe320000 0x0 0x4000>; 250 reg = <0x0 0xfe320000 0x0 0x4000>;
251 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 251 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
252 clock-freq-min-max = <400000 150000000>; 252 max-frequency = <150000000>;
253 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 253 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
254 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 254 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
255 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 255 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
256 fifo-depth = <0x100>; 256 fifo-depth = <0x100>;
257 power-domains = <&power RK3399_PD_SD>;
257 status = "disabled"; 258 status = "disabled";
258 }; 259 };
259 260
@@ -270,6 +271,7 @@
270 #clock-cells = <0>; 271 #clock-cells = <0>;
271 phys = <&emmc_phy>; 272 phys = <&emmc_phy>;
272 phy-names = "phy_arasan"; 273 phy-names = "phy_arasan";
274 power-domains = <&power RK3399_PD_EMMC>;
273 status = "disabled"; 275 status = "disabled";
274 }; 276 };
275 277
@@ -694,6 +696,16 @@
694 status = "disabled"; 696 status = "disabled";
695 }; 697 };
696 698
699 qos_sd: qos@ffa74000 {
700 compatible = "syscon";
701 reg = <0x0 0xffa74000 0x0 0x20>;
702 };
703
704 qos_emmc: qos@ffa58000 {
705 compatible = "syscon";
706 reg = <0x0 0xffa58000 0x0 0x20>;
707 };
708
697 qos_gmac: qos@ffa5c000 { 709 qos_gmac: qos@ffa5c000 {
698 compatible = "syscon"; 710 compatible = "syscon";
699 reg = <0x0 0xffa5c000 0x0 0x20>; 711 reg = <0x0 0xffa5c000 0x0 0x20>;
@@ -827,11 +839,23 @@
827 }; 839 };
828 840
829 /* These power domains are grouped by VD_LOGIC */ 841 /* These power domains are grouped by VD_LOGIC */
842 pd_emmc@RK3399_PD_EMMC {
843 reg = <RK3399_PD_EMMC>;
844 clocks = <&cru ACLK_EMMC>;
845 pm_qos = <&qos_emmc>;
846 };
830 pd_gmac@RK3399_PD_GMAC { 847 pd_gmac@RK3399_PD_GMAC {
831 reg = <RK3399_PD_GMAC>; 848 reg = <RK3399_PD_GMAC>;
832 clocks = <&cru ACLK_GMAC>; 849 clocks = <&cru ACLK_GMAC>,
850 <&cru PCLK_GMAC>;
833 pm_qos = <&qos_gmac>; 851 pm_qos = <&qos_gmac>;
834 }; 852 };
853 pd_sd@RK3399_PD_SD {
854 reg = <RK3399_PD_SD>;
855 clocks = <&cru HCLK_SDMMC>,
856 <&cru SCLK_SDMMC>;
857 pm_qos = <&qos_sd>;
858 };
835 pd_vio@RK3399_PD_VIO { 859 pd_vio@RK3399_PD_VIO {
836 reg = <RK3399_PD_VIO>; 860 reg = <RK3399_PD_VIO>;
837 #address-cells = <1>; 861 #address-cells = <1>;
@@ -1027,6 +1051,9 @@
1027 clock-names = "pclk_efuse"; 1051 clock-names = "pclk_efuse";
1028 1052
1029 /* Data cells */ 1053 /* Data cells */
1054 cpu_id: cpu-id@7 {
1055 reg = <0x07 0x10>;
1056 };
1030 cpub_leakage: cpu-leakage@17 { 1057 cpub_leakage: cpu-leakage@17 {
1031 reg = <0x17 0x1>; 1058 reg = <0x17 0x1>;
1032 }; 1059 };
@@ -1105,6 +1132,16 @@
1105 interrupt-names = "linestate"; 1132 interrupt-names = "linestate";
1106 status = "disabled"; 1133 status = "disabled";
1107 }; 1134 };
1135
1136 u2phy0_otg: otg-port {
1137 #phy-cells = <0>;
1138 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1139 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1140 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1141 interrupt-names = "otg-bvalid", "otg-id",
1142 "linestate";
1143 status = "disabled";
1144 };
1108 }; 1145 };
1109 1146
1110 u2phy1: usb2-phy@e460 { 1147 u2phy1: usb2-phy@e460 {
@@ -1122,6 +1159,16 @@
1122 interrupt-names = "linestate"; 1159 interrupt-names = "linestate";
1123 status = "disabled"; 1160 status = "disabled";
1124 }; 1161 };
1162
1163 u2phy1_otg: otg-port {
1164 #phy-cells = <0>;
1165 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1166 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1167 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1168 interrupt-names = "otg-bvalid", "otg-id",
1169 "linestate";
1170 status = "disabled";
1171 };
1125 }; 1172 };
1126 1173
1127 emmc_phy: phy@f780 { 1174 emmc_phy: phy@f780 {
@@ -1152,6 +1199,7 @@
1152 clock-names = "tcpdcore", "tcpdphy-ref"; 1199 clock-names = "tcpdcore", "tcpdphy-ref";
1153 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1200 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1154 assigned-clock-rates = <50000000>; 1201 assigned-clock-rates = <50000000>;
1202 power-domains = <&power RK3399_PD_TCPD0>;
1155 resets = <&cru SRST_UPHY0>, 1203 resets = <&cru SRST_UPHY0>,
1156 <&cru SRST_UPHY0_PIPE_L00>, 1204 <&cru SRST_UPHY0_PIPE_L00>,
1157 <&cru SRST_P_UPHY0_TCPHY>; 1205 <&cru SRST_P_UPHY0_TCPHY>;
@@ -1180,6 +1228,7 @@
1180 clock-names = "tcpdcore", "tcpdphy-ref"; 1228 clock-names = "tcpdcore", "tcpdphy-ref";
1181 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1229 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1182 assigned-clock-rates = <50000000>; 1230 assigned-clock-rates = <50000000>;
1231 power-domains = <&power RK3399_PD_TCPD1>;
1183 resets = <&cru SRST_UPHY1>, 1232 resets = <&cru SRST_UPHY1>,
1184 <&cru SRST_UPHY1_PIPE_L00>, 1233 <&cru SRST_UPHY1_PIPE_L00>,
1185 <&cru SRST_P_UPHY1_TCPHY>; 1234 <&cru SRST_P_UPHY1_TCPHY>;
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index 3eb4c42ce7b9..7c7511b9d231 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -43,7 +43,7 @@
43 * OTHER DEALINGS IN THE SOFTWARE. 43 * OTHER DEALINGS IN THE SOFTWARE.
44 */ 44 */
45 45
46/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ 46/memreserve/ 0x80000000 0x00080000;
47 47
48/ { 48/ {
49 compatible = "socionext,uniphier-ld11"; 49 compatible = "socionext,uniphier-ld11";
@@ -70,19 +70,60 @@
70 device_type = "cpu"; 70 device_type = "cpu";
71 compatible = "arm,cortex-a53", "arm,armv8"; 71 compatible = "arm,cortex-a53", "arm,armv8";
72 reg = <0 0x000>; 72 reg = <0 0x000>;
73 enable-method = "spin-table"; 73 clocks = <&sys_clk 33>;
74 cpu-release-addr = <0 0x80000000>; 74 enable-method = "psci";
75 operating-points-v2 = <&cluster0_opp>;
75 }; 76 };
76 77
77 cpu1: cpu@1 { 78 cpu1: cpu@1 {
78 device_type = "cpu"; 79 device_type = "cpu";
79 compatible = "arm,cortex-a53", "arm,armv8"; 80 compatible = "arm,cortex-a53", "arm,armv8";
80 reg = <0 0x001>; 81 reg = <0 0x001>;
81 enable-method = "spin-table"; 82 clocks = <&sys_clk 33>;
82 cpu-release-addr = <0 0x80000000>; 83 enable-method = "psci";
84 operating-points-v2 = <&cluster0_opp>;
83 }; 85 };
84 }; 86 };
85 87
88 cluster0_opp: opp_table {
89 compatible = "operating-points-v2";
90 opp-shared;
91
92 opp@245000000 {
93 opp-hz = /bits/ 64 <245000000>;
94 clock-latency-ns = <300>;
95 };
96 opp@250000000 {
97 opp-hz = /bits/ 64 <250000000>;
98 clock-latency-ns = <300>;
99 };
100 opp@490000000 {
101 opp-hz = /bits/ 64 <490000000>;
102 clock-latency-ns = <300>;
103 };
104 opp@500000000 {
105 opp-hz = /bits/ 64 <500000000>;
106 clock-latency-ns = <300>;
107 };
108 opp@653334000 {
109 opp-hz = /bits/ 64 <653334000>;
110 clock-latency-ns = <300>;
111 };
112 opp@666667000 {
113 opp-hz = /bits/ 64 <666667000>;
114 clock-latency-ns = <300>;
115 };
116 opp@980000000 {
117 opp-hz = /bits/ 64 <980000000>;
118 clock-latency-ns = <300>;
119 };
120 };
121
122 psci {
123 compatible = "arm,psci-1.0";
124 method = "smc";
125 };
126
86 clocks { 127 clocks {
87 refclk: ref { 128 refclk: ref {
88 compatible = "fixed-clock"; 129 compatible = "fixed-clock";
@@ -233,7 +274,7 @@
233 }; 274 };
234 275
235 perictrl@59820000 { 276 perictrl@59820000 {
236 compatible = "socionext,uniphier-perictrl", 277 compatible = "socionext,uniphier-ld11-perictrl",
237 "simple-mfd", "syscon"; 278 "simple-mfd", "syscon";
238 reg = <0x59820000 0x200>; 279 reg = <0x59820000 0x200>;
239 280
@@ -282,7 +323,7 @@
282 }; 323 };
283 324
284 mioctrl@5b3e0000 { 325 mioctrl@5b3e0000 {
285 compatible = "socionext,uniphier-mioctrl", 326 compatible = "socionext,uniphier-ld11-mioctrl",
286 "simple-mfd", "syscon"; 327 "simple-mfd", "syscon";
287 reg = <0x5b3e0000 0x800>; 328 reg = <0x5b3e0000 0x800>;
288 329
@@ -299,7 +340,7 @@
299 }; 340 };
300 341
301 soc-glue@5f800000 { 342 soc-glue@5f800000 {
302 compatible = "socionext,uniphier-soc-glue", 343 compatible = "socionext,uniphier-ld11-soc-glue",
303 "simple-mfd", "syscon"; 344 "simple-mfd", "syscon";
304 reg = <0x5f800000 0x2000>; 345 reg = <0x5f800000 0x2000>;
305 346
@@ -320,7 +361,7 @@
320 sysctrl@61840000 { 361 sysctrl@61840000 {
321 compatible = "socionext,uniphier-ld11-sysctrl", 362 compatible = "socionext,uniphier-ld11-sysctrl",
322 "simple-mfd", "syscon"; 363 "simple-mfd", "syscon";
323 reg = <0x61840000 0x4000>; 364 reg = <0x61840000 0x10000>;
324 365
325 sys_clk: clock { 366 sys_clk: clock {
326 compatible = "socionext,uniphier-ld11-clock"; 367 compatible = "socionext,uniphier-ld11-clock";
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 56a1b2e92cf3..fcaecc6bdeac 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -43,7 +43,7 @@
43 * OTHER DEALINGS IN THE SOFTWARE. 43 * OTHER DEALINGS IN THE SOFTWARE.
44 */ 44 */
45 45
46/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ 46/memreserve/ 0x80000000 0x00080000;
47 47
48/ { 48/ {
49 compatible = "socionext,uniphier-ld20"; 49 compatible = "socionext,uniphier-ld20";
@@ -79,35 +79,120 @@
79 device_type = "cpu"; 79 device_type = "cpu";
80 compatible = "arm,cortex-a72", "arm,armv8"; 80 compatible = "arm,cortex-a72", "arm,armv8";
81 reg = <0 0x000>; 81 reg = <0 0x000>;
82 enable-method = "spin-table"; 82 clocks = <&sys_clk 32>;
83 cpu-release-addr = <0 0x80000000>; 83 enable-method = "psci";
84 operating-points-v2 = <&cluster0_opp>;
84 }; 85 };
85 86
86 cpu1: cpu@1 { 87 cpu1: cpu@1 {
87 device_type = "cpu"; 88 device_type = "cpu";
88 compatible = "arm,cortex-a72", "arm,armv8"; 89 compatible = "arm,cortex-a72", "arm,armv8";
89 reg = <0 0x001>; 90 reg = <0 0x001>;
90 enable-method = "spin-table"; 91 clocks = <&sys_clk 32>;
91 cpu-release-addr = <0 0x80000000>; 92 enable-method = "psci";
93 operating-points-v2 = <&cluster0_opp>;
92 }; 94 };
93 95
94 cpu2: cpu@100 { 96 cpu2: cpu@100 {
95 device_type = "cpu"; 97 device_type = "cpu";
96 compatible = "arm,cortex-a53", "arm,armv8"; 98 compatible = "arm,cortex-a53", "arm,armv8";
97 reg = <0 0x100>; 99 reg = <0 0x100>;
98 enable-method = "spin-table"; 100 clocks = <&sys_clk 33>;
99 cpu-release-addr = <0 0x80000000>; 101 enable-method = "psci";
102 operating-points-v2 = <&cluster1_opp>;
100 }; 103 };
101 104
102 cpu3: cpu@101 { 105 cpu3: cpu@101 {
103 device_type = "cpu"; 106 device_type = "cpu";
104 compatible = "arm,cortex-a53", "arm,armv8"; 107 compatible = "arm,cortex-a53", "arm,armv8";
105 reg = <0 0x101>; 108 reg = <0 0x101>;
106 enable-method = "spin-table"; 109 clocks = <&sys_clk 33>;
107 cpu-release-addr = <0 0x80000000>; 110 enable-method = "psci";
111 operating-points-v2 = <&cluster1_opp>;
108 }; 112 };
109 }; 113 };
110 114
115 cluster0_opp: opp_table0 {
116 compatible = "operating-points-v2";
117 opp-shared;
118
119 opp@250000000 {
120 opp-hz = /bits/ 64 <250000000>;
121 clock-latency-ns = <300>;
122 };
123 opp@275000000 {
124 opp-hz = /bits/ 64 <275000000>;
125 clock-latency-ns = <300>;
126 };
127 opp@500000000 {
128 opp-hz = /bits/ 64 <500000000>;
129 clock-latency-ns = <300>;
130 };
131 opp@550000000 {
132 opp-hz = /bits/ 64 <550000000>;
133 clock-latency-ns = <300>;
134 };
135 opp@666667000 {
136 opp-hz = /bits/ 64 <666667000>;
137 clock-latency-ns = <300>;
138 };
139 opp@733334000 {
140 opp-hz = /bits/ 64 <733334000>;
141 clock-latency-ns = <300>;
142 };
143 opp@1000000000 {
144 opp-hz = /bits/ 64 <1000000000>;
145 clock-latency-ns = <300>;
146 };
147 opp@1100000000 {
148 opp-hz = /bits/ 64 <1100000000>;
149 clock-latency-ns = <300>;
150 };
151 };
152
153 cluster1_opp: opp_table1 {
154 compatible = "operating-points-v2";
155 opp-shared;
156
157 opp@250000000 {
158 opp-hz = /bits/ 64 <250000000>;
159 clock-latency-ns = <300>;
160 };
161 opp@275000000 {
162 opp-hz = /bits/ 64 <275000000>;
163 clock-latency-ns = <300>;
164 };
165 opp@500000000 {
166 opp-hz = /bits/ 64 <500000000>;
167 clock-latency-ns = <300>;
168 };
169 opp@550000000 {
170 opp-hz = /bits/ 64 <550000000>;
171 clock-latency-ns = <300>;
172 };
173 opp@666667000 {
174 opp-hz = /bits/ 64 <666667000>;
175 clock-latency-ns = <300>;
176 };
177 opp@733334000 {
178 opp-hz = /bits/ 64 <733334000>;
179 clock-latency-ns = <300>;
180 };
181 opp@1000000000 {
182 opp-hz = /bits/ 64 <1000000000>;
183 clock-latency-ns = <300>;
184 };
185 opp@1100000000 {
186 opp-hz = /bits/ 64 <1100000000>;
187 clock-latency-ns = <300>;
188 };
189 };
190
191 psci {
192 compatible = "arm,psci-1.0";
193 method = "smc";
194 };
195
111 clocks { 196 clocks {
112 refclk: ref { 197 refclk: ref {
113 compatible = "fixed-clock"; 198 compatible = "fixed-clock";
@@ -274,7 +359,7 @@
274 }; 359 };
275 360
276 perictrl@59820000 { 361 perictrl@59820000 {
277 compatible = "socionext,uniphier-perictrl", 362 compatible = "socionext,uniphier-ld20-perictrl",
278 "simple-mfd", "syscon"; 363 "simple-mfd", "syscon";
279 reg = <0x59820000 0x200>; 364 reg = <0x59820000 0x200>;
280 365
@@ -290,7 +375,7 @@
290 }; 375 };
291 376
292 soc-glue@5f800000 { 377 soc-glue@5f800000 {
293 compatible = "socionext,uniphier-soc-glue", 378 compatible = "socionext,uniphier-ld20-soc-glue",
294 "simple-mfd", "syscon"; 379 "simple-mfd", "syscon";
295 reg = <0x5f800000 0x2000>; 380 reg = <0x5f800000 0x2000>;
296 381
@@ -309,9 +394,9 @@
309 }; 394 };
310 395
311 sysctrl@61840000 { 396 sysctrl@61840000 {
312 compatible = "socionext,uniphier-sysctrl", 397 compatible = "socionext,uniphier-ld20-sysctrl",
313 "simple-mfd", "syscon"; 398 "simple-mfd", "syscon";
314 reg = <0x61840000 0x4000>; 399 reg = <0x61840000 0x10000>;
315 400
316 sys_clk: clock { 401 sys_clk: clock {
317 compatible = "socionext,uniphier-ld20-clock"; 402 compatible = "socionext,uniphier-ld20-clock";
diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi
index dd2cd73c774c..88ff70a06086 100644
--- a/arch/arm64/boot/dts/zte/zx296718.dtsi
+++ b/arch/arm64/boot/dts/zte/zx296718.dtsi
@@ -277,9 +277,33 @@
277 dma-requests = <32>; 277 dma-requests = <32>;
278 }; 278 };
279 279
280 lsp0crm: clock-controller@1420000 {
281 compatible = "zte,zx296718-lsp0crm";
282 reg = <0x01420000 0x1000>;
283 #clock-cells = <1>;
284 };
285
286 lsp1crm: clock-controller@1430000 {
287 compatible = "zte,zx296718-lsp1crm";
288 reg = <0x01430000 0x1000>;
289 #clock-cells = <1>;
290 };
291
292 topcrm: clock-controller@1461000 {
293 compatible = "zte,zx296718-topcrm";
294 reg = <0x01461000 0x1000>;
295 #clock-cells = <1>;
296 };
297
280 sysctrl: sysctrl@1463000 { 298 sysctrl: sysctrl@1463000 {
281 compatible = "zte,zx296718-sysctrl", "syscon"; 299 compatible = "zte,zx296718-sysctrl", "syscon";
282 reg = <0x1463000 0x1000>; 300 reg = <0x1463000 0x1000>;
283 }; 301 };
302
303 audiocrm: clock-controller@1480000 {
304 compatible = "zte,zx296718-audiocrm";
305 reg = <0x01480000 0x1000>;
306 #clock-cells = <1>;
307 };
284 }; 308 };
285}; 309};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 15:45:28 -0400