Documentation: dt: socfpga: Add interrupt-controller to ecc-manager

Designate the ECC Manager as an interrupt controller and add child
interrupts.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: ijc+devicetree@hellion.org.uk
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-doc@vger.kernel.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1464193783-5071-2-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>

1 files changed, 13 insertions, 1 deletions

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
index 5a6b16070a33..15eb0df1d36e 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
@@ -61,7 +61,9 @@ Required Properties:
 - #address-cells: must be 1
 - #size-cells: must be 1
 - interrupts : Should be single bit error interrupt, then double bit error
-        interrupt. Note the rising edge type.
+        interrupt.
+- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
+- #interrupt-cells : must be set to 2.
 - ranges : standard definition, should translate from local addresses
 
 Subcomponents:
@@ -70,11 +72,15 @@ L2 Cache ECC
 Required Properties:
 - compatible : Should be "altr,socfpga-a10-l2-ecc"
 - reg : Address and size for ECC error interrupt clear registers.
+- interrupts : Should be single bit error interrupt, then double bit error
+        interrupt, in this order.
 
 On-Chip RAM ECC
 Required Properties:
 - compatible : Should be "altr,socfpga-a10-ocram-ecc"
 - reg        : Address and size for ECC block registers.
+- interrupts : Should be single bit error interrupt, then double bit error
+        interrupt, in this order.
 
 Example:
 
@@ -85,15 +91,21 @@ Example:
                 #size-cells = <1>;
                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
                              <0 0 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
                 ranges;
 
                 l2-ecc@ffd06010 {
                         compatible = "altr,socfpga-a10-l2-ecc";
                         reg = <0xffd06010 0x4>;
+                        interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
+                                     <32 IRQ_TYPE_LEVEL_HIGH>;
                 };
 
                 ocram-ecc@ff8c3000 {
                         compatible = "altr,socfpga-a10-ocram-ecc";
                         reg = <0xff8c3000 0x90>;
+                        interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
+                                     <33 IRQ_TYPE_LEVEL_HIGH> ;
                 };
         };