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authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>2017-04-01 09:59:22 -0400
committerLinus Walleij <linus.walleij@linaro.org>2017-04-07 03:30:39 -0400
commit4781c22c7691140b2d945cb663d3b7b03319e07c (patch)
tree48f2d10268b0a8a9f28cc818e49b897150218d5b
parent97ba26b8a9343008504d4e3a87d212bc07b05212 (diff)
pinctrl: meson: meson8b: rename the NAND DQS pin definitions
The NAND DQS pins are currently named nand_dqs_0 and nand_dqs_1. However, they both seem to have the same function, just exposed on different pins (unlike the ethernet TX pins for example, where there's eth_txd0..3 - all of these can be active at the same time as they are different data lines). Rename the NAND DQS pins to nand_dqs_15 and nand_dqs_18 to reflect that it's the same functionality just exposed on different pins (BOOT_15 and BOOT_18). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson8b.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/pinctrl/meson/pinctrl-meson8b.c b/drivers/pinctrl/meson/pinctrl-meson8b.c
index f87ef5a0ee6c..bf747eb1f3f4 100644
--- a/drivers/pinctrl/meson/pinctrl-meson8b.c
+++ b/drivers/pinctrl/meson/pinctrl-meson8b.c
@@ -267,8 +267,8 @@ static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, 0) };
267static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, 0) }; 267static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, 0) };
268static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, 0) }; 268static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, 0) };
269static const unsigned int nand_ren_clk_pins[] = { PIN(BOOT_14, 0) }; 269static const unsigned int nand_ren_clk_pins[] = { PIN(BOOT_14, 0) };
270static const unsigned int nand_dqs_0_pins[] = { PIN(BOOT_15, 0) }; 270static const unsigned int nand_dqs_15_pins[] = { PIN(BOOT_15, 0) };
271static const unsigned int nand_dqs_1_pins[] = { PIN(BOOT_18, 0) }; 271static const unsigned int nand_dqs_18_pins[] = { PIN(BOOT_18, 0) };
272 272
273static const unsigned int sdxc_d0_c_pins[] = { PIN(BOOT_0, 0)}; 273static const unsigned int sdxc_d0_c_pins[] = { PIN(BOOT_0, 0)};
274static const unsigned int sdxc_d13_c_pins[] = { PIN(BOOT_1, 0), PIN(BOOT_2, 0), 274static const unsigned int sdxc_d13_c_pins[] = { PIN(BOOT_1, 0), PIN(BOOT_2, 0),
@@ -527,8 +527,8 @@ static struct meson_pmx_group meson8b_cbus_groups[] = {
527 GROUP(nand_cle, 2, 20), 527 GROUP(nand_cle, 2, 20),
528 GROUP(nand_wen_clk, 2, 19), 528 GROUP(nand_wen_clk, 2, 19),
529 GROUP(nand_ren_clk, 2, 18), 529 GROUP(nand_ren_clk, 2, 18),
530 GROUP(nand_dqs_0, 2, 27), 530 GROUP(nand_dqs_15, 2, 27),
531 GROUP(nand_dqs_1, 2, 28), 531 GROUP(nand_dqs_18, 2, 28),
532 GROUP(sdxc_d0_c, 4, 30), 532 GROUP(sdxc_d0_c, 4, 30),
533 GROUP(sdxc_d13_c, 4, 29), 533 GROUP(sdxc_d13_c, 4, 29),
534 GROUP(sdxc_d47_c, 4, 28), 534 GROUP(sdxc_d47_c, 4, 28),
@@ -739,8 +739,8 @@ static const char * const sdxc_c_groups[] = {
739static const char * const nand_groups[] = { 739static const char * const nand_groups[] = {
740 "nand_io", "nand_io_ce0", "nand_io_ce1", 740 "nand_io", "nand_io_ce0", "nand_io_ce1",
741 "nand_io_rb0", "nand_ale", "nand_cle", 741 "nand_io_rb0", "nand_ale", "nand_cle",
742 "nand_wen_clk", "nand_ren_clk", "nand_dqs_0", 742 "nand_wen_clk", "nand_ren_clk", "nand_dqs_15",
743 "nand_dqs_1" 743 "nand_dqs_18"
744}; 744};
745 745
746static const char * const nor_groups[] = { 746static const char * const nor_groups[] = {