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authorThierry Reding <treding@nvidia.com>2018-09-21 06:27:44 -0400
committerThierry Reding <treding@nvidia.com>2018-09-26 10:04:39 -0400
commit474431968507d437d340de35b709aa3b41f8c996 (patch)
tree049e9da21ef5d009aa086f0c09a73bd5509fcebd
parent5725daaab55ca023c87ff0f1b2dbf6bf9b38376d (diff)
drm/tegra: dc: Add Tegra194 support
The display controllers found on Tegra194 are almost identical to those found on Tegra186. Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--drivers/gpu/drm/tegra/dc.c51
-rw-r--r--drivers/gpu/drm/tegra/dc.h2
-rw-r--r--drivers/gpu/drm/tegra/drm.c1
3 files changed, 53 insertions, 1 deletions
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index 7e36ca204cbb..f80e82e16475 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -2256,8 +2256,59 @@ static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
2256 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps), 2256 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
2257}; 2257};
2258 2258
2259static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = {
2260 {
2261 .index = 0,
2262 .dc = 0,
2263 .windows = (const unsigned int[]) { 0 },
2264 .num_windows = 1,
2265 }, {
2266 .index = 1,
2267 .dc = 1,
2268 .windows = (const unsigned int[]) { 1 },
2269 .num_windows = 1,
2270 }, {
2271 .index = 2,
2272 .dc = 1,
2273 .windows = (const unsigned int[]) { 2 },
2274 .num_windows = 1,
2275 }, {
2276 .index = 3,
2277 .dc = 2,
2278 .windows = (const unsigned int[]) { 3 },
2279 .num_windows = 1,
2280 }, {
2281 .index = 4,
2282 .dc = 2,
2283 .windows = (const unsigned int[]) { 4 },
2284 .num_windows = 1,
2285 }, {
2286 .index = 5,
2287 .dc = 2,
2288 .windows = (const unsigned int[]) { 5 },
2289 .num_windows = 1,
2290 },
2291};
2292
2293static const struct tegra_dc_soc_info tegra194_dc_soc_info = {
2294 .supports_background_color = true,
2295 .supports_interlacing = true,
2296 .supports_cursor = true,
2297 .supports_block_linear = true,
2298 .has_legacy_blending = false,
2299 .pitch_align = 64,
2300 .has_powergate = false,
2301 .coupled_pm = false,
2302 .has_nvdisplay = true,
2303 .wgrps = tegra194_dc_wgrps,
2304 .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps),
2305};
2306
2259static const struct of_device_id tegra_dc_of_match[] = { 2307static const struct of_device_id tegra_dc_of_match[] = {
2260 { 2308 {
2309 .compatible = "nvidia,tegra194-dc",
2310 .data = &tegra194_dc_soc_info,
2311 }, {
2261 .compatible = "nvidia,tegra186-dc", 2312 .compatible = "nvidia,tegra186-dc",
2262 .data = &tegra186_dc_soc_info, 2313 .data = &tegra186_dc_soc_info,
2263 }, { 2314 }, {
diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h
index e96f582ca692..1256dfb6b2f5 100644
--- a/drivers/gpu/drm/tegra/dc.h
+++ b/drivers/gpu/drm/tegra/dc.h
@@ -300,7 +300,7 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
300#define SOR1_TIMING_CYA (1 << 27) 300#define SOR1_TIMING_CYA (1 << 27)
301#define CURSOR_ENABLE (1 << 16) 301#define CURSOR_ENABLE (1 << 16)
302 302
303#define SOR_ENABLE(x) (1 << (25 + (x))) 303#define SOR_ENABLE(x) (1 << (25 + (((x) > 1) ? ((x) + 1) : (x))))
304 304
305#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403 305#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
306#define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24) 306#define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24)
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 4e40ffd2b32e..0ed6fa8ac446 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -1256,6 +1256,7 @@ static const struct of_device_id host1x_drm_subdevs[] = {
1256 { .compatible = "nvidia,tegra186-sor1", }, 1256 { .compatible = "nvidia,tegra186-sor1", },
1257 { .compatible = "nvidia,tegra186-vic", }, 1257 { .compatible = "nvidia,tegra186-vic", },
1258 { .compatible = "nvidia,tegra194-display", }, 1258 { .compatible = "nvidia,tegra194-display", },
1259 { .compatible = "nvidia,tegra194-dc", },
1259 { /* sentinel */ } 1260 { /* sentinel */ }
1260}; 1261};
1261 1262