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authorThierry Reding <treding@nvidia.com>2015-08-05 10:39:55 -0400
committerThierry Reding <treding@nvidia.com>2015-08-13 07:47:43 -0400
commit472a6d1fd5f5d37a1c081e69f5c8ad5307ac358f (patch)
tree3da9416145eec9bccb8b7635e73da97da0d409ed
parent76ac3284bb708545e762091ba5d6d0f0dbc008bc (diff)
drm/tegra: dc: Rename BASE_COLOR_SIZE* fields
Use an underscore to separate the prefix from the color size suffix. Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--drivers/gpu/drm/tegra/dc.h9
-rw-r--r--drivers/gpu/drm/tegra/hdmi.c2
2 files changed, 10 insertions, 1 deletions
diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h
index 87700bf60108..203056a378f0 100644
--- a/drivers/gpu/drm/tegra/dc.h
+++ b/drivers/gpu/drm/tegra/dc.h
@@ -250,6 +250,15 @@
250#define DITHER_CONTROL_DISABLE (0 << 8) 250#define DITHER_CONTROL_DISABLE (0 << 8)
251#define DITHER_CONTROL_ORDERED (2 << 8) 251#define DITHER_CONTROL_ORDERED (2 << 8)
252#define DITHER_CONTROL_ERRDIFF (3 << 8) 252#define DITHER_CONTROL_ERRDIFF (3 << 8)
253#define BASE_COLOR_SIZE_666 (0 << 0)
254#define BASE_COLOR_SIZE_111 (1 << 0)
255#define BASE_COLOR_SIZE_222 (2 << 0)
256#define BASE_COLOR_SIZE_333 (3 << 0)
257#define BASE_COLOR_SIZE_444 (4 << 0)
258#define BASE_COLOR_SIZE_555 (5 << 0)
259#define BASE_COLOR_SIZE_565 (6 << 0)
260#define BASE_COLOR_SIZE_332 (7 << 0)
261#define BASE_COLOR_SIZE_888 (8 << 0)
253 262
254#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431 263#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
255#define SC1_H_QUALIFIER_NONE (1 << 16) 264#define SC1_H_QUALIFIER_NONE (1 << 16)
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
index 58f0cff65ff8..0749308f4203 100644
--- a/drivers/gpu/drm/tegra/hdmi.c
+++ b/drivers/gpu/drm/tegra/hdmi.c
@@ -872,7 +872,7 @@ static void tegra_hdmi_encoder_mode_set(struct drm_encoder *encoder,
872 872
873 tegra_dc_writel(dc, VSYNC_H_POSITION(1), 873 tegra_dc_writel(dc, VSYNC_H_POSITION(1),
874 DC_DISP_DISP_TIMING_OPTIONS); 874 DC_DISP_DISP_TIMING_OPTIONS);
875 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888, 875 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
876 DC_DISP_DISP_COLOR_CONTROL); 876 DC_DISP_DISP_COLOR_CONTROL);
877 877
878 /* video_preamble uses h_pulse2 */ 878 /* video_preamble uses h_pulse2 */