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authorAndrzej Hajda <a.hajda@samsung.com>2016-03-23 09:15:12 -0400
committerInki Dae <daeinki@gmail.com>2016-04-29 12:03:54 -0400
commit4677f51ade432987f01062abad9e4cf60fd33f7d (patch)
tree69e4da85beda6745dab2033fb23790e504a7edd6
parent50ec220eb4e3c90b3d7d40c679e19a0b61de162c (diff)
drm/exynos/hdmi: fix PHY configuration sequence
Proper PHY configuration should be as follow: 1. set HDMI clock parents to OSCCLK. 2. reconfigure PHY. 3. set HDMI clock parents to PHY. 4. wait for PLL stabilization. The patch fixes it and consolidates the code. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
-rw-r--r--drivers/gpu/drm/exynos/exynos_hdmi.c22
1 files changed, 11 insertions, 11 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 06105feb6c87..8faf3151242a 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -1654,15 +1654,11 @@ static void hdmi_mode_apply(struct hdmi_context *hdata)
1654 else 1654 else
1655 hdmi_v14_mode_apply(hdata); 1655 hdmi_v14_mode_apply(hdata);
1656 1656
1657 hdmiphy_wait_for_pll(hdata);
1658 hdmi_clk_set_parents(hdata, true);
1659 hdmi_start(hdata, true); 1657 hdmi_start(hdata, true);
1660} 1658}
1661 1659
1662static void hdmiphy_conf_reset(struct hdmi_context *hdata) 1660static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1663{ 1661{
1664 hdmi_clk_set_parents(hdata, false);
1665
1666 hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT); 1662 hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT);
1667 usleep_range(10000, 12000); 1663 usleep_range(10000, 12000);
1668 hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, 0, HDMI_PHY_SW_RSTOUT); 1664 hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, 0, HDMI_PHY_SW_RSTOUT);
@@ -1680,29 +1676,33 @@ static void hdmiphy_enable_mode_set(struct hdmi_context *hdata, bool enable)
1680static void hdmiphy_conf_apply(struct hdmi_context *hdata) 1676static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1681{ 1677{
1682 int ret; 1678 int ret;
1683 int i; 1679 const u8 *phy_conf;
1684 1680
1685 i = hdmi_find_phy_conf(hdata, hdata->current_mode.clock * 1000); 1681 ret = hdmi_find_phy_conf(hdata, hdata->current_mode.clock * 1000);
1686 if (i < 0) { 1682 if (ret < 0) {
1687 DRM_ERROR("failed to find hdmiphy conf\n"); 1683 DRM_ERROR("failed to find hdmiphy conf\n");
1688 return; 1684 return;
1689 } 1685 }
1686 phy_conf = hdata->drv_data->phy_confs.data[ret].conf;
1687
1688 hdmi_clk_set_parents(hdata, false);
1689
1690 hdmiphy_conf_reset(hdata);
1690 1691
1691 hdmiphy_enable_mode_set(hdata, true); 1692 hdmiphy_enable_mode_set(hdata, true);
1692 ret = hdmiphy_reg_write_buf(hdata, 0, 1693 ret = hdmiphy_reg_write_buf(hdata, 0, phy_conf, 32);
1693 hdata->drv_data->phy_confs.data[i].conf, 32);
1694 if (ret) { 1694 if (ret) {
1695 DRM_ERROR("failed to configure hdmiphy\n"); 1695 DRM_ERROR("failed to configure hdmiphy\n");
1696 return; 1696 return;
1697 } 1697 }
1698 hdmiphy_enable_mode_set(hdata, false); 1698 hdmiphy_enable_mode_set(hdata, false);
1699 1699 hdmi_clk_set_parents(hdata, true);
1700 usleep_range(10000, 12000); 1700 usleep_range(10000, 12000);
1701 hdmiphy_wait_for_pll(hdata);
1701} 1702}
1702 1703
1703static void hdmi_conf_apply(struct hdmi_context *hdata) 1704static void hdmi_conf_apply(struct hdmi_context *hdata)
1704{ 1705{
1705 hdmiphy_conf_reset(hdata);
1706 hdmiphy_conf_apply(hdata); 1706 hdmiphy_conf_apply(hdata);
1707 hdmi_start(hdata, false); 1707 hdmi_start(hdata, false);
1708 hdmi_conf_init(hdata); 1708 hdmi_conf_init(hdata);