Merge tag 'mvebu-dt64-4.13-1' of git://git.infradead.org/linux-mvebu into next/dt64

mvebu dt64 for 4.13 (part 1)

- Improve the mcbin support (Armada 8040 based board): add sdhci and
  the second 1G port
- Improve crypro nodes description on Aramda 7K/8K
- Use new binding for ap806 clocks
- Improve mdio nodes and add xmdio on Aramda 7K/8K
- Add second SGCI node on Armada 37xx
- Improve the description of the Armada 3720 DB board

* tag 'mvebu-dt64-4.13-1' of git://git.infradead.org/linux-mvebu:
  arm64: dts: marvell: add xmdio nodes for 7k/8k
  arm64: dts: marvell: add a comment on the cp110 slave node status
  arm64: dts: marvell: remove cpm crypto nodes from dts files
  arm64: dts: marvell: cp110: enable the crypto engine at the SoC level
  arm64: dts: marvell: armada-3720-db: Add vqmmc regulator for SD slot
  arm64: dts: marvell: Enable second SDHCI controller in Armada 37xx
  arm64: dts: marvell: armada-37xx: Use angle bracket for each register set
  arm64: dts: marvell: armada-37xx: Align the compatible string
  arm64: dts: marvell: armada-3720-db: Add information about the V2 board
  arm64: dts: marvell: armada-3720-db: Sort the dts node alphabetically
  arm64: dts: marvell: disable the mdio nodes by default
  arm64: dts: marvell: explicitly enable the mdio nodes for 7k/8k DB
  arm64: dts: marvell: add dma-mask in crypto nodes for 7k/8k
  arm64: dts: marvell: 8040-mcbin: Enable 1GB Ethernet
  arm64: dts: marvell: cp110: add required clocks for mdio interface
  arm64: dts: marvell: use new binding for the system controller on ap806
  arm64: dts: marvell: remove clock-output-names on ap806
  arm64: dts: marvell: add second 1G port on the Armada 8040 DB
  arm64: dts: marvell: mcbin: add sdhci
  arm64: dts: marvell: add clocks for Armada AP806 XOR engines

Signed-off-by: Olof Johansson <olof@lixom.net>

8 files changed, 200 insertions, 72 deletions

diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index a89855f57091..9df0f06ce607 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -42,6 +42,10 @@
  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  *     OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * This file is compatible with the version 1.4 and the version 2.0 of
+ * the board, however the CON numbers are different between the 2
+ * version
  */
 
 /dts-v1/;
@@ -76,6 +80,36 @@
                 compatible = "usb-nop-xceiv";
                 vcc-supply = <&exp_usb3_vbus>;
         };
+
+        vcc_sd_reg1: regulator {
+                compatible = "regulator-gpio";
+                regulator-name = "vcc_sd1";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+
+                gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
+                gpios-states = <0>;
+                states = <1800000 0x1
+                          3300000 0x0>;
+                enable-active-high;
+        };
+};
+
+/* Gigabit module on CON19(V2.0)/CON21(V1.4) */
+&eth0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&rgmii_pins>;
+        phy-mode = "rgmii-id";
+        phy = <&phy0>;
+        status = "okay";
+};
+
+/* Gigabit module on CON18(V2.0)/CON20(V1.4) */
+&eth1 {
+        phy-mode = "sgmii";
+        phy = <&phy1>;
+        status = "okay";
 };
 
 &i2c0 {
@@ -108,11 +142,46 @@
         };
 };
 
+&mdio {
+        status = "okay";
+        phy0: ethernet-phy@0 {
+                reg = <0>;
+        };
+
+        phy1: ethernet-phy@1 {
+                reg = <1>;
+        };
+};
+
+/* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */
+&pcie0 {
+        status = "okay";
+};
+
 /* CON3 */
 &sata {
         status = "okay";
 };
 
+&sdhci0 {
+        non-removable;
+        bus-width = <8>;
+        mmc-ddr-1_8v;
+        mmc-hs400-1_8v;
+        marvell,pad-type = "fixed-1-8v";
+        status = "okay";
+};
+
+/* SD slot module on CON14(V2.0)/CON15(V1.4) */
+&sdhci1 {
+        wp-inverted;
+        cd-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
+        bus-width = <4>;
+        marvell,pad-type = "sd";
+        vqmmc-supply = <&vcc_sd_reg1>;
+        status = "okay";
+};
+
 &spi0 {
         status = "okay";
         pinctrl-names = "default";
@@ -145,60 +214,23 @@
         };
 };
 
-/* Exported on the micro USB connector CON32 through an FTDI */
+/*
+ * Exported on the micro USB connector CON30(V2.0)/CON32(V1.4) through
+ * an FTDI
+ */
 &uart0 {
         pinctrl-names = "default";
         pinctrl-0 = <&uart1_pins>;
         status = "okay";
 };
 
-&sdhci0 {
-        non-removable;
-        bus-width = <8>;
-        mmc-ddr-1_8v;
-        mmc-hs400-1_8v;
-        marvell,pad-type = "fixed-1-8v";
+/* CON27(V2.0)/CON29(V1.4) */
+&usb2 {
         status = "okay";
 };
 
-/* CON31 */
+/* CON29(V2.0)/CON31(V1.4) */
 &usb3 {
         status = "okay";
         usb-phy = <&usb3_phy>;
 };
-
-/* CON17 (PCIe) / CON12 (mini-PCIe) */
-&pcie0 {
-        status = "okay";
-};
-
-/* CON27 */
-&usb2 {
-        status = "okay";
-};
-
-
-&mdio {
-        status = "okay";
-        phy0: ethernet-phy@0 {
-                reg = <0>;
-        };
-
-        phy1: ethernet-phy@1 {
-                reg = <1>;
-        };
-};
-
-&eth0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&rgmii_pins>;
-        phy-mode = "rgmii-id";
-        phy = <&phy0>;
-        status = "okay";
-};
-
-&eth1 {
-        phy-mode = "sgmii";
-        phy = <&phy1>;
-        status = "okay";
-};
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index 4d495ec39202..b4d27857c61b 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -163,7 +163,7 @@
 
                         pinctrl_nb: pinctrl@13800 {
                                 compatible = "marvell,armada3710-nb-pinctrl",
-                                "syscon", "simple-mfd";
+                                             "syscon", "simple-mfd";
                                 reg = <0x13800 0x100>, <0x13C00 0x20>;
                                 gpionb: gpio {
                                         #gpio-cells = <2>;
@@ -219,7 +219,7 @@
 
                         pinctrl_sb: pinctrl@18800 {
                                 compatible = "marvell,armada3710-sb-pinctrl",
-                                "syscon", "simple-mfd";
+                                             "syscon", "simple-mfd";
                                 reg = <0x18800 0x100>, <0x18C00 0x20>;
                                 gpiosb: gpio {
                                         #gpio-cells = <2>;
@@ -281,8 +281,8 @@
 
                         xor@60900 {
                                 compatible = "marvell,armada-3700-xor";
-                                reg = <0x60900 0x100
-                                       0x60b00 0x100>;
+                                reg = <0x60900 0x100>,
+                                      <0x60b00 0x100>;
 
                                 xor10 {
                                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
@@ -292,11 +292,22 @@
                                 };
                         };
 
+                        sdhci1: sdhci@d0000 {
+                                compatible = "marvell,armada-3700-sdhci",
+                                             "marvell,sdhci-xenon";
+                                reg = <0xd0000 0x300>,
+                                      <0x1e808 0x4>;
+                                interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&nb_periph_clk 0>;
+                                clock-names = "core";
+                                status = "disabled";
+                        };
+
                         sdhci0: sdhci@d8000 {
                                 compatible = "marvell,armada-3700-sdhci",
-                                "marvell,sdhci-xenon";
-                                reg = <0xd8000 0x300
-                                       0x17808 0x4>;
+                                             "marvell,sdhci-xenon";
+                                reg = <0xd8000 0x300>,
+                                      <0x17808 0x4>;
                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&nb_periph_clk 0>;
                                 clock-names = "core";
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index 12442329b80f..92c761c380d3 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -162,6 +162,8 @@
 };
 
 &cpm_mdio {
+        status = "okay";
+
         phy0: ethernet-phy@0 {
                 reg = <0>;
         };
@@ -185,7 +187,3 @@
         phy = <&phy1>;
         phy-mode = "rgmii-id";
 };
-
-&cpm_crypto {
-        status = "okay";
-};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index dc0d084005b2..1e8f7242ed6f 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -125,6 +125,8 @@
 };
 
 &cpm_mdio {
+        status = "okay";
+
         phy1: ethernet-phy@1 {
                 reg = <1>;
         };
@@ -140,10 +142,6 @@
         phy-mode = "rgmii-id";
 };
 
-&cpm_crypto {
-        status = "okay";
-};
-
 /* CON5 on CP1 expansion */
 &cps_pcie2 {
         status = "okay";
@@ -169,6 +167,24 @@
         status = "okay";
 };
 
+&cps_mdio {
+        status = "okay";
+
+        phy0: ethernet-phy@0 {
+                reg = <0>;
+        };
+};
+
+&cps_ethernet {
+        status = "okay";
+};
+
+&cps_eth1 {
+        status = "okay";
+        phy = <&phy0>;
+        phy-mode = "rgmii-id";
+};
+
 &ap_sdhci0 {
         status = "okay";
         bus-width = <4>;
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
index f7bb0cc03147..fe56efcfcefe 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
@@ -95,16 +95,45 @@
         status = "okay";
 };
 
+&ap_sdhci0 {
+        bus-width = <8>;
+        /*
+         * Not stable in HS modes - phy needs "more calibration", so add
+         * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
+         */
+        marvell,xenon-phy-slow-mode;
+        no-1-8-v;
+        no-sd;
+        no-sdio;
+        non-removable;
+        status = "okay";
+        vqmmc-supply = <&v_vddo_h>;
+};
+
 &cpm_i2c0 {
         clock-frequency = <100000>;
         status = "okay";
 };
 
+&cpm_mdio {
+        ge_phy: ethernet-phy@0 {
+                reg = <0>;
+        };
+};
+
 &cpm_sata0 {
         /* CPM Lane 0 - U29 */
         status = "okay";
 };
 
+&cpm_sdhci0 {
+        /* U6 */
+        broken-cd;
+        bus-width = <4>;
+        status = "okay";
+        vqmmc-supply = <&v_3_3>;
+};
+
 &cpm_usb3_0 {
         /* J38? - USB2.0 only */
         status = "okay";
@@ -115,6 +144,17 @@
         status = "okay";
 };
 
+&cps_ethernet {
+        status = "okay";
+};
+
+&cps_eth1 {
+        /* CPS Lane 0 - J5 (Gigabit RJ45) */
+        status = "okay";
+        phy = <&ge_phy>;
+        phy-mode = "sgmii";
+};
+
 &cps_sata0 {
         /* CPS Lane 1 - U32 */
         /* CPS Lane 3 - U31 */
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index fe41bf9c301e..ff1964d314de 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -159,6 +159,7 @@
                                 reg = <0x400000 0x1000>,
                                       <0x410000 0x1000>;
                                 msi-parent = <&gic_v2m0>;
+                                clocks = <&ap_syscon 3>;
                                 dma-coherent;
                         };
 
@@ -167,6 +168,7 @@
                                 reg = <0x420000 0x1000>,
                                       <0x430000 0x1000>;
                                 msi-parent = <&gic_v2m0>;
+                                clocks = <&ap_syscon 3>;
                                 dma-coherent;
                         };
 
@@ -175,6 +177,7 @@
                                 reg = <0x440000 0x1000>,
                                       <0x450000 0x1000>;
                                 msi-parent = <&gic_v2m0>;
+                                clocks = <&ap_syscon 3>;
                                 dma-coherent;
                         };
 
@@ -183,6 +186,7 @@
                                 reg = <0x460000 0x1000>,
                                       <0x470000 0x1000>;
                                 msi-parent = <&gic_v2m0>;
+                                clocks = <&ap_syscon 3>;
                                 dma-coherent;
                         };
 
@@ -193,7 +197,7 @@
                                 #size-cells = <0>;
                                 cell-index = <0>;
                                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&ap_syscon 3>;
+                                clocks = <&ap_clk 3>;
                                 status = "disabled";
                         };
 
@@ -204,7 +208,7 @@
                                 #size-cells = <0>;
                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
                                 timeout-ms = <1000>;
-                                clocks = <&ap_syscon 3>;
+                                clocks = <&ap_clk 3>;
                                 status = "disabled";
                         };
 
@@ -214,7 +218,7 @@
                                 reg-shift = <2>;
                                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
                                 reg-io-width = <1>;
-                                clocks = <&ap_syscon 3>;
+                                clocks = <&ap_clk 3>;
                                 status = "disabled";
                         };
 
@@ -224,7 +228,7 @@
                                 reg-shift = <2>;
                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
                                 reg-io-width = <1>;
-                                clocks = <&ap_syscon 3>;
+                                clocks = <&ap_clk 3>;
                                 status = "disabled";
 
                         };
@@ -234,21 +238,20 @@
                                 reg = <0x6e0000 0x300>;
                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
                                 clock-names = "core";
-                                clocks = <&ap_syscon 4>;
+                                clocks = <&ap_clk 4>;
                                 dma-coherent;
                                 marvell,xenon-phy-slow-mode;
                                 status = "disabled";
                         };
 
                         ap_syscon: system-controller@6f4000 {
-                                compatible = "marvell,ap806-system-controller",
-                                             "syscon";
-                                #clock-cells = <1>;
-                                clock-output-names = "ap-cpu-cluster-0",
-                                                     "ap-cpu-cluster-1",
-                                                     "ap-fixed", "ap-mss",
-                                                     "ap-emmc";
+                                compatible = "syscon", "simple-mfd";
                                 reg = <0x6f4000 0x1000>;
+
+                                ap_clk: clock {
+                                        compatible = "marvell,ap806-clock";
+                                        #clock-cells = <1>;
+                                };
                         };
                 };
         };
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index ac8df5201cd6..d490a377d0c1 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -94,6 +94,16 @@
                                 #size-cells = <0>;
                                 compatible = "marvell,orion-mdio";
                                 reg = <0x12a200 0x10>;
+                                clocks = <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>;
+                                status = "disabled";
+                        };
+
+                        cpm_xmdio: mdio@12a600 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "marvell,xmdio";
+                                reg = <0x12a600 0x10>;
+                                status = "disabled";
                         };
 
                         cpm_syscon0: system-controller@440000 {
@@ -241,7 +251,7 @@
                                 interrupt-names = "mem", "ring0", "ring1",
                                 "ring2", "ring3", "eip";
                                 clocks = <&cpm_syscon0 1 26>;
-                                status = "disabled";
+                                dma-mask = <0xff 0xffffffff>;
                         };
                 };
 
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 7740a75a8230..dc4673dcf81b 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -101,6 +101,16 @@
                                 #size-cells = <0>;
                                 compatible = "marvell,orion-mdio";
                                 reg = <0x12a200 0x10>;
+                                clocks = <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
+                                status = "disabled";
+                        };
+
+                        cps_xmdio: mdio@12a600 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "marvell,xmdio";
+                                reg = <0x12a600 0x10>;
+                                status = "disabled";
                         };
 
                         cps_syscon0: system-controller@440000 {
@@ -231,6 +241,14 @@
                                 interrupt-names = "mem", "ring0", "ring1",
                                                   "ring2", "ring3", "eip";
                                 clocks = <&cps_syscon0 1 26>;
+                                dma-mask = <0xff 0xffffffff>;
+                                /*
+                                 * The cryptographic engine found on the cp110
+                                 * master is enabled by default at the SoC
+                                 * level. Because it is not possible as of now
+                                 * to enable two cryptographic engines in
+                                 * parallel, disable this one by default.
+                                 */
                                 status = "disabled";
                         };
                 };