aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorTero Kristo <t-kristo@ti.com>2017-12-08 10:17:28 -0500
committerTony Lindgren <tony@atomide.com>2017-12-11 11:28:35 -0500
commit460c49610d5920b7a18799898e33c55f1e096494 (patch)
treeedfec2356eca871af0aa945714d7d32230847a9e
parenta5c82a09d876287cd394945dd2a73aaeb6596ecd (diff)
ARM: dts: omap5: add clkctrl nodes
Add clkctrl nodes for OMAP5 SoC. These are going to be acting as replacement for part of the existing clock data and the existing clkctrl hooks under hwmod data. This patch also removes any obsolete clock nodes, and reroutes all users for these to use the new clkctrl clocks instead. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat
-rw-r--r--arch/arm/boot/dts/omap5.dtsi30
-rw-r--r--arch/arm/boot/dts/omap54xx-clocks.dtsi623
2 files changed, 222 insertions, 431 deletions
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index b0992b860705..4bc52257df67 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -10,6 +10,7 @@
10#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/pinctrl/omap.h> 12#include <dt-bindings/pinctrl/omap.h>
13#include <dt-bindings/clock/omap5.h>
13 14
14/ { 15/ {
15 #address-cells = <2>; 16 #address-cells = <2>;
@@ -744,7 +745,7 @@
744 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 745 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
745 ti,hwmods = "timer1"; 746 ti,hwmods = "timer1";
746 ti,timer-alwon; 747 ti,timer-alwon;
747 clocks = <&timer1_gfclk_mux>; 748 clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
748 clock-names = "fck"; 749 clock-names = "fck";
749 }; 750 };
750 751
@@ -905,7 +906,8 @@
905 compatible = "ti,omap-usb2"; 906 compatible = "ti,omap-usb2";
906 reg = <0x4a084000 0x7c>; 907 reg = <0x4a084000 0x7c>;
907 syscon-phy-power = <&scm_conf 0x300>; 908 syscon-phy-power = <&scm_conf 0x300>;
908 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>; 909 clocks = <&usb_phy_cm_clk32k>,
910 <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
909 clock-names = "wkupclk", "refclk"; 911 clock-names = "wkupclk", "refclk";
910 #phy-cells = <0>; 912 #phy-cells = <0>;
911 }; 913 };
@@ -919,7 +921,7 @@
919 syscon-phy-power = <&scm_conf 0x370>; 921 syscon-phy-power = <&scm_conf 0x370>;
920 clocks = <&usb_phy_cm_clk32k>, 922 clocks = <&usb_phy_cm_clk32k>,
921 <&sys_clkin>, 923 <&sys_clkin>,
922 <&usb_otg_ss_refclk960m>; 924 <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
923 clock-names = "wkupclk", 925 clock-names = "wkupclk",
924 "sysclk", 926 "sysclk",
925 "refclk"; 927 "refclk";
@@ -987,7 +989,8 @@
987 <0x4A096800 0x40>; /* pll_ctrl */ 989 <0x4A096800 0x40>; /* pll_ctrl */
988 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 990 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
989 syscon-phy-power = <&scm_conf 0x374>; 991 syscon-phy-power = <&scm_conf 0x374>;
990 clocks = <&sys_clkin>, <&sata_ref_clk>; 992 clocks = <&sys_clkin>,
993 <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
991 clock-names = "sysclk", "refclk"; 994 clock-names = "sysclk", "refclk";
992 #phy-cells = <0>; 995 #phy-cells = <0>;
993 }; 996 };
@@ -999,7 +1002,7 @@
999 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1002 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1000 phys = <&sata_phy>; 1003 phys = <&sata_phy>;
1001 phy-names = "sata-phy"; 1004 phy-names = "sata-phy";
1002 clocks = <&sata_ref_clk>; 1005 clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
1003 ti,hwmods = "sata"; 1006 ti,hwmods = "sata";
1004 ports-implemented = <0x1>; 1007 ports-implemented = <0x1>;
1005 }; 1008 };
@@ -1009,7 +1012,7 @@
1009 reg = <0x58000000 0x80>; 1012 reg = <0x58000000 0x80>;
1010 status = "disabled"; 1013 status = "disabled";
1011 ti,hwmods = "dss_core"; 1014 ti,hwmods = "dss_core";
1012 clocks = <&dss_dss_clk>; 1015 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
1013 clock-names = "fck"; 1016 clock-names = "fck";
1014 #address-cells = <1>; 1017 #address-cells = <1>;
1015 #size-cells = <1>; 1018 #size-cells = <1>;
@@ -1020,7 +1023,7 @@
1020 reg = <0x58001000 0x1000>; 1023 reg = <0x58001000 0x1000>;
1021 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1024 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1022 ti,hwmods = "dss_dispc"; 1025 ti,hwmods = "dss_dispc";
1023 clocks = <&dss_dss_clk>; 1026 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
1024 clock-names = "fck"; 1027 clock-names = "fck";
1025 }; 1028 };
1026 1029
@@ -1029,7 +1032,7 @@
1029 reg = <0x58002000 0x100>; 1032 reg = <0x58002000 0x100>;
1030 status = "disabled"; 1033 status = "disabled";
1031 ti,hwmods = "dss_rfbi"; 1034 ti,hwmods = "dss_rfbi";
1032 clocks = <&dss_dss_clk>, <&l3_iclk_div>; 1035 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
1033 clock-names = "fck", "ick"; 1036 clock-names = "fck", "ick";
1034 }; 1037 };
1035 1038
@@ -1042,7 +1045,8 @@
1042 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1045 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1043 status = "disabled"; 1046 status = "disabled";
1044 ti,hwmods = "dss_dsi1"; 1047 ti,hwmods = "dss_dsi1";
1045 clocks = <&dss_dss_clk>, <&dss_sys_clk>; 1048 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
1049 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1046 clock-names = "fck", "sys_clk"; 1050 clock-names = "fck", "sys_clk";
1047 }; 1051 };
1048 1052
@@ -1055,7 +1059,8 @@
1055 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1059 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1056 status = "disabled"; 1060 status = "disabled";
1057 ti,hwmods = "dss_dsi2"; 1061 ti,hwmods = "dss_dsi2";
1058 clocks = <&dss_dss_clk>, <&dss_sys_clk>; 1062 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
1063 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1059 clock-names = "fck", "sys_clk"; 1064 clock-names = "fck", "sys_clk";
1060 }; 1065 };
1061 1066
@@ -1069,7 +1074,8 @@
1069 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1074 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1070 status = "disabled"; 1075 status = "disabled";
1071 ti,hwmods = "dss_hdmi"; 1076 ti,hwmods = "dss_hdmi";
1072 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>; 1077 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
1078 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1073 clock-names = "fck", "sys_clk"; 1079 clock-names = "fck", "sys_clk";
1074 dmas = <&sdma 76>; 1080 dmas = <&sdma 76>;
1075 dma-names = "audio_tx"; 1081 dma-names = "audio_tx";
@@ -1143,7 +1149,7 @@
1143 coefficients = <65 (-1791)>; 1149 coefficients = <65 (-1791)>;
1144}; 1150};
1145 1151
1146/include/ "omap54xx-clocks.dtsi" 1152#include "omap54xx-clocks.dtsi"
1147 1153
1148&gpu_thermal { 1154&gpu_thermal {
1149 coefficients = <117 (-2992)>; 1155 coefficients = <117 (-2992)>;
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index 529193442620..9619a746d657 100644
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -432,22 +432,6 @@
432 reg = <0x0528>; 432 reg = <0x0528>;
433 }; 433 };
434 434
435 dmic_sync_mux_ck: dmic_sync_mux_ck@538 {
436 #clock-cells = <0>;
437 compatible = "ti,mux-clock";
438 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
439 ti,bit-shift = <26>;
440 reg = <0x0538>;
441 };
442
443 dmic_gfclk: dmic_gfclk@538 {
444 #clock-cells = <0>;
445 compatible = "ti,mux-clock";
446 clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
447 ti,bit-shift = <24>;
448 reg = <0x0538>;
449 };
450
451 mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 { 435 mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
452 #clock-cells = <0>; 436 #clock-cells = <0>;
453 compatible = "ti,mux-clock"; 437 compatible = "ti,mux-clock";
@@ -464,86 +448,6 @@
464 reg = <0x0540>; 448 reg = <0x0540>;
465 }; 449 };
466 450
467 mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@548 {
468 #clock-cells = <0>;
469 compatible = "ti,mux-clock";
470 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
471 ti,bit-shift = <26>;
472 reg = <0x0548>;
473 };
474
475 mcbsp1_gfclk: mcbsp1_gfclk@548 {
476 #clock-cells = <0>;
477 compatible = "ti,mux-clock";
478 clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
479 ti,bit-shift = <24>;
480 reg = <0x0548>;
481 };
482
483 mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@550 {
484 #clock-cells = <0>;
485 compatible = "ti,mux-clock";
486 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
487 ti,bit-shift = <26>;
488 reg = <0x0550>;
489 };
490
491 mcbsp2_gfclk: mcbsp2_gfclk@550 {
492 #clock-cells = <0>;
493 compatible = "ti,mux-clock";
494 clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
495 ti,bit-shift = <24>;
496 reg = <0x0550>;
497 };
498
499 mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@558 {
500 #clock-cells = <0>;
501 compatible = "ti,mux-clock";
502 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
503 ti,bit-shift = <26>;
504 reg = <0x0558>;
505 };
506
507 mcbsp3_gfclk: mcbsp3_gfclk@558 {
508 #clock-cells = <0>;
509 compatible = "ti,mux-clock";
510 clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
511 ti,bit-shift = <24>;
512 reg = <0x0558>;
513 };
514
515 timer5_gfclk_mux: timer5_gfclk_mux@568 {
516 #clock-cells = <0>;
517 compatible = "ti,mux-clock";
518 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
519 ti,bit-shift = <24>;
520 reg = <0x0568>;
521 };
522
523 timer6_gfclk_mux: timer6_gfclk_mux@570 {
524 #clock-cells = <0>;
525 compatible = "ti,mux-clock";
526 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
527 ti,bit-shift = <24>;
528 reg = <0x0570>;
529 };
530
531 timer7_gfclk_mux: timer7_gfclk_mux@578 {
532 #clock-cells = <0>;
533 compatible = "ti,mux-clock";
534 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
535 ti,bit-shift = <24>;
536 reg = <0x0578>;
537 };
538
539 timer8_gfclk_mux: timer8_gfclk_mux@580 {
540 #clock-cells = <0>;
541 compatible = "ti,mux-clock";
542 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
543 ti,bit-shift = <24>;
544 reg = <0x0580>;
545 };
546
547 dummy_ck: dummy_ck { 451 dummy_ck: dummy_ck {
548 #clock-cells = <0>; 452 #clock-cells = <0>;
549 compatible = "fixed-clock"; 453 compatible = "fixed-clock";
@@ -603,23 +507,8 @@
603 clock-mult = <1>; 507 clock-mult = <1>;
604 clock-div = <1>; 508 clock-div = <1>;
605 }; 509 };
606
607 gpio1_dbclk: gpio1_dbclk@1938 {
608 #clock-cells = <0>;
609 compatible = "ti,gate-clock";
610 clocks = <&sys_32k_ck>;
611 ti,bit-shift = <8>;
612 reg = <0x1938>;
613 };
614
615 timer1_gfclk_mux: timer1_gfclk_mux@1940 {
616 #clock-cells = <0>;
617 compatible = "ti,mux-clock";
618 clocks = <&sys_clkin>, <&sys_32k_ck>;
619 ti,bit-shift = <24>;
620 reg = <0x1940>;
621 };
622}; 510};
511
623&cm_core_clocks { 512&cm_core_clocks {
624 513
625 dpll_per_byp_mux: dpll_per_byp_mux@14c { 514 dpll_per_byp_mux: dpll_per_byp_mux@14c {
@@ -825,95 +714,6 @@
825 ti,dividers = <1>, <8>; 714 ti,dividers = <1>, <8>;
826 }; 715 };
827 716
828 dss_32khz_clk: dss_32khz_clk@1420 {
829 #clock-cells = <0>;
830 compatible = "ti,gate-clock";
831 clocks = <&sys_32k_ck>;
832 ti,bit-shift = <11>;
833 reg = <0x1420>;
834 };
835
836 dss_48mhz_clk: dss_48mhz_clk@1420 {
837 #clock-cells = <0>;
838 compatible = "ti,gate-clock";
839 clocks = <&func_48m_fclk>;
840 ti,bit-shift = <9>;
841 reg = <0x1420>;
842 };
843
844 dss_dss_clk: dss_dss_clk@1420 {
845 #clock-cells = <0>;
846 compatible = "ti,gate-clock";
847 clocks = <&dpll_per_h12x2_ck>;
848 ti,bit-shift = <8>;
849 reg = <0x1420>;
850 ti,set-rate-parent;
851 };
852
853 dss_sys_clk: dss_sys_clk@1420 {
854 #clock-cells = <0>;
855 compatible = "ti,gate-clock";
856 clocks = <&dss_syc_gfclk_div>;
857 ti,bit-shift = <10>;
858 reg = <0x1420>;
859 };
860
861 gpio2_dbclk: gpio2_dbclk@1060 {
862 #clock-cells = <0>;
863 compatible = "ti,gate-clock";
864 clocks = <&sys_32k_ck>;
865 ti,bit-shift = <8>;
866 reg = <0x1060>;
867 };
868
869 gpio3_dbclk: gpio3_dbclk@1068 {
870 #clock-cells = <0>;
871 compatible = "ti,gate-clock";
872 clocks = <&sys_32k_ck>;
873 ti,bit-shift = <8>;
874 reg = <0x1068>;
875 };
876
877 gpio4_dbclk: gpio4_dbclk@1070 {
878 #clock-cells = <0>;
879 compatible = "ti,gate-clock";
880 clocks = <&sys_32k_ck>;
881 ti,bit-shift = <8>;
882 reg = <0x1070>;
883 };
884
885 gpio5_dbclk: gpio5_dbclk@1078 {
886 #clock-cells = <0>;
887 compatible = "ti,gate-clock";
888 clocks = <&sys_32k_ck>;
889 ti,bit-shift = <8>;
890 reg = <0x1078>;
891 };
892
893 gpio6_dbclk: gpio6_dbclk@1080 {
894 #clock-cells = <0>;
895 compatible = "ti,gate-clock";
896 clocks = <&sys_32k_ck>;
897 ti,bit-shift = <8>;
898 reg = <0x1080>;
899 };
900
901 gpio7_dbclk: gpio7_dbclk@1110 {
902 #clock-cells = <0>;
903 compatible = "ti,gate-clock";
904 clocks = <&sys_32k_ck>;
905 ti,bit-shift = <8>;
906 reg = <0x1110>;
907 };
908
909 gpio8_dbclk: gpio8_dbclk@1118 {
910 #clock-cells = <0>;
911 compatible = "ti,gate-clock";
912 clocks = <&sys_32k_ck>;
913 ti,bit-shift = <8>;
914 reg = <0x1118>;
915 };
916
917 iss_ctrlclk: iss_ctrlclk@1320 { 717 iss_ctrlclk: iss_ctrlclk@1320 {
918 #clock-cells = <0>; 718 #clock-cells = <0>;
919 compatible = "ti,gate-clock"; 719 compatible = "ti,gate-clock";
@@ -938,118 +738,6 @@
938 reg = <0x0f20>; 738 reg = <0x0f20>;
939 }; 739 };
940 740
941 mmc1_32khz_clk: mmc1_32khz_clk@1628 {
942 #clock-cells = <0>;
943 compatible = "ti,gate-clock";
944 clocks = <&sys_32k_ck>;
945 ti,bit-shift = <8>;
946 reg = <0x1628>;
947 };
948
949 sata_ref_clk: sata_ref_clk@1688 {
950 #clock-cells = <0>;
951 compatible = "ti,gate-clock";
952 clocks = <&sys_clkin>;
953 ti,bit-shift = <8>;
954 reg = <0x1688>;
955 };
956
957 usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@1658 {
958 #clock-cells = <0>;
959 compatible = "ti,gate-clock";
960 clocks = <&dpll_usb_m2_ck>;
961 ti,bit-shift = <13>;
962 reg = <0x1658>;
963 };
964
965 usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@1658 {
966 #clock-cells = <0>;
967 compatible = "ti,gate-clock";
968 clocks = <&dpll_usb_m2_ck>;
969 ti,bit-shift = <14>;
970 reg = <0x1658>;
971 };
972
973 usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk@1658 {
974 #clock-cells = <0>;
975 compatible = "ti,gate-clock";
976 clocks = <&dpll_usb_m2_ck>;
977 ti,bit-shift = <7>;
978 reg = <0x1658>;
979 };
980
981 usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@1658 {
982 #clock-cells = <0>;
983 compatible = "ti,gate-clock";
984 clocks = <&l3init_60m_fclk>;
985 ti,bit-shift = <11>;
986 reg = <0x1658>;
987 };
988
989 usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@1658 {
990 #clock-cells = <0>;
991 compatible = "ti,gate-clock";
992 clocks = <&l3init_60m_fclk>;
993 ti,bit-shift = <12>;
994 reg = <0x1658>;
995 };
996
997 usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk@1658 {
998 #clock-cells = <0>;
999 compatible = "ti,gate-clock";
1000 clocks = <&l3init_60m_fclk>;
1001 ti,bit-shift = <6>;
1002 reg = <0x1658>;
1003 };
1004
1005 utmi_p1_gfclk: utmi_p1_gfclk@1658 {
1006 #clock-cells = <0>;
1007 compatible = "ti,mux-clock";
1008 clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
1009 ti,bit-shift = <24>;
1010 reg = <0x1658>;
1011 };
1012
1013 usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@1658 {
1014 #clock-cells = <0>;
1015 compatible = "ti,gate-clock";
1016 clocks = <&utmi_p1_gfclk>;
1017 ti,bit-shift = <8>;
1018 reg = <0x1658>;
1019 };
1020
1021 utmi_p2_gfclk: utmi_p2_gfclk@1658 {
1022 #clock-cells = <0>;
1023 compatible = "ti,mux-clock";
1024 clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
1025 ti,bit-shift = <25>;
1026 reg = <0x1658>;
1027 };
1028
1029 usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@1658 {
1030 #clock-cells = <0>;
1031 compatible = "ti,gate-clock";
1032 clocks = <&utmi_p2_gfclk>;
1033 ti,bit-shift = <9>;
1034 reg = <0x1658>;
1035 };
1036
1037 usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@1658 {
1038 #clock-cells = <0>;
1039 compatible = "ti,gate-clock";
1040 clocks = <&l3init_60m_fclk>;
1041 ti,bit-shift = <10>;
1042 reg = <0x1658>;
1043 };
1044
1045 usb_otg_ss_refclk960m: usb_otg_ss_refclk960m@16f0 {
1046 #clock-cells = <0>;
1047 compatible = "ti,gate-clock";
1048 clocks = <&dpll_usb_clkdcoldo>;
1049 ti,bit-shift = <8>;
1050 reg = <0x16f0>;
1051 };
1052
1053 usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { 741 usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
1054 #clock-cells = <0>; 742 #clock-cells = <0>;
1055 compatible = "ti,gate-clock"; 743 compatible = "ti,gate-clock";
@@ -1058,30 +746,6 @@
1058 reg = <0x0640>; 746 reg = <0x0640>;
1059 }; 747 };
1060 748
1061 usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@1668 {
1062 #clock-cells = <0>;
1063 compatible = "ti,gate-clock";
1064 clocks = <&l3init_60m_fclk>;
1065 ti,bit-shift = <8>;
1066 reg = <0x1668>;
1067 };
1068
1069 usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@1668 {
1070 #clock-cells = <0>;
1071 compatible = "ti,gate-clock";
1072 clocks = <&l3init_60m_fclk>;
1073 ti,bit-shift = <9>;
1074 reg = <0x1668>;
1075 };
1076
1077 usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@1668 {
1078 #clock-cells = <0>;
1079 compatible = "ti,gate-clock";
1080 clocks = <&l3init_60m_fclk>;
1081 ti,bit-shift = <10>;
1082 reg = <0x1668>;
1083 };
1084
1085 fdif_fclk: fdif_fclk@1328 { 749 fdif_fclk: fdif_fclk@1328 {
1086 #clock-cells = <0>; 750 #clock-cells = <0>;
1087 compatible = "ti,divider-clock"; 751 compatible = "ti,divider-clock";
@@ -1115,88 +779,6 @@
1115 ti,max-div = <2>; 779 ti,max-div = <2>;
1116 reg = <0x1638>; 780 reg = <0x1638>;
1117 }; 781 };
1118
1119 mmc1_fclk_mux: mmc1_fclk_mux@1628 {
1120 #clock-cells = <0>;
1121 compatible = "ti,mux-clock";
1122 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1123 ti,bit-shift = <24>;
1124 reg = <0x1628>;
1125 };
1126
1127 mmc1_fclk: mmc1_fclk@1628 {
1128 #clock-cells = <0>;
1129 compatible = "ti,divider-clock";
1130 clocks = <&mmc1_fclk_mux>;
1131 ti,bit-shift = <25>;
1132 ti,max-div = <2>;
1133 reg = <0x1628>;
1134 };
1135
1136 mmc2_fclk_mux: mmc2_fclk_mux@1630 {
1137 #clock-cells = <0>;
1138 compatible = "ti,mux-clock";
1139 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1140 ti,bit-shift = <24>;
1141 reg = <0x1630>;
1142 };
1143
1144 mmc2_fclk: mmc2_fclk@1630 {
1145 #clock-cells = <0>;
1146 compatible = "ti,divider-clock";
1147 clocks = <&mmc2_fclk_mux>;
1148 ti,bit-shift = <25>;
1149 ti,max-div = <2>;
1150 reg = <0x1630>;
1151 };
1152
1153 timer10_gfclk_mux: timer10_gfclk_mux@1028 {
1154 #clock-cells = <0>;
1155 compatible = "ti,mux-clock";
1156 clocks = <&sys_clkin>, <&sys_32k_ck>;
1157 ti,bit-shift = <24>;
1158 reg = <0x1028>;
1159 };
1160
1161 timer11_gfclk_mux: timer11_gfclk_mux@1030 {
1162 #clock-cells = <0>;
1163 compatible = "ti,mux-clock";
1164 clocks = <&sys_clkin>, <&sys_32k_ck>;
1165 ti,bit-shift = <24>;
1166 reg = <0x1030>;
1167 };
1168
1169 timer2_gfclk_mux: timer2_gfclk_mux@1038 {
1170 #clock-cells = <0>;
1171 compatible = "ti,mux-clock";
1172 clocks = <&sys_clkin>, <&sys_32k_ck>;
1173 ti,bit-shift = <24>;
1174 reg = <0x1038>;
1175 };
1176
1177 timer3_gfclk_mux: timer3_gfclk_mux@1040 {
1178 #clock-cells = <0>;
1179 compatible = "ti,mux-clock";
1180 clocks = <&sys_clkin>, <&sys_32k_ck>;
1181 ti,bit-shift = <24>;
1182 reg = <0x1040>;
1183 };
1184
1185 timer4_gfclk_mux: timer4_gfclk_mux@1048 {
1186 #clock-cells = <0>;
1187 compatible = "ti,mux-clock";
1188 clocks = <&sys_clkin>, <&sys_32k_ck>;
1189 ti,bit-shift = <24>;
1190 reg = <0x1048>;
1191 };
1192
1193 timer9_gfclk_mux: timer9_gfclk_mux@1050 {
1194 #clock-cells = <0>;
1195 compatible = "ti,mux-clock";
1196 clocks = <&sys_clkin>, <&sys_32k_ck>;
1197 ti,bit-shift = <24>;
1198 reg = <0x1050>;
1199 };
1200}; 782};
1201 783
1202&cm_core_clockdomains { 784&cm_core_clockdomains {
@@ -1394,3 +976,206 @@
1394 reg = <0x021c>; 976 reg = <0x021c>;
1395 }; 977 };
1396}; 978};
979
980&cm_core_aon {
981 mpu_cm: mpu_cm@300 {
982 compatible = "ti,omap4-cm";
983 reg = <0x300 0x100>;
984 #address-cells = <1>;
985 #size-cells = <1>;
986 ranges = <0 0x300 0x100>;
987
988 mpu_clkctrl: clk@20 {
989 compatible = "ti,clkctrl";
990 reg = <0x20 0x4>;
991 #clock-cells = <2>;
992 };
993 };
994
995 dsp_cm: dsp_cm@400 {
996 compatible = "ti,omap4-cm";
997 reg = <0x400 0x100>;
998 #address-cells = <1>;
999 #size-cells = <1>;
1000 ranges = <0 0x400 0x100>;
1001
1002 dsp_clkctrl: clk@20 {
1003 compatible = "ti,clkctrl";
1004 reg = <0x20 0x4>;
1005 #clock-cells = <2>;
1006 };
1007 };
1008
1009 abe_cm: abe_cm@500 {
1010 compatible = "ti,omap4-cm";
1011 reg = <0x500 0x100>;
1012 #address-cells = <1>;
1013 #size-cells = <1>;
1014 ranges = <0 0x500 0x100>;
1015
1016 abe_clkctrl: clk@20 {
1017 compatible = "ti,clkctrl";
1018 reg = <0x20 0x64>;
1019 #clock-cells = <2>;
1020 };
1021 };
1022
1023};
1024
1025&cm_core {
1026 l3main1_cm: l3main1_cm@700 {
1027 compatible = "ti,omap4-cm";
1028 reg = <0x700 0x100>;
1029 #address-cells = <1>;
1030 #size-cells = <1>;
1031 ranges = <0 0x700 0x100>;
1032
1033 l3main1_clkctrl: clk@20 {
1034 compatible = "ti,clkctrl";
1035 reg = <0x20 0x4>;
1036 #clock-cells = <2>;
1037 };
1038 };
1039
1040 l3main2_cm: l3main2_cm@800 {
1041 compatible = "ti,omap4-cm";
1042 reg = <0x800 0x100>;
1043 #address-cells = <1>;
1044 #size-cells = <1>;
1045 ranges = <0 0x800 0x100>;
1046
1047 l3main2_clkctrl: clk@20 {
1048 compatible = "ti,clkctrl";
1049 reg = <0x20 0x4>;
1050 #clock-cells = <2>;
1051 };
1052 };
1053
1054 ipu_cm: ipu_cm@900 {
1055 compatible = "ti,omap4-cm";
1056 reg = <0x900 0x100>;
1057 #address-cells = <1>;
1058 #size-cells = <1>;
1059 ranges = <0 0x900 0x100>;
1060
1061 ipu_clkctrl: clk@20 {
1062 compatible = "ti,clkctrl";
1063 reg = <0x20 0x4>;
1064 #clock-cells = <2>;
1065 };
1066 };
1067
1068 dma_cm: dma_cm@a00 {
1069 compatible = "ti,omap4-cm";
1070 reg = <0xa00 0x100>;
1071 #address-cells = <1>;
1072 #size-cells = <1>;
1073 ranges = <0 0xa00 0x100>;
1074
1075 dma_clkctrl: clk@20 {
1076 compatible = "ti,clkctrl";
1077 reg = <0x20 0x4>;
1078 #clock-cells = <2>;
1079 };
1080 };
1081
1082 emif_cm: emif_cm@b00 {
1083 compatible = "ti,omap4-cm";
1084 reg = <0xb00 0x100>;
1085 #address-cells = <1>;
1086 #size-cells = <1>;
1087 ranges = <0 0xb00 0x100>;
1088
1089 emif_clkctrl: clk@20 {
1090 compatible = "ti,clkctrl";
1091 reg = <0x20 0x1c>;
1092 #clock-cells = <2>;
1093 };
1094 };
1095
1096 l4cfg_cm: l4cfg_cm@d00 {
1097 compatible = "ti,omap4-cm";
1098 reg = <0xd00 0x100>;
1099 #address-cells = <1>;
1100 #size-cells = <1>;
1101 ranges = <0 0xd00 0x100>;
1102
1103 l4cfg_clkctrl: clk@20 {
1104 compatible = "ti,clkctrl";
1105 reg = <0x20 0x14>;
1106 #clock-cells = <2>;
1107 };
1108 };
1109
1110 l3instr_cm: l3instr_cm@e00 {
1111 compatible = "ti,omap4-cm";
1112 reg = <0xe00 0x100>;
1113 #address-cells = <1>;
1114 #size-cells = <1>;
1115 ranges = <0 0xe00 0x100>;
1116
1117 l3instr_clkctrl: clk@20 {
1118 compatible = "ti,clkctrl";
1119 reg = <0x20 0xc>;
1120 #clock-cells = <2>;
1121 };
1122 };
1123
1124 l4per_cm: l4per_cm@1000 {
1125 compatible = "ti,omap4-cm";
1126 reg = <0x1000 0x200>;
1127 #address-cells = <1>;
1128 #size-cells = <1>;
1129 ranges = <0 0x1000 0x200>;
1130
1131 l4per_clkctrl: clk@20 {
1132 compatible = "ti,clkctrl";
1133 reg = <0x20 0x15c>;
1134 #clock-cells = <2>;
1135 };
1136 };
1137
1138 dss_cm: dss_cm@1400 {
1139 compatible = "ti,omap4-cm";
1140 reg = <0x1400 0x100>;
1141 #address-cells = <1>;
1142 #size-cells = <1>;
1143 ranges = <0 0x1400 0x100>;
1144
1145 dss_clkctrl: clk@20 {
1146 compatible = "ti,clkctrl";
1147 reg = <0x20 0x4>;
1148 #clock-cells = <2>;
1149 };
1150 };
1151
1152 l3init_cm: l3init_cm@1600 {
1153 compatible = "ti,omap4-cm";
1154 reg = <0x1600 0x100>;
1155 #address-cells = <1>;
1156 #size-cells = <1>;
1157 ranges = <0 0x1600 0x100>;
1158
1159 l3init_clkctrl: clk@20 {
1160 compatible = "ti,clkctrl";
1161 reg = <0x20 0xd4>;
1162 #clock-cells = <2>;
1163 };
1164 };
1165};
1166
1167&prm {
1168 wkupaon_cm: wkupaon_cm@1900 {
1169 compatible = "ti,omap4-cm";
1170 reg = <0x1900 0x100>;
1171 #address-cells = <1>;
1172 #size-cells = <1>;
1173 ranges = <0 0x1900 0x100>;
1174
1175 wkupaon_clkctrl: clk@20 {
1176 compatible = "ti,clkctrl";
1177 reg = <0x20 0x5c>;
1178 #clock-cells = <2>;
1179 };
1180 };
1181};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-26 02:17:41 -0400