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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2018-07-30 04:21:14 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2018-07-30 04:21:14 -0400
commit45dd7af410b71da511085b806c22caf8ecca87e4 (patch)
treec04c335512353c6aa0f35d6420a6de22ae0f6c39
parent8a7b5d0f75f757fa88b0d17c19523161b27b8e80 (diff)
parent4ea438da76f4277627347147f6f7004affae07b9 (diff)
Merge tag 'usb-for-v4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next
Felipe writes: usb: changes for v4.19 Not a big pull request with only 37 non-merge commits, most of which are touching dwc2 (74% of the changes). The most important changes are dwc2's support for uframe scheduling and its endian-agnostic readl/writel wrappers. From dwc3 side we have a special new glue layer for Synopsys HAPS which will help Synopsys running FPGA validation using our upstream driver. We also have the beginnings of dual-role support for Intel Merrifield platform. Apart from these, just a series of non-critical changes.
Diffstat
-rw-r--r--Documentation/ABI/testing/configfs-usb-gadget-uvc5
-rw-r--r--Documentation/devicetree/bindings/usb/dwc3.txt6
-rw-r--r--MAINTAINERS1
-rw-r--r--drivers/usb/dwc2/core.c241
-rw-r--r--drivers/usb/dwc2/core.h109
-rw-r--r--drivers/usb/dwc2/core_intr.c118
-rw-r--r--drivers/usb/dwc2/debugfs.c55
-rw-r--r--drivers/usb/dwc2/gadget.c531
-rw-r--r--drivers/usb/dwc2/hcd.c459
-rw-r--r--drivers/usb/dwc2/hcd.h10
-rw-r--r--drivers/usb/dwc2/hcd_ddma.c10
-rw-r--r--drivers/usb/dwc2/hcd_intr.c96
-rw-r--r--drivers/usb/dwc2/hcd_queue.c10
-rw-r--r--drivers/usb/dwc2/params.c24
-rw-r--r--drivers/usb/dwc2/platform.c19
-rw-r--r--drivers/usb/dwc3/Kconfig13
-rw-r--r--drivers/usb/dwc3/Makefile1
-rw-r--r--drivers/usb/dwc3/core.c118
-rw-r--r--drivers/usb/dwc3/core.h17
-rw-r--r--drivers/usb/dwc3/dwc3-haps.c137
-rw-r--r--drivers/usb/dwc3/dwc3-of-simple.c29
-rw-r--r--drivers/usb/dwc3/dwc3-pci.c223
-rw-r--r--drivers/usb/dwc3/gadget.c2
-rw-r--r--drivers/usb/dwc3/gadget.h2
-rw-r--r--drivers/usb/gadget/configfs.c4
-rw-r--r--drivers/usb/gadget/function/f_mass_storage.c31
-rw-r--r--drivers/usb/gadget/function/f_mass_storage.h4
-rw-r--r--drivers/usb/gadget/function/f_uvc.c31
-rw-r--r--drivers/usb/gadget/function/f_uvc.h6
-rw-r--r--drivers/usb/gadget/function/u_uvc.h5
-rw-r--r--drivers/usb/gadget/function/uvc.h53
-rw-r--r--drivers/usb/gadget/function/uvc_configfs.c12
-rw-r--r--drivers/usb/gadget/function/uvc_queue.h12
-rw-r--r--drivers/usb/gadget/function/uvc_v4l2.c3
-rw-r--r--drivers/usb/gadget/function/uvc_video.h2
-rw-r--r--drivers/usb/gadget/legacy/tcm_usb_gadget.c2
-rw-r--r--drivers/usb/gadget/legacy/webcam.c4
-rw-r--r--drivers/usb/gadget/udc/Kconfig1
-rw-r--r--drivers/usb/gadget/udc/core.c18
-rw-r--r--drivers/usb/gadget/udc/renesas_usb3.c84
-rw-r--r--include/uapi/linux/usb/g_uvc.h39
41 files changed, 1506 insertions, 1041 deletions
diff --git a/Documentation/ABI/testing/configfs-usb-gadget-uvc b/Documentation/ABI/testing/configfs-usb-gadget-uvc
index 1ba0d0fda9c0..9281e2aa38df 100644
--- a/Documentation/ABI/testing/configfs-usb-gadget-uvc
+++ b/Documentation/ABI/testing/configfs-usb-gadget-uvc
@@ -263,3 +263,8 @@ Description: Specific streaming header descriptors
263 is connected 263 is connected
264 bmInfo - capabilities of this video streaming 264 bmInfo - capabilities of this video streaming
265 interface 265 interface
266
267What: /sys/class/udc/udc.name/device/gadget/video4linux/video.name/function_name
268Date: May 2018
269KernelVersion: 4.19
270Description: UVC configfs function instance name
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 7f13ebef06cb..3e4c38b806ac 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -96,6 +96,11 @@ Optional properties:
96 enable periodic ESS TX threshold. 96 enable periodic ESS TX threshold.
97 97
98 - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated. 98 - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated.
99 - snps,incr-burst-type-adjustment: Value for INCR burst type of GSBUSCFG0
100 register, undefined length INCR burst type enable and INCRx type.
101 When just one value, which means INCRX burst mode enabled. When
102 more than one value, which means undefined length INCR burst type
103 enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256.
99 104
100 - in addition all properties from usb-xhci.txt from the current directory are 105 - in addition all properties from usb-xhci.txt from the current directory are
101 supported as well 106 supported as well
@@ -108,4 +113,5 @@ dwc3@4a030000 {
108 reg = <0x4a030000 0xcfff>; 113 reg = <0x4a030000 0xcfff>;
109 interrupts = <0 92 4> 114 interrupts = <0 92 4>
110 usb-phy = <&usb2_phy>, <&usb3,phy>; 115 usb-phy = <&usb2_phy>, <&usb3,phy>;
116 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
111}; 117};
diff --git a/MAINTAINERS b/MAINTAINERS
index b6f6c22c03f1..a16450acf347 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15007,6 +15007,7 @@ L: linux-usb@vger.kernel.org
15007S: Maintained 15007S: Maintained
15008F: drivers/usb/gadget/function/*uvc* 15008F: drivers/usb/gadget/function/*uvc*
15009F: drivers/usb/gadget/legacy/webcam.c 15009F: drivers/usb/gadget/legacy/webcam.c
15010F: include/uapi/linux/usb/g_uvc.h
15010 15011
15011USB WIRELESS RNDIS DRIVER (rndis_wlan) 15012USB WIRELESS RNDIS DRIVER (rndis_wlan)
15012M: Jussi Kivilinna <jussi.kivilinna@iki.fi> 15013M: Jussi Kivilinna <jussi.kivilinna@iki.fi>
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index 1c36a6a9dd63..55d5ae2a7ec7 100644
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -73,17 +73,17 @@ int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
73 /* Backup global regs */ 73 /* Backup global regs */
74 gr = &hsotg->gr_backup; 74 gr = &hsotg->gr_backup;
75 75
76 gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 76 gr->gotgctl = dwc2_readl(hsotg, GOTGCTL);
77 gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 77 gr->gintmsk = dwc2_readl(hsotg, GINTMSK);
78 gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 78 gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG);
79 gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 79 gr->gusbcfg = dwc2_readl(hsotg, GUSBCFG);
80 gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 80 gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
81 gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 81 gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
82 gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); 82 gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
83 gr->pcgcctl1 = dwc2_readl(hsotg->regs + PCGCCTL1); 83 gr->pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
84 gr->glpmcfg = dwc2_readl(hsotg->regs + GLPMCFG); 84 gr->glpmcfg = dwc2_readl(hsotg, GLPMCFG);
85 gr->gi2cctl = dwc2_readl(hsotg->regs + GI2CCTL); 85 gr->gi2cctl = dwc2_readl(hsotg, GI2CCTL);
86 gr->pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 86 gr->pcgcctl = dwc2_readl(hsotg, PCGCTL);
87 87
88 gr->valid = true; 88 gr->valid = true;
89 return 0; 89 return 0;
@@ -111,18 +111,18 @@ int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
111 } 111 }
112 gr->valid = false; 112 gr->valid = false;
113 113
114 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 114 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
115 dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL); 115 dwc2_writel(hsotg, gr->gotgctl, GOTGCTL);
116 dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK); 116 dwc2_writel(hsotg, gr->gintmsk, GINTMSK);
117 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG); 117 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
118 dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG); 118 dwc2_writel(hsotg, gr->gahbcfg, GAHBCFG);
119 dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ); 119 dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ);
120 dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ); 120 dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ);
121 dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG); 121 dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG);
122 dwc2_writel(gr->pcgcctl1, hsotg->regs + PCGCCTL1); 122 dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1);
123 dwc2_writel(gr->glpmcfg, hsotg->regs + GLPMCFG); 123 dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG);
124 dwc2_writel(gr->pcgcctl, hsotg->regs + PCGCTL); 124 dwc2_writel(hsotg, gr->pcgcctl, PCGCTL);
125 dwc2_writel(gr->gi2cctl, hsotg->regs + GI2CCTL); 125 dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL);
126 126
127 return 0; 127 return 0;
128} 128}
@@ -141,17 +141,17 @@ int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore)
141 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL) 141 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL)
142 return -ENOTSUPP; 142 return -ENOTSUPP;
143 143
144 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 144 pcgcctl = dwc2_readl(hsotg, PCGCTL);
145 pcgcctl &= ~PCGCTL_STOPPCLK; 145 pcgcctl &= ~PCGCTL_STOPPCLK;
146 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 146 dwc2_writel(hsotg, pcgcctl, PCGCTL);
147 147
148 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 148 pcgcctl = dwc2_readl(hsotg, PCGCTL);
149 pcgcctl &= ~PCGCTL_PWRCLMP; 149 pcgcctl &= ~PCGCTL_PWRCLMP;
150 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 150 dwc2_writel(hsotg, pcgcctl, PCGCTL);
151 151
152 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 152 pcgcctl = dwc2_readl(hsotg, PCGCTL);
153 pcgcctl &= ~PCGCTL_RSTPDWNMODULE; 153 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
154 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 154 dwc2_writel(hsotg, pcgcctl, PCGCTL);
155 155
156 udelay(100); 156 udelay(100);
157 if (restore) { 157 if (restore) {
@@ -222,21 +222,21 @@ int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg)
222 * Clear any pending interrupts since dwc2 will not be able to 222 * Clear any pending interrupts since dwc2 will not be able to
223 * clear them after entering partial_power_down. 223 * clear them after entering partial_power_down.
224 */ 224 */
225 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 225 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
226 226
227 /* Put the controller in low power state */ 227 /* Put the controller in low power state */
228 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 228 pcgcctl = dwc2_readl(hsotg, PCGCTL);
229 229
230 pcgcctl |= PCGCTL_PWRCLMP; 230 pcgcctl |= PCGCTL_PWRCLMP;
231 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 231 dwc2_writel(hsotg, pcgcctl, PCGCTL);
232 ndelay(20); 232 ndelay(20);
233 233
234 pcgcctl |= PCGCTL_RSTPDWNMODULE; 234 pcgcctl |= PCGCTL_RSTPDWNMODULE;
235 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 235 dwc2_writel(hsotg, pcgcctl, PCGCTL);
236 ndelay(20); 236 ndelay(20);
237 237
238 pcgcctl |= PCGCTL_STOPPCLK; 238 pcgcctl |= PCGCTL_STOPPCLK;
239 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 239 dwc2_writel(hsotg, pcgcctl, PCGCTL);
240 240
241 return ret; 241 return ret;
242} 242}
@@ -272,39 +272,39 @@ static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode,
272 if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK)) 272 if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK))
273 pcgcctl |= BIT(17); 273 pcgcctl |= BIT(17);
274 } 274 }
275 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 275 dwc2_writel(hsotg, pcgcctl, PCGCTL);
276 276
277 /* Umnask global Interrupt in GAHBCFG and restore it */ 277 /* Umnask global Interrupt in GAHBCFG and restore it */
278 dwc2_writel(gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG); 278 dwc2_writel(hsotg, gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, GAHBCFG);
279 279
280 /* Clear all pending interupts */ 280 /* Clear all pending interupts */
281 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 281 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
282 282
283 /* Unmask restore done interrupt */ 283 /* Unmask restore done interrupt */
284 dwc2_writel(GINTSTS_RESTOREDONE, hsotg->regs + GINTMSK); 284 dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTMSK);
285 285
286 /* Restore GUSBCFG and HCFG/DCFG */ 286 /* Restore GUSBCFG and HCFG/DCFG */
287 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG); 287 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
288 288
289 if (is_host) { 289 if (is_host) {
290 dwc2_writel(hr->hcfg, hsotg->regs + HCFG); 290 dwc2_writel(hsotg, hr->hcfg, HCFG);
291 if (rmode) 291 if (rmode)
292 pcgcctl |= PCGCTL_RESTOREMODE; 292 pcgcctl |= PCGCTL_RESTOREMODE;
293 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 293 dwc2_writel(hsotg, pcgcctl, PCGCTL);
294 udelay(10); 294 udelay(10);
295 295
296 pcgcctl |= PCGCTL_ESS_REG_RESTORED; 296 pcgcctl |= PCGCTL_ESS_REG_RESTORED;
297 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 297 dwc2_writel(hsotg, pcgcctl, PCGCTL);
298 udelay(10); 298 udelay(10);
299 } else { 299 } else {
300 dwc2_writel(dr->dcfg, hsotg->regs + DCFG); 300 dwc2_writel(hsotg, dr->dcfg, DCFG);
301 if (!rmode) 301 if (!rmode)
302 pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE; 302 pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE;
303 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 303 dwc2_writel(hsotg, pcgcctl, PCGCTL);
304 udelay(10); 304 udelay(10);
305 305
306 pcgcctl |= PCGCTL_ESS_REG_RESTORED; 306 pcgcctl |= PCGCTL_ESS_REG_RESTORED;
307 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 307 dwc2_writel(hsotg, pcgcctl, PCGCTL);
308 udelay(10); 308 udelay(10);
309 } 309 }
310} 310}
@@ -322,42 +322,42 @@ void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
322 u32 gpwrdn; 322 u32 gpwrdn;
323 323
324 /* Switch-on voltage to the core */ 324 /* Switch-on voltage to the core */
325 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 325 gpwrdn = dwc2_readl(hsotg, GPWRDN);
326 gpwrdn &= ~GPWRDN_PWRDNSWTCH; 326 gpwrdn &= ~GPWRDN_PWRDNSWTCH;
327 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 327 dwc2_writel(hsotg, gpwrdn, GPWRDN);
328 udelay(10); 328 udelay(10);
329 329
330 /* Reset core */ 330 /* Reset core */
331 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 331 gpwrdn = dwc2_readl(hsotg, GPWRDN);
332 gpwrdn &= ~GPWRDN_PWRDNRSTN; 332 gpwrdn &= ~GPWRDN_PWRDNRSTN;
333 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 333 dwc2_writel(hsotg, gpwrdn, GPWRDN);
334 udelay(10); 334 udelay(10);
335 335
336 /* Enable restore from PMU */ 336 /* Enable restore from PMU */
337 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 337 gpwrdn = dwc2_readl(hsotg, GPWRDN);
338 gpwrdn |= GPWRDN_RESTORE; 338 gpwrdn |= GPWRDN_RESTORE;
339 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 339 dwc2_writel(hsotg, gpwrdn, GPWRDN);
340 udelay(10); 340 udelay(10);
341 341
342 /* Disable Power Down Clamp */ 342 /* Disable Power Down Clamp */
343 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 343 gpwrdn = dwc2_readl(hsotg, GPWRDN);
344 gpwrdn &= ~GPWRDN_PWRDNCLMP; 344 gpwrdn &= ~GPWRDN_PWRDNCLMP;
345 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 345 dwc2_writel(hsotg, gpwrdn, GPWRDN);
346 udelay(50); 346 udelay(50);
347 347
348 if (!is_host && rem_wakeup) 348 if (!is_host && rem_wakeup)
349 udelay(70); 349 udelay(70);
350 350
351 /* Deassert reset core */ 351 /* Deassert reset core */
352 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 352 gpwrdn = dwc2_readl(hsotg, GPWRDN);
353 gpwrdn |= GPWRDN_PWRDNRSTN; 353 gpwrdn |= GPWRDN_PWRDNRSTN;
354 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 354 dwc2_writel(hsotg, gpwrdn, GPWRDN);
355 udelay(10); 355 udelay(10);
356 356
357 /* Disable PMU interrupt */ 357 /* Disable PMU interrupt */
358 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 358 gpwrdn = dwc2_readl(hsotg, GPWRDN);
359 gpwrdn &= ~GPWRDN_PMUINTSEL; 359 gpwrdn &= ~GPWRDN_PMUINTSEL;
360 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 360 dwc2_writel(hsotg, gpwrdn, GPWRDN);
361 udelay(10); 361 udelay(10);
362 362
363 /* Set Restore Essential Regs bit in PCGCCTL register */ 363 /* Set Restore Essential Regs bit in PCGCCTL register */
@@ -431,7 +431,7 @@ static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
431 return false; 431 return false;
432 432
433 /* Check if core configuration includes the IDDIG filter. */ 433 /* Check if core configuration includes the IDDIG filter. */
434 ghwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); 434 ghwcfg4 = dwc2_readl(hsotg, GHWCFG4);
435 if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN)) 435 if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN))
436 return false; 436 return false;
437 437
@@ -439,9 +439,9 @@ static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
439 * Check if the IDDIG debounce filter is bypassed. Available 439 * Check if the IDDIG debounce filter is bypassed. Available
440 * in core version >= 3.10a. 440 * in core version >= 3.10a.
441 */ 441 */
442 gsnpsid = dwc2_readl(hsotg->regs + GSNPSID); 442 gsnpsid = dwc2_readl(hsotg, GSNPSID);
443 if (gsnpsid >= DWC2_CORE_REV_3_10a) { 443 if (gsnpsid >= DWC2_CORE_REV_3_10a) {
444 u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 444 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
445 445
446 if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS) 446 if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS)
447 return false; 447 return false;
@@ -510,8 +510,8 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
510 * reset and account for this delay after the reset. 510 * reset and account for this delay after the reset.
511 */ 511 */
512 if (dwc2_iddig_filter_enabled(hsotg)) { 512 if (dwc2_iddig_filter_enabled(hsotg)) {
513 u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 513 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
514 u32 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 514 u32 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
515 515
516 if (!(gotgctl & GOTGCTL_CONID_B) || 516 if (!(gotgctl & GOTGCTL_CONID_B) ||
517 (gusbcfg & GUSBCFG_FORCEHOSTMODE)) { 517 (gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
@@ -520,9 +520,9 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
520 } 520 }
521 521
522 /* Core Soft Reset */ 522 /* Core Soft Reset */
523 greset = dwc2_readl(hsotg->regs + GRSTCTL); 523 greset = dwc2_readl(hsotg, GRSTCTL);
524 greset |= GRSTCTL_CSFTRST; 524 greset |= GRSTCTL_CSFTRST;
525 dwc2_writel(greset, hsotg->regs + GRSTCTL); 525 dwc2_writel(hsotg, greset, GRSTCTL);
526 526
527 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_CSFTRST, 50)) { 527 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_CSFTRST, 50)) {
528 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL GRSTCTL_CSFTRST\n", 528 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL GRSTCTL_CSFTRST\n",
@@ -594,14 +594,14 @@ void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
594 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST)) 594 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))
595 return; 595 return;
596 596
597 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 597 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
598 598
599 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE; 599 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
600 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE; 600 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
601 601
602 gusbcfg &= ~clear; 602 gusbcfg &= ~clear;
603 gusbcfg |= set; 603 gusbcfg |= set;
604 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); 604 dwc2_writel(hsotg, gusbcfg, GUSBCFG);
605 605
606 dwc2_wait_for_mode(hsotg, host); 606 dwc2_wait_for_mode(hsotg, host);
607 return; 607 return;
@@ -627,10 +627,10 @@ static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
627 627
628 dev_dbg(hsotg->dev, "Clearing force mode bits\n"); 628 dev_dbg(hsotg->dev, "Clearing force mode bits\n");
629 629
630 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 630 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
631 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; 631 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
632 gusbcfg &= ~GUSBCFG_FORCEDEVMODE; 632 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
633 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); 633 dwc2_writel(hsotg, gusbcfg, GUSBCFG);
634 634
635 if (dwc2_iddig_filter_enabled(hsotg)) 635 if (dwc2_iddig_filter_enabled(hsotg))
636 msleep(100); 636 msleep(100);
@@ -670,11 +670,11 @@ void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
670void dwc2_enable_acg(struct dwc2_hsotg *hsotg) 670void dwc2_enable_acg(struct dwc2_hsotg *hsotg)
671{ 671{
672 if (hsotg->params.acg_enable) { 672 if (hsotg->params.acg_enable) {
673 u32 pcgcctl1 = dwc2_readl(hsotg->regs + PCGCCTL1); 673 u32 pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
674 674
675 dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n"); 675 dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n");
676 pcgcctl1 |= PCGCCTL1_GATEEN; 676 pcgcctl1 |= PCGCCTL1_GATEEN;
677 dwc2_writel(pcgcctl1, hsotg->regs + PCGCCTL1); 677 dwc2_writel(hsotg, pcgcctl1, PCGCCTL1);
678 } 678 }
679} 679}
680 680
@@ -695,56 +695,57 @@ void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
695 dev_dbg(hsotg->dev, "Host Global Registers\n"); 695 dev_dbg(hsotg->dev, "Host Global Registers\n");
696 addr = hsotg->regs + HCFG; 696 addr = hsotg->regs + HCFG;
697 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", 697 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
698 (unsigned long)addr, dwc2_readl(addr)); 698 (unsigned long)addr, dwc2_readl(hsotg, HCFG));
699 addr = hsotg->regs + HFIR; 699 addr = hsotg->regs + HFIR;
700 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", 700 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n",
701 (unsigned long)addr, dwc2_readl(addr)); 701 (unsigned long)addr, dwc2_readl(hsotg, HFIR));
702 addr = hsotg->regs + HFNUM; 702 addr = hsotg->regs + HFNUM;
703 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", 703 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n",
704 (unsigned long)addr, dwc2_readl(addr)); 704 (unsigned long)addr, dwc2_readl(hsotg, HFNUM));
705 addr = hsotg->regs + HPTXSTS; 705 addr = hsotg->regs + HPTXSTS;
706 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", 706 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n",
707 (unsigned long)addr, dwc2_readl(addr)); 707 (unsigned long)addr, dwc2_readl(hsotg, HPTXSTS));
708 addr = hsotg->regs + HAINT; 708 addr = hsotg->regs + HAINT;
709 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", 709 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n",
710 (unsigned long)addr, dwc2_readl(addr)); 710 (unsigned long)addr, dwc2_readl(hsotg, HAINT));
711 addr = hsotg->regs + HAINTMSK; 711 addr = hsotg->regs + HAINTMSK;
712 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", 712 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
713 (unsigned long)addr, dwc2_readl(addr)); 713 (unsigned long)addr, dwc2_readl(hsotg, HAINTMSK));
714 if (hsotg->params.dma_desc_enable) { 714 if (hsotg->params.dma_desc_enable) {
715 addr = hsotg->regs + HFLBADDR; 715 addr = hsotg->regs + HFLBADDR;
716 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", 716 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
717 (unsigned long)addr, dwc2_readl(addr)); 717 (unsigned long)addr, dwc2_readl(hsotg, HFLBADDR));
718 } 718 }
719 719
720 addr = hsotg->regs + HPRT0; 720 addr = hsotg->regs + HPRT0;
721 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", 721 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
722 (unsigned long)addr, dwc2_readl(addr)); 722 (unsigned long)addr, dwc2_readl(hsotg, HPRT0));
723 723
724 for (i = 0; i < hsotg->params.host_channels; i++) { 724 for (i = 0; i < hsotg->params.host_channels; i++) {
725 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); 725 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
726 addr = hsotg->regs + HCCHAR(i); 726 addr = hsotg->regs + HCCHAR(i);
727 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", 727 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
728 (unsigned long)addr, dwc2_readl(addr)); 728 (unsigned long)addr, dwc2_readl(hsotg, HCCHAR(i)));
729 addr = hsotg->regs + HCSPLT(i); 729 addr = hsotg->regs + HCSPLT(i);
730 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", 730 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n",
731 (unsigned long)addr, dwc2_readl(addr)); 731 (unsigned long)addr, dwc2_readl(hsotg, HCSPLT(i)));
732 addr = hsotg->regs + HCINT(i); 732 addr = hsotg->regs + HCINT(i);
733 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", 733 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n",
734 (unsigned long)addr, dwc2_readl(addr)); 734 (unsigned long)addr, dwc2_readl(hsotg, HCINT(i)));
735 addr = hsotg->regs + HCINTMSK(i); 735 addr = hsotg->regs + HCINTMSK(i);
736 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", 736 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n",
737 (unsigned long)addr, dwc2_readl(addr)); 737 (unsigned long)addr, dwc2_readl(hsotg, HCINTMSK(i)));
738 addr = hsotg->regs + HCTSIZ(i); 738 addr = hsotg->regs + HCTSIZ(i);
739 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", 739 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n",
740 (unsigned long)addr, dwc2_readl(addr)); 740 (unsigned long)addr, dwc2_readl(hsotg, HCTSIZ(i)));
741 addr = hsotg->regs + HCDMA(i); 741 addr = hsotg->regs + HCDMA(i);
742 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", 742 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
743 (unsigned long)addr, dwc2_readl(addr)); 743 (unsigned long)addr, dwc2_readl(hsotg, HCDMA(i)));
744 if (hsotg->params.dma_desc_enable) { 744 if (hsotg->params.dma_desc_enable) {
745 addr = hsotg->regs + HCDMAB(i); 745 addr = hsotg->regs + HCDMAB(i);
746 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", 746 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
747 (unsigned long)addr, dwc2_readl(addr)); 747 (unsigned long)addr, dwc2_readl(hsotg,
748 HCDMAB(i)));
748 } 749 }
749 } 750 }
750#endif 751#endif
@@ -766,80 +767,80 @@ void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
766 dev_dbg(hsotg->dev, "Core Global Registers\n"); 767 dev_dbg(hsotg->dev, "Core Global Registers\n");
767 addr = hsotg->regs + GOTGCTL; 768 addr = hsotg->regs + GOTGCTL;
768 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", 769 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
769 (unsigned long)addr, dwc2_readl(addr)); 770 (unsigned long)addr, dwc2_readl(hsotg, GOTGCTL));
770 addr = hsotg->regs + GOTGINT; 771 addr = hsotg->regs + GOTGINT;
771 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", 772 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n",
772 (unsigned long)addr, dwc2_readl(addr)); 773 (unsigned long)addr, dwc2_readl(hsotg, GOTGINT));
773 addr = hsotg->regs + GAHBCFG; 774 addr = hsotg->regs + GAHBCFG;
774 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", 775 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n",
775 (unsigned long)addr, dwc2_readl(addr)); 776 (unsigned long)addr, dwc2_readl(hsotg, GAHBCFG));
776 addr = hsotg->regs + GUSBCFG; 777 addr = hsotg->regs + GUSBCFG;
777 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", 778 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n",
778 (unsigned long)addr, dwc2_readl(addr)); 779 (unsigned long)addr, dwc2_readl(hsotg, GUSBCFG));
779 addr = hsotg->regs + GRSTCTL; 780 addr = hsotg->regs + GRSTCTL;
780 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", 781 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n",
781 (unsigned long)addr, dwc2_readl(addr)); 782 (unsigned long)addr, dwc2_readl(hsotg, GRSTCTL));
782 addr = hsotg->regs + GINTSTS; 783 addr = hsotg->regs + GINTSTS;
783 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", 784 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n",
784 (unsigned long)addr, dwc2_readl(addr)); 785 (unsigned long)addr, dwc2_readl(hsotg, GINTSTS));
785 addr = hsotg->regs + GINTMSK; 786 addr = hsotg->regs + GINTMSK;
786 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", 787 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n",
787 (unsigned long)addr, dwc2_readl(addr)); 788 (unsigned long)addr, dwc2_readl(hsotg, GINTMSK));
788 addr = hsotg->regs + GRXSTSR; 789 addr = hsotg->regs + GRXSTSR;
789 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", 790 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n",
790 (unsigned long)addr, dwc2_readl(addr)); 791 (unsigned long)addr, dwc2_readl(hsotg, GRXSTSR));
791 addr = hsotg->regs + GRXFSIZ; 792 addr = hsotg->regs + GRXFSIZ;
792 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", 793 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n",
793 (unsigned long)addr, dwc2_readl(addr)); 794 (unsigned long)addr, dwc2_readl(hsotg, GRXFSIZ));
794 addr = hsotg->regs + GNPTXFSIZ; 795 addr = hsotg->regs + GNPTXFSIZ;
795 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", 796 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n",
796 (unsigned long)addr, dwc2_readl(addr)); 797 (unsigned long)addr, dwc2_readl(hsotg, GNPTXFSIZ));
797 addr = hsotg->regs + GNPTXSTS; 798 addr = hsotg->regs + GNPTXSTS;
798 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", 799 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n",
799 (unsigned long)addr, dwc2_readl(addr)); 800 (unsigned long)addr, dwc2_readl(hsotg, GNPTXSTS));
800 addr = hsotg->regs + GI2CCTL; 801 addr = hsotg->regs + GI2CCTL;
801 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", 802 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n",
802 (unsigned long)addr, dwc2_readl(addr)); 803 (unsigned long)addr, dwc2_readl(hsotg, GI2CCTL));
803 addr = hsotg->regs + GPVNDCTL; 804 addr = hsotg->regs + GPVNDCTL;
804 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", 805 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n",
805 (unsigned long)addr, dwc2_readl(addr)); 806 (unsigned long)addr, dwc2_readl(hsotg, GPVNDCTL));
806 addr = hsotg->regs + GGPIO; 807 addr = hsotg->regs + GGPIO;
807 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", 808 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n",
808 (unsigned long)addr, dwc2_readl(addr)); 809 (unsigned long)addr, dwc2_readl(hsotg, GGPIO));
809 addr = hsotg->regs + GUID; 810 addr = hsotg->regs + GUID;
810 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", 811 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n",
811 (unsigned long)addr, dwc2_readl(addr)); 812 (unsigned long)addr, dwc2_readl(hsotg, GUID));
812 addr = hsotg->regs + GSNPSID; 813 addr = hsotg->regs + GSNPSID;
813 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", 814 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n",
814 (unsigned long)addr, dwc2_readl(addr)); 815 (unsigned long)addr, dwc2_readl(hsotg, GSNPSID));
815 addr = hsotg->regs + GHWCFG1; 816 addr = hsotg->regs + GHWCFG1;
816 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", 817 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n",
817 (unsigned long)addr, dwc2_readl(addr)); 818 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG1));
818 addr = hsotg->regs + GHWCFG2; 819 addr = hsotg->regs + GHWCFG2;
819 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", 820 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n",
820 (unsigned long)addr, dwc2_readl(addr)); 821 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG2));
821 addr = hsotg->regs + GHWCFG3; 822 addr = hsotg->regs + GHWCFG3;
822 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", 823 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n",
823 (unsigned long)addr, dwc2_readl(addr)); 824 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG3));
824 addr = hsotg->regs + GHWCFG4; 825 addr = hsotg->regs + GHWCFG4;
825 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", 826 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n",
826 (unsigned long)addr, dwc2_readl(addr)); 827 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG4));
827 addr = hsotg->regs + GLPMCFG; 828 addr = hsotg->regs + GLPMCFG;
828 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", 829 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n",
829 (unsigned long)addr, dwc2_readl(addr)); 830 (unsigned long)addr, dwc2_readl(hsotg, GLPMCFG));
830 addr = hsotg->regs + GPWRDN; 831 addr = hsotg->regs + GPWRDN;
831 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", 832 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n",
832 (unsigned long)addr, dwc2_readl(addr)); 833 (unsigned long)addr, dwc2_readl(hsotg, GPWRDN));
833 addr = hsotg->regs + GDFIFOCFG; 834 addr = hsotg->regs + GDFIFOCFG;
834 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", 835 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n",
835 (unsigned long)addr, dwc2_readl(addr)); 836 (unsigned long)addr, dwc2_readl(hsotg, GDFIFOCFG));
836 addr = hsotg->regs + HPTXFSIZ; 837 addr = hsotg->regs + HPTXFSIZ;
837 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", 838 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n",
838 (unsigned long)addr, dwc2_readl(addr)); 839 (unsigned long)addr, dwc2_readl(hsotg, HPTXFSIZ));
839 840
840 addr = hsotg->regs + PCGCTL; 841 addr = hsotg->regs + PCGCTL;
841 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", 842 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n",
842 (unsigned long)addr, dwc2_readl(addr)); 843 (unsigned long)addr, dwc2_readl(hsotg, PCGCTL));
843#endif 844#endif
844} 845}
845 846
@@ -862,7 +863,7 @@ void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
862 863
863 greset = GRSTCTL_TXFFLSH; 864 greset = GRSTCTL_TXFFLSH;
864 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK; 865 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
865 dwc2_writel(greset, hsotg->regs + GRSTCTL); 866 dwc2_writel(hsotg, greset, GRSTCTL);
866 867
867 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000)) 868 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000))
868 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n", 869 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n",
@@ -889,7 +890,7 @@ void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
889 __func__); 890 __func__);
890 891
891 greset = GRSTCTL_RXFFLSH; 892 greset = GRSTCTL_RXFFLSH;
892 dwc2_writel(greset, hsotg->regs + GRSTCTL); 893 dwc2_writel(hsotg, greset, GRSTCTL);
893 894
894 /* Wait for RxFIFO flush done */ 895 /* Wait for RxFIFO flush done */
895 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_RXFFLSH, 10000)) 896 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_RXFFLSH, 10000))
@@ -902,7 +903,7 @@ void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
902 903
903bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) 904bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
904{ 905{
905 if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff) 906 if (dwc2_readl(hsotg, GSNPSID) == 0xffffffff)
906 return false; 907 return false;
907 else 908 else
908 return true; 909 return true;
@@ -916,10 +917,10 @@ bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
916 */ 917 */
917void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) 918void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
918{ 919{
919 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 920 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
920 921
921 ahbcfg |= GAHBCFG_GLBL_INTR_EN; 922 ahbcfg |= GAHBCFG_GLBL_INTR_EN;
922 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 923 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
923} 924}
924 925
925/** 926/**
@@ -930,16 +931,16 @@ void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
930 */ 931 */
931void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) 932void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
932{ 933{
933 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 934 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
934 935
935 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 936 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
936 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 937 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
937} 938}
938 939
939/* Returns the controller's GHWCFG2.OTG_MODE. */ 940/* Returns the controller's GHWCFG2.OTG_MODE. */
940unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg) 941unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg)
941{ 942{
942 u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); 943 u32 ghwcfg2 = dwc2_readl(hsotg, GHWCFG2);
943 944
944 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >> 945 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
945 GHWCFG2_OP_MODE_SHIFT; 946 GHWCFG2_OP_MODE_SHIFT;
@@ -988,7 +989,7 @@ int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
988 u32 i; 989 u32 i;
989 990
990 for (i = 0; i < timeout; i++) { 991 for (i = 0; i < timeout; i++) {
991 if (dwc2_readl(hsotg->regs + offset) & mask) 992 if (dwc2_readl(hsotg, offset) & mask)
992 return 0; 993 return 0;
993 udelay(1); 994 udelay(1);
994 } 995 }
@@ -1011,7 +1012,7 @@ int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
1011 u32 i; 1012 u32 i;
1012 1013
1013 for (i = 0; i < timeout; i++) { 1014 for (i = 0; i < timeout; i++) {
1014 if (!(dwc2_readl(hsotg->regs + offset) & mask)) 1015 if (!(dwc2_readl(hsotg, offset) & mask))
1015 return 0; 1016 return 0;
1016 udelay(1); 1017 udelay(1);
1017 } 1018 }
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index 71b3b08ad516..cc9c93affa14 100644
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -65,60 +65,6 @@
65 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ 65 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \
66 dev_name(hsotg->dev), ##__VA_ARGS__) 66 dev_name(hsotg->dev), ##__VA_ARGS__)
67 67
68#ifdef CONFIG_MIPS
69/*
70 * There are some MIPS machines that can run in either big-endian
71 * or little-endian mode and that use the dwc2 register without
72 * a byteswap in both ways.
73 * Unlike other architectures, MIPS apparently does not require a
74 * barrier before the __raw_writel() to synchronize with DMA but does
75 * require the barrier after the __raw_writel() to serialize a set of
76 * writes. This set of operations was added specifically for MIPS and
77 * should only be used there.
78 */
79static inline u32 dwc2_readl(const void __iomem *addr)
80{
81 u32 value = __raw_readl(addr);
82
83 /* In order to preserve endianness __raw_* operation is used. Therefore
84 * a barrier is needed to ensure IO access is not re-ordered across
85 * reads or writes
86 */
87 mb();
88 return value;
89}
90
91static inline void dwc2_writel(u32 value, void __iomem *addr)
92{
93 __raw_writel(value, addr);
94
95 /*
96 * In order to preserve endianness __raw_* operation is used. Therefore
97 * a barrier is needed to ensure IO access is not re-ordered across
98 * reads or writes
99 */
100 mb();
101#ifdef DWC2_LOG_WRITES
102 pr_info("INFO:: wrote %08x to %p\n", value, addr);
103#endif
104}
105#else
106/* Normal architectures just use readl/write */
107static inline u32 dwc2_readl(const void __iomem *addr)
108{
109 return readl(addr);
110}
111
112static inline void dwc2_writel(u32 value, void __iomem *addr)
113{
114 writel(value, addr);
115
116#ifdef DWC2_LOG_WRITES
117 pr_info("info:: wrote %08x to %p\n", value, addr);
118#endif
119}
120#endif
121
122/* Maximum number of Endpoints/HostChannels */ 68/* Maximum number of Endpoints/HostChannels */
123#define MAX_EPS_CHANNELS 16 69#define MAX_EPS_CHANNELS 16
124 70
@@ -911,6 +857,7 @@ struct dwc2_hregs_backup {
911 * @gr_backup: Backup of global registers during suspend 857 * @gr_backup: Backup of global registers during suspend
912 * @dr_backup: Backup of device registers during suspend 858 * @dr_backup: Backup of device registers during suspend
913 * @hr_backup: Backup of host registers during suspend 859 * @hr_backup: Backup of host registers during suspend
860 * @needs_byte_swap: Specifies whether the opposite endianness.
914 * 861 *
915 * These are for host mode: 862 * These are for host mode:
916 * 863 *
@@ -1100,6 +1047,7 @@ struct dwc2_hsotg {
1100 1047
1101 struct dentry *debug_root; 1048 struct dentry *debug_root;
1102 struct debugfs_regset32 *regset; 1049 struct debugfs_regset32 *regset;
1050 bool needs_byte_swap;
1103 1051
1104 /* DWC OTG HW Release versions */ 1052 /* DWC OTG HW Release versions */
1105#define DWC2_CORE_REV_2_71a 0x4f54271a 1053#define DWC2_CORE_REV_2_71a 0x4f54271a
@@ -1215,6 +1163,55 @@ struct dwc2_hsotg {
1215#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 1163#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
1216}; 1164};
1217 1165
1166/* Normal architectures just use readl/write */
1167static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset)
1168{
1169 u32 val;
1170
1171 val = readl(hsotg->regs + offset);
1172 if (hsotg->needs_byte_swap)
1173 return swab32(val);
1174 else
1175 return val;
1176}
1177
1178static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset)
1179{
1180 if (hsotg->needs_byte_swap)
1181 writel(swab32(value), hsotg->regs + offset);
1182 else
1183 writel(value, hsotg->regs + offset);
1184
1185#ifdef DWC2_LOG_WRITES
1186 pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset);
1187#endif
1188}
1189
1190static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset,
1191 void *buffer, unsigned int count)
1192{
1193 if (count) {
1194 u32 *buf = buffer;
1195
1196 do {
1197 u32 x = dwc2_readl(hsotg, offset);
1198 *buf++ = x;
1199 } while (--count);
1200 }
1201}
1202
1203static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset,
1204 const void *buffer, unsigned int count)
1205{
1206 if (count) {
1207 const u32 *buf = buffer;
1208
1209 do {
1210 dwc2_writel(hsotg, *buf++, offset);
1211 } while (--count);
1212 }
1213}
1214
1218/* Reasons for halting a host channel */ 1215/* Reasons for halting a host channel */
1219enum dwc2_halt_status { 1216enum dwc2_halt_status {
1220 DWC2_HC_XFER_NO_HALT_STATUS, 1217 DWC2_HC_XFER_NO_HALT_STATUS,
@@ -1320,12 +1317,12 @@ bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1320 */ 1317 */
1321static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 1318static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1322{ 1319{
1323 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 1320 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1324} 1321}
1325 1322
1326static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 1323static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1327{ 1324{
1328 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 1325 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1329} 1326}
1330 1327
1331/* 1328/*
diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index cc90b58b6b3c..19ae2595f1c3 100644
--- a/drivers/usb/dwc2/core_intr.c
+++ b/drivers/usb/dwc2/core_intr.c
@@ -81,11 +81,11 @@ static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg)
81 */ 81 */
82static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg) 82static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
83{ 83{
84 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 84 u32 hprt0 = dwc2_readl(hsotg, HPRT0);
85 85
86 if (hprt0 & HPRT0_ENACHG) { 86 if (hprt0 & HPRT0_ENACHG) {
87 hprt0 &= ~HPRT0_ENA; 87 hprt0 &= ~HPRT0_ENA;
88 dwc2_writel(hprt0, hsotg->regs + HPRT0); 88 dwc2_writel(hsotg, hprt0, HPRT0);
89 } 89 }
90} 90}
91 91
@@ -97,7 +97,7 @@ static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
97static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg) 97static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg)
98{ 98{
99 /* Clear interrupt */ 99 /* Clear interrupt */
100 dwc2_writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS); 100 dwc2_writel(hsotg, GINTSTS_MODEMIS, GINTSTS);
101 101
102 dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n", 102 dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n",
103 dwc2_is_host_mode(hsotg) ? "Host" : "Device"); 103 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
@@ -115,8 +115,8 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
115 u32 gotgctl; 115 u32 gotgctl;
116 u32 gintmsk; 116 u32 gintmsk;
117 117
118 gotgint = dwc2_readl(hsotg->regs + GOTGINT); 118 gotgint = dwc2_readl(hsotg, GOTGINT);
119 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 119 gotgctl = dwc2_readl(hsotg, GOTGCTL);
120 dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint, 120 dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint,
121 dwc2_op_state_str(hsotg)); 121 dwc2_op_state_str(hsotg));
122 122
@@ -124,7 +124,7 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
124 dev_dbg(hsotg->dev, 124 dev_dbg(hsotg->dev,
125 " ++OTG Interrupt: Session End Detected++ (%s)\n", 125 " ++OTG Interrupt: Session End Detected++ (%s)\n",
126 dwc2_op_state_str(hsotg)); 126 dwc2_op_state_str(hsotg));
127 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 127 gotgctl = dwc2_readl(hsotg, GOTGCTL);
128 128
129 if (dwc2_is_device_mode(hsotg)) 129 if (dwc2_is_device_mode(hsotg))
130 dwc2_hsotg_disconnect(hsotg); 130 dwc2_hsotg_disconnect(hsotg);
@@ -150,24 +150,24 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
150 hsotg->lx_state = DWC2_L0; 150 hsotg->lx_state = DWC2_L0;
151 } 151 }
152 152
153 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 153 gotgctl = dwc2_readl(hsotg, GOTGCTL);
154 gotgctl &= ~GOTGCTL_DEVHNPEN; 154 gotgctl &= ~GOTGCTL_DEVHNPEN;
155 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); 155 dwc2_writel(hsotg, gotgctl, GOTGCTL);
156 } 156 }
157 157
158 if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) { 158 if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) {
159 dev_dbg(hsotg->dev, 159 dev_dbg(hsotg->dev,
160 " ++OTG Interrupt: Session Request Success Status Change++\n"); 160 " ++OTG Interrupt: Session Request Success Status Change++\n");
161 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 161 gotgctl = dwc2_readl(hsotg, GOTGCTL);
162 if (gotgctl & GOTGCTL_SESREQSCS) { 162 if (gotgctl & GOTGCTL_SESREQSCS) {
163 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS && 163 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
164 hsotg->params.i2c_enable) { 164 hsotg->params.i2c_enable) {
165 hsotg->srp_success = 1; 165 hsotg->srp_success = 1;
166 } else { 166 } else {
167 /* Clear Session Request */ 167 /* Clear Session Request */
168 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 168 gotgctl = dwc2_readl(hsotg, GOTGCTL);
169 gotgctl &= ~GOTGCTL_SESREQ; 169 gotgctl &= ~GOTGCTL_SESREQ;
170 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); 170 dwc2_writel(hsotg, gotgctl, GOTGCTL);
171 } 171 }
172 } 172 }
173 } 173 }
@@ -177,7 +177,7 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
177 * Print statements during the HNP interrupt handling 177 * Print statements during the HNP interrupt handling
178 * can cause it to fail 178 * can cause it to fail
179 */ 179 */
180 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 180 gotgctl = dwc2_readl(hsotg, GOTGCTL);
181 /* 181 /*
182 * WA for 3.00a- HW is not setting cur_mode, even sometimes 182 * WA for 3.00a- HW is not setting cur_mode, even sometimes
183 * this does not help 183 * this does not help
@@ -197,9 +197,9 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
197 * interrupt does not get handled and Linux 197 * interrupt does not get handled and Linux
198 * complains loudly. 198 * complains loudly.
199 */ 199 */
200 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 200 gintmsk = dwc2_readl(hsotg, GINTMSK);
201 gintmsk &= ~GINTSTS_SOF; 201 gintmsk &= ~GINTSTS_SOF;
202 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 202 dwc2_writel(hsotg, gintmsk, GINTMSK);
203 203
204 /* 204 /*
205 * Call callback function with spin lock 205 * Call callback function with spin lock
@@ -213,9 +213,9 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
213 hsotg->op_state = OTG_STATE_B_HOST; 213 hsotg->op_state = OTG_STATE_B_HOST;
214 } 214 }
215 } else { 215 } else {
216 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 216 gotgctl = dwc2_readl(hsotg, GOTGCTL);
217 gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN); 217 gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN);
218 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); 218 dwc2_writel(hsotg, gotgctl, GOTGCTL);
219 dev_dbg(hsotg->dev, "HNP Failed\n"); 219 dev_dbg(hsotg->dev, "HNP Failed\n");
220 dev_err(hsotg->dev, 220 dev_err(hsotg->dev,
221 "Device Not Connected/Responding\n"); 221 "Device Not Connected/Responding\n");
@@ -241,9 +241,9 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
241 hsotg->op_state = OTG_STATE_A_PERIPHERAL; 241 hsotg->op_state = OTG_STATE_A_PERIPHERAL;
242 } else { 242 } else {
243 /* Need to disable SOF interrupt immediately */ 243 /* Need to disable SOF interrupt immediately */
244 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 244 gintmsk = dwc2_readl(hsotg, GINTMSK);
245 gintmsk &= ~GINTSTS_SOF; 245 gintmsk &= ~GINTSTS_SOF;
246 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 246 dwc2_writel(hsotg, gintmsk, GINTMSK);
247 spin_unlock(&hsotg->lock); 247 spin_unlock(&hsotg->lock);
248 dwc2_hcd_start(hsotg); 248 dwc2_hcd_start(hsotg);
249 spin_lock(&hsotg->lock); 249 spin_lock(&hsotg->lock);
@@ -258,7 +258,7 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
258 dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n"); 258 dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n");
259 259
260 /* Clear GOTGINT */ 260 /* Clear GOTGINT */
261 dwc2_writel(gotgint, hsotg->regs + GOTGINT); 261 dwc2_writel(hsotg, gotgint, GOTGINT);
262} 262}
263 263
264/** 264/**
@@ -276,12 +276,12 @@ static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
276 u32 gintmsk; 276 u32 gintmsk;
277 277
278 /* Clear interrupt */ 278 /* Clear interrupt */
279 dwc2_writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS); 279 dwc2_writel(hsotg, GINTSTS_CONIDSTSCHNG, GINTSTS);
280 280
281 /* Need to disable SOF interrupt immediately */ 281 /* Need to disable SOF interrupt immediately */
282 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 282 gintmsk = dwc2_readl(hsotg, GINTMSK);
283 gintmsk &= ~GINTSTS_SOF; 283 gintmsk &= ~GINTSTS_SOF;
284 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 284 dwc2_writel(hsotg, gintmsk, GINTMSK);
285 285
286 dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n", 286 dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n",
287 dwc2_is_host_mode(hsotg) ? "Host" : "Device"); 287 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
@@ -314,7 +314,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
314 int ret; 314 int ret;
315 315
316 /* Clear interrupt */ 316 /* Clear interrupt */
317 dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS); 317 dwc2_writel(hsotg, GINTSTS_SESSREQINT, GINTSTS);
318 318
319 dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n", 319 dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n",
320 hsotg->lx_state); 320 hsotg->lx_state);
@@ -351,15 +351,15 @@ static void dwc2_wakeup_from_lpm_l1(struct dwc2_hsotg *hsotg)
351 return; 351 return;
352 } 352 }
353 353
354 glpmcfg = dwc2_readl(hsotg->regs + GLPMCFG); 354 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
355 if (dwc2_is_device_mode(hsotg)) { 355 if (dwc2_is_device_mode(hsotg)) {
356 dev_dbg(hsotg->dev, "Exit from L1 state\n"); 356 dev_dbg(hsotg->dev, "Exit from L1 state\n");
357 glpmcfg &= ~GLPMCFG_ENBLSLPM; 357 glpmcfg &= ~GLPMCFG_ENBLSLPM;
358 glpmcfg &= ~GLPMCFG_HIRD_THRES_EN; 358 glpmcfg &= ~GLPMCFG_HIRD_THRES_EN;
359 dwc2_writel(glpmcfg, hsotg->regs + GLPMCFG); 359 dwc2_writel(hsotg, glpmcfg, GLPMCFG);
360 360
361 do { 361 do {
362 glpmcfg = dwc2_readl(hsotg->regs + GLPMCFG); 362 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
363 363
364 if (!(glpmcfg & (GLPMCFG_COREL1RES_MASK | 364 if (!(glpmcfg & (GLPMCFG_COREL1RES_MASK |
365 GLPMCFG_L1RESUMEOK | GLPMCFG_SLPSTS))) 365 GLPMCFG_L1RESUMEOK | GLPMCFG_SLPSTS)))
@@ -398,7 +398,7 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
398 int ret; 398 int ret;
399 399
400 /* Clear interrupt */ 400 /* Clear interrupt */
401 dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS); 401 dwc2_writel(hsotg, GINTSTS_WKUPINT, GINTSTS);
402 402
403 dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n"); 403 dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n");
404 dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state); 404 dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);
@@ -410,13 +410,13 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
410 410
411 if (dwc2_is_device_mode(hsotg)) { 411 if (dwc2_is_device_mode(hsotg)) {
412 dev_dbg(hsotg->dev, "DSTS=0x%0x\n", 412 dev_dbg(hsotg->dev, "DSTS=0x%0x\n",
413 dwc2_readl(hsotg->regs + DSTS)); 413 dwc2_readl(hsotg, DSTS));
414 if (hsotg->lx_state == DWC2_L2) { 414 if (hsotg->lx_state == DWC2_L2) {
415 u32 dctl = dwc2_readl(hsotg->regs + DCTL); 415 u32 dctl = dwc2_readl(hsotg, DCTL);
416 416
417 /* Clear Remote Wakeup Signaling */ 417 /* Clear Remote Wakeup Signaling */
418 dctl &= ~DCTL_RMTWKUPSIG; 418 dctl &= ~DCTL_RMTWKUPSIG;
419 dwc2_writel(dctl, hsotg->regs + DCTL); 419 dwc2_writel(hsotg, dctl, DCTL);
420 ret = dwc2_exit_partial_power_down(hsotg, true); 420 ret = dwc2_exit_partial_power_down(hsotg, true);
421 if (ret && (ret != -ENOTSUPP)) 421 if (ret && (ret != -ENOTSUPP))
422 dev_err(hsotg->dev, "exit power_down failed\n"); 422 dev_err(hsotg->dev, "exit power_down failed\n");
@@ -430,11 +430,11 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
430 return; 430 return;
431 431
432 if (hsotg->lx_state != DWC2_L1) { 432 if (hsotg->lx_state != DWC2_L1) {
433 u32 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 433 u32 pcgcctl = dwc2_readl(hsotg, PCGCTL);
434 434
435 /* Restart the Phy Clock */ 435 /* Restart the Phy Clock */
436 pcgcctl &= ~PCGCTL_STOPPCLK; 436 pcgcctl &= ~PCGCTL_STOPPCLK;
437 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 437 dwc2_writel(hsotg, pcgcctl, PCGCTL);
438 mod_timer(&hsotg->wkp_timer, 438 mod_timer(&hsotg->wkp_timer,
439 jiffies + msecs_to_jiffies(71)); 439 jiffies + msecs_to_jiffies(71));
440 } else { 440 } else {
@@ -450,7 +450,7 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
450 */ 450 */
451static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg) 451static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg)
452{ 452{
453 dwc2_writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS); 453 dwc2_writel(hsotg, GINTSTS_DISCONNINT, GINTSTS);
454 454
455 dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n", 455 dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n",
456 dwc2_is_host_mode(hsotg) ? "Host" : "Device", 456 dwc2_is_host_mode(hsotg) ? "Host" : "Device",
@@ -474,7 +474,7 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
474 int ret; 474 int ret;
475 475
476 /* Clear interrupt */ 476 /* Clear interrupt */
477 dwc2_writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS); 477 dwc2_writel(hsotg, GINTSTS_USBSUSP, GINTSTS);
478 478
479 dev_dbg(hsotg->dev, "USB SUSPEND\n"); 479 dev_dbg(hsotg->dev, "USB SUSPEND\n");
480 480
@@ -483,7 +483,7 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
483 * Check the Device status register to determine if the Suspend 483 * Check the Device status register to determine if the Suspend
484 * state is active 484 * state is active
485 */ 485 */
486 dsts = dwc2_readl(hsotg->regs + DSTS); 486 dsts = dwc2_readl(hsotg, DSTS);
487 dev_dbg(hsotg->dev, "%s: DSTS=0x%0x\n", __func__, dsts); 487 dev_dbg(hsotg->dev, "%s: DSTS=0x%0x\n", __func__, dsts);
488 dev_dbg(hsotg->dev, 488 dev_dbg(hsotg->dev,
489 "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d HWCFG4.Hibernation=%d\n", 489 "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d HWCFG4.Hibernation=%d\n",
@@ -563,9 +563,9 @@ static void dwc2_handle_lpm_intr(struct dwc2_hsotg *hsotg)
563 u32 enslpm; 563 u32 enslpm;
564 564
565 /* Clear interrupt */ 565 /* Clear interrupt */
566 dwc2_writel(GINTSTS_LPMTRANRCVD, hsotg->regs + GINTSTS); 566 dwc2_writel(hsotg, GINTSTS_LPMTRANRCVD, GINTSTS);
567 567
568 glpmcfg = dwc2_readl(hsotg->regs + GLPMCFG); 568 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
569 569
570 if (!(glpmcfg & GLPMCFG_LPMCAP)) { 570 if (!(glpmcfg & GLPMCFG_LPMCAP)) {
571 dev_err(hsotg->dev, "Unexpected LPM interrupt\n"); 571 dev_err(hsotg->dev, "Unexpected LPM interrupt\n");
@@ -588,16 +588,16 @@ static void dwc2_handle_lpm_intr(struct dwc2_hsotg *hsotg)
588 } else { 588 } else {
589 dev_dbg(hsotg->dev, "Entering Sleep with L1 Gating\n"); 589 dev_dbg(hsotg->dev, "Entering Sleep with L1 Gating\n");
590 590
591 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 591 pcgcctl = dwc2_readl(hsotg, PCGCTL);
592 pcgcctl |= PCGCTL_ENBL_SLEEP_GATING; 592 pcgcctl |= PCGCTL_ENBL_SLEEP_GATING;
593 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 593 dwc2_writel(hsotg, pcgcctl, PCGCTL);
594 } 594 }
595 /** 595 /**
596 * Examine prt_sleep_sts after TL1TokenTetry period max (10 us) 596 * Examine prt_sleep_sts after TL1TokenTetry period max (10 us)
597 */ 597 */
598 udelay(10); 598 udelay(10);
599 599
600 glpmcfg = dwc2_readl(hsotg->regs + GLPMCFG); 600 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
601 601
602 if (glpmcfg & GLPMCFG_SLPSTS) { 602 if (glpmcfg & GLPMCFG_SLPSTS) {
603 /* Save the current state */ 603 /* Save the current state */
@@ -627,9 +627,9 @@ static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg)
627 u32 gahbcfg; 627 u32 gahbcfg;
628 u32 gintmsk_common = GINTMSK_COMMON; 628 u32 gintmsk_common = GINTMSK_COMMON;
629 629
630 gintsts = dwc2_readl(hsotg->regs + GINTSTS); 630 gintsts = dwc2_readl(hsotg, GINTSTS);
631 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 631 gintmsk = dwc2_readl(hsotg, GINTMSK);
632 gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 632 gahbcfg = dwc2_readl(hsotg, GAHBCFG);
633 633
634 /* If any common interrupts set */ 634 /* If any common interrupts set */
635 if (gintsts & gintmsk_common) 635 if (gintsts & gintmsk_common)
@@ -653,9 +653,9 @@ static void dwc2_handle_gpwrdn_intr(struct dwc2_hsotg *hsotg)
653 u32 gpwrdn; 653 u32 gpwrdn;
654 int linestate; 654 int linestate;
655 655
656 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 656 gpwrdn = dwc2_readl(hsotg, GPWRDN);
657 /* clear all interrupt */ 657 /* clear all interrupt */
658 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 658 dwc2_writel(hsotg, gpwrdn, GPWRDN);
659 linestate = (gpwrdn & GPWRDN_LINESTATE_MASK) >> GPWRDN_LINESTATE_SHIFT; 659 linestate = (gpwrdn & GPWRDN_LINESTATE_MASK) >> GPWRDN_LINESTATE_SHIFT;
660 dev_dbg(hsotg->dev, 660 dev_dbg(hsotg->dev,
661 "%s: dwc2_handle_gpwrdwn_intr called gpwrdn= %08x\n", __func__, 661 "%s: dwc2_handle_gpwrdwn_intr called gpwrdn= %08x\n", __func__,
@@ -668,38 +668,38 @@ static void dwc2_handle_gpwrdn_intr(struct dwc2_hsotg *hsotg)
668 dev_dbg(hsotg->dev, "%s: GPWRDN_DISCONN_DET\n", __func__); 668 dev_dbg(hsotg->dev, "%s: GPWRDN_DISCONN_DET\n", __func__);
669 669
670 /* Switch-on voltage to the core */ 670 /* Switch-on voltage to the core */
671 gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN); 671 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
672 gpwrdn_tmp &= ~GPWRDN_PWRDNSWTCH; 672 gpwrdn_tmp &= ~GPWRDN_PWRDNSWTCH;
673 dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN); 673 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
674 udelay(10); 674 udelay(10);
675 675
676 /* Reset core */ 676 /* Reset core */
677 gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN); 677 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
678 gpwrdn_tmp &= ~GPWRDN_PWRDNRSTN; 678 gpwrdn_tmp &= ~GPWRDN_PWRDNRSTN;
679 dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN); 679 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
680 udelay(10); 680 udelay(10);
681 681
682 /* Disable Power Down Clamp */ 682 /* Disable Power Down Clamp */
683 gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN); 683 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
684 gpwrdn_tmp &= ~GPWRDN_PWRDNCLMP; 684 gpwrdn_tmp &= ~GPWRDN_PWRDNCLMP;
685 dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN); 685 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
686 udelay(10); 686 udelay(10);
687 687
688 /* Deassert reset core */ 688 /* Deassert reset core */
689 gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN); 689 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
690 gpwrdn_tmp |= GPWRDN_PWRDNRSTN; 690 gpwrdn_tmp |= GPWRDN_PWRDNRSTN;
691 dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN); 691 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
692 udelay(10); 692 udelay(10);
693 693
694 /* Disable PMU interrupt */ 694 /* Disable PMU interrupt */
695 gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN); 695 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
696 gpwrdn_tmp &= ~GPWRDN_PMUINTSEL; 696 gpwrdn_tmp &= ~GPWRDN_PMUINTSEL;
697 dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN); 697 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
698 698
699 /* De-assert Wakeup Logic */ 699 /* De-assert Wakeup Logic */
700 gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN); 700 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
701 gpwrdn_tmp &= ~GPWRDN_PMUACTV; 701 gpwrdn_tmp &= ~GPWRDN_PMUACTV;
702 dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN); 702 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
703 703
704 hsotg->hibernated = 0; 704 hsotg->hibernated = 0;
705 705
@@ -780,10 +780,10 @@ irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
780 780
781 /* Reading current frame number value in device or host modes. */ 781 /* Reading current frame number value in device or host modes. */
782 if (dwc2_is_device_mode(hsotg)) 782 if (dwc2_is_device_mode(hsotg))
783 hsotg->frame_number = (dwc2_readl(hsotg->regs + DSTS) 783 hsotg->frame_number = (dwc2_readl(hsotg, DSTS)
784 & DSTS_SOFFN_MASK) >> DSTS_SOFFN_SHIFT; 784 & DSTS_SOFFN_MASK) >> DSTS_SOFFN_SHIFT;
785 else 785 else
786 hsotg->frame_number = (dwc2_readl(hsotg->regs + HFNUM) 786 hsotg->frame_number = (dwc2_readl(hsotg, HFNUM)
787 & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 787 & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
788 788
789 gintsts = dwc2_read_common_intr(hsotg); 789 gintsts = dwc2_read_common_intr(hsotg);
diff --git a/drivers/usb/dwc2/debugfs.c b/drivers/usb/dwc2/debugfs.c
index d0bdb7997557..22d015b0424f 100644
--- a/drivers/usb/dwc2/debugfs.c
+++ b/drivers/usb/dwc2/debugfs.c
@@ -69,7 +69,7 @@ static int testmode_show(struct seq_file *s, void *unused)
69 int dctl; 69 int dctl;
70 70
71 spin_lock_irqsave(&hsotg->lock, flags); 71 spin_lock_irqsave(&hsotg->lock, flags);
72 dctl = dwc2_readl(hsotg->regs + DCTL); 72 dctl = dwc2_readl(hsotg, DCTL);
73 dctl &= DCTL_TSTCTL_MASK; 73 dctl &= DCTL_TSTCTL_MASK;
74 dctl >>= DCTL_TSTCTL_SHIFT; 74 dctl >>= DCTL_TSTCTL_SHIFT;
75 spin_unlock_irqrestore(&hsotg->lock, flags); 75 spin_unlock_irqrestore(&hsotg->lock, flags);
@@ -126,42 +126,41 @@ static const struct file_operations testmode_fops = {
126static int state_show(struct seq_file *seq, void *v) 126static int state_show(struct seq_file *seq, void *v)
127{ 127{
128 struct dwc2_hsotg *hsotg = seq->private; 128 struct dwc2_hsotg *hsotg = seq->private;
129 void __iomem *regs = hsotg->regs;
130 int idx; 129 int idx;
131 130
132 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n", 131 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
133 dwc2_readl(regs + DCFG), 132 dwc2_readl(hsotg, DCFG),
134 dwc2_readl(regs + DCTL), 133 dwc2_readl(hsotg, DCTL),
135 dwc2_readl(regs + DSTS)); 134 dwc2_readl(hsotg, DSTS));
136 135
137 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n", 136 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
138 dwc2_readl(regs + DIEPMSK), dwc2_readl(regs + DOEPMSK)); 137 dwc2_readl(hsotg, DIEPMSK), dwc2_readl(hsotg, DOEPMSK));
139 138
140 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n", 139 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
141 dwc2_readl(regs + GINTMSK), 140 dwc2_readl(hsotg, GINTMSK),
142 dwc2_readl(regs + GINTSTS)); 141 dwc2_readl(hsotg, GINTSTS));
143 142
144 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n", 143 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
145 dwc2_readl(regs + DAINTMSK), 144 dwc2_readl(hsotg, DAINTMSK),
146 dwc2_readl(regs + DAINT)); 145 dwc2_readl(hsotg, DAINT));
147 146
148 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n", 147 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
149 dwc2_readl(regs + GNPTXSTS), 148 dwc2_readl(hsotg, GNPTXSTS),
150 dwc2_readl(regs + GRXSTSR)); 149 dwc2_readl(hsotg, GRXSTSR));
151 150
152 seq_puts(seq, "\nEndpoint status:\n"); 151 seq_puts(seq, "\nEndpoint status:\n");
153 152
154 for (idx = 0; idx < hsotg->num_of_eps; idx++) { 153 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
155 u32 in, out; 154 u32 in, out;
156 155
157 in = dwc2_readl(regs + DIEPCTL(idx)); 156 in = dwc2_readl(hsotg, DIEPCTL(idx));
158 out = dwc2_readl(regs + DOEPCTL(idx)); 157 out = dwc2_readl(hsotg, DOEPCTL(idx));
159 158
160 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x", 159 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
161 idx, in, out); 160 idx, in, out);
162 161
163 in = dwc2_readl(regs + DIEPTSIZ(idx)); 162 in = dwc2_readl(hsotg, DIEPTSIZ(idx));
164 out = dwc2_readl(regs + DOEPTSIZ(idx)); 163 out = dwc2_readl(hsotg, DOEPTSIZ(idx));
165 164
166 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x", 165 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
167 in, out); 166 in, out);
@@ -184,14 +183,13 @@ DEFINE_SHOW_ATTRIBUTE(state);
184static int fifo_show(struct seq_file *seq, void *v) 183static int fifo_show(struct seq_file *seq, void *v)
185{ 184{
186 struct dwc2_hsotg *hsotg = seq->private; 185 struct dwc2_hsotg *hsotg = seq->private;
187 void __iomem *regs = hsotg->regs;
188 u32 val; 186 u32 val;
189 int idx; 187 int idx;
190 188
191 seq_puts(seq, "Non-periodic FIFOs:\n"); 189 seq_puts(seq, "Non-periodic FIFOs:\n");
192 seq_printf(seq, "RXFIFO: Size %d\n", dwc2_readl(regs + GRXFSIZ)); 190 seq_printf(seq, "RXFIFO: Size %d\n", dwc2_readl(hsotg, GRXFSIZ));
193 191
194 val = dwc2_readl(regs + GNPTXFSIZ); 192 val = dwc2_readl(hsotg, GNPTXFSIZ);
195 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n", 193 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
196 val >> FIFOSIZE_DEPTH_SHIFT, 194 val >> FIFOSIZE_DEPTH_SHIFT,
197 val & FIFOSIZE_STARTADDR_MASK); 195 val & FIFOSIZE_STARTADDR_MASK);
@@ -199,7 +197,7 @@ static int fifo_show(struct seq_file *seq, void *v)
199 seq_puts(seq, "\nPeriodic TXFIFOs:\n"); 197 seq_puts(seq, "\nPeriodic TXFIFOs:\n");
200 198
201 for (idx = 1; idx < hsotg->num_of_eps; idx++) { 199 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
202 val = dwc2_readl(regs + DPTXFSIZN(idx)); 200 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
203 201
204 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx, 202 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
205 val >> FIFOSIZE_DEPTH_SHIFT, 203 val >> FIFOSIZE_DEPTH_SHIFT,
@@ -228,7 +226,6 @@ static int ep_show(struct seq_file *seq, void *v)
228 struct dwc2_hsotg_ep *ep = seq->private; 226 struct dwc2_hsotg_ep *ep = seq->private;
229 struct dwc2_hsotg *hsotg = ep->parent; 227 struct dwc2_hsotg *hsotg = ep->parent;
230 struct dwc2_hsotg_req *req; 228 struct dwc2_hsotg_req *req;
231 void __iomem *regs = hsotg->regs;
232 int index = ep->index; 229 int index = ep->index;
233 int show_limit = 15; 230 int show_limit = 15;
234 unsigned long flags; 231 unsigned long flags;
@@ -239,20 +236,20 @@ static int ep_show(struct seq_file *seq, void *v)
239 /* first show the register state */ 236 /* first show the register state */
240 237
241 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n", 238 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
242 dwc2_readl(regs + DIEPCTL(index)), 239 dwc2_readl(hsotg, DIEPCTL(index)),
243 dwc2_readl(regs + DOEPCTL(index))); 240 dwc2_readl(hsotg, DOEPCTL(index)));
244 241
245 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n", 242 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
246 dwc2_readl(regs + DIEPDMA(index)), 243 dwc2_readl(hsotg, DIEPDMA(index)),
247 dwc2_readl(regs + DOEPDMA(index))); 244 dwc2_readl(hsotg, DOEPDMA(index)));
248 245
249 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n", 246 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
250 dwc2_readl(regs + DIEPINT(index)), 247 dwc2_readl(hsotg, DIEPINT(index)),
251 dwc2_readl(regs + DOEPINT(index))); 248 dwc2_readl(hsotg, DOEPINT(index)));
252 249
253 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n", 250 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
254 dwc2_readl(regs + DIEPTSIZ(index)), 251 dwc2_readl(hsotg, DIEPTSIZ(index)),
255 dwc2_readl(regs + DOEPTSIZ(index))); 252 dwc2_readl(hsotg, DOEPTSIZ(index)));
256 253
257 seq_puts(seq, "\n"); 254 seq_puts(seq, "\n");
258 seq_printf(seq, "mps %d\n", ep->ep.maxpacket); 255 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
index cefc99ae69b2..220c0f9b89b0 100644
--- a/drivers/usb/dwc2/gadget.c
+++ b/drivers/usb/dwc2/gadget.c
@@ -47,14 +47,14 @@ static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
47 return container_of(gadget, struct dwc2_hsotg, gadget); 47 return container_of(gadget, struct dwc2_hsotg, gadget);
48} 48}
49 49
50static inline void dwc2_set_bit(void __iomem *ptr, u32 val) 50static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
51{ 51{
52 dwc2_writel(dwc2_readl(ptr) | val, ptr); 52 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
53} 53}
54 54
55static inline void dwc2_clear_bit(void __iomem *ptr, u32 val) 55static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
56{ 56{
57 dwc2_writel(dwc2_readl(ptr) & ~val, ptr); 57 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
58} 58}
59 59
60static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, 60static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
@@ -129,14 +129,14 @@ static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
129 */ 129 */
130static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) 130static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
131{ 131{
132 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); 132 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
133 u32 new_gsintmsk; 133 u32 new_gsintmsk;
134 134
135 new_gsintmsk = gsintmsk | ints; 135 new_gsintmsk = gsintmsk | ints;
136 136
137 if (new_gsintmsk != gsintmsk) { 137 if (new_gsintmsk != gsintmsk) {
138 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); 138 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
139 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); 139 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
140 } 140 }
141} 141}
142 142
@@ -147,13 +147,13 @@ static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
147 */ 147 */
148static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) 148static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
149{ 149{
150 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); 150 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
151 u32 new_gsintmsk; 151 u32 new_gsintmsk;
152 152
153 new_gsintmsk = gsintmsk & ~ints; 153 new_gsintmsk = gsintmsk & ~ints;
154 154
155 if (new_gsintmsk != gsintmsk) 155 if (new_gsintmsk != gsintmsk)
156 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); 156 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
157} 157}
158 158
159/** 159/**
@@ -178,12 +178,12 @@ static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
178 bit <<= 16; 178 bit <<= 16;
179 179
180 local_irq_save(flags); 180 local_irq_save(flags);
181 daint = dwc2_readl(hsotg->regs + DAINTMSK); 181 daint = dwc2_readl(hsotg, DAINTMSK);
182 if (en) 182 if (en)
183 daint |= bit; 183 daint |= bit;
184 else 184 else
185 daint &= ~bit; 185 daint &= ~bit;
186 dwc2_writel(daint, hsotg->regs + DAINTMSK); 186 dwc2_writel(hsotg, daint, DAINTMSK);
187 local_irq_restore(flags); 187 local_irq_restore(flags);
188} 188}
189 189
@@ -266,10 +266,11 @@ static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
266 hsotg->fifo_map = 0; 266 hsotg->fifo_map = 0;
267 267
268 /* set RX/NPTX FIFO sizes */ 268 /* set RX/NPTX FIFO sizes */
269 dwc2_writel(hsotg->params.g_rx_fifo_size, hsotg->regs + GRXFSIZ); 269 dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
270 dwc2_writel((hsotg->params.g_rx_fifo_size << FIFOSIZE_STARTADDR_SHIFT) | 270 dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
271 FIFOSIZE_STARTADDR_SHIFT) |
271 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT), 272 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
272 hsotg->regs + GNPTXFSIZ); 273 GNPTXFSIZ);
273 274
274 /* 275 /*
275 * arange all the rest of the TX FIFOs, as some versions of this 276 * arange all the rest of the TX FIFOs, as some versions of this
@@ -295,25 +296,25 @@ static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
295 "insufficient fifo memory"); 296 "insufficient fifo memory");
296 addr += txfsz[ep]; 297 addr += txfsz[ep];
297 298
298 dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep)); 299 dwc2_writel(hsotg, val, DPTXFSIZN(ep));
299 val = dwc2_readl(hsotg->regs + DPTXFSIZN(ep)); 300 val = dwc2_readl(hsotg, DPTXFSIZN(ep));
300 } 301 }
301 302
302 dwc2_writel(hsotg->hw_params.total_fifo_size | 303 dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
303 addr << GDFIFOCFG_EPINFOBASE_SHIFT, 304 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
304 hsotg->regs + GDFIFOCFG); 305 GDFIFOCFG);
305 /* 306 /*
306 * according to p428 of the design guide, we need to ensure that 307 * according to p428 of the design guide, we need to ensure that
307 * all fifos are flushed before continuing 308 * all fifos are flushed before continuing
308 */ 309 */
309 310
310 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | 311 dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
311 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); 312 GRSTCTL_RXFFLSH, GRSTCTL);
312 313
313 /* wait until the fifos are both flushed */ 314 /* wait until the fifos are both flushed */
314 timeout = 100; 315 timeout = 100;
315 while (1) { 316 while (1) {
316 val = dwc2_readl(hsotg->regs + GRSTCTL); 317 val = dwc2_readl(hsotg, GRSTCTL);
317 318
318 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) 319 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
319 break; 320 break;
@@ -451,7 +452,7 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
451 struct dwc2_hsotg_req *hs_req) 452 struct dwc2_hsotg_req *hs_req)
452{ 453{
453 bool periodic = is_ep_periodic(hs_ep); 454 bool periodic = is_ep_periodic(hs_ep);
454 u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); 455 u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
455 int buf_pos = hs_req->req.actual; 456 int buf_pos = hs_req->req.actual;
456 int to_write = hs_ep->size_loaded; 457 int to_write = hs_ep->size_loaded;
457 void *data; 458 void *data;
@@ -466,7 +467,7 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
466 return 0; 467 return 0;
467 468
468 if (periodic && !hsotg->dedicated_fifos) { 469 if (periodic && !hsotg->dedicated_fifos) {
469 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); 470 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
470 int size_left; 471 int size_left;
471 int size_done; 472 int size_done;
472 473
@@ -507,8 +508,8 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
507 return -ENOSPC; 508 return -ENOSPC;
508 } 509 }
509 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { 510 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
510 can_write = dwc2_readl(hsotg->regs + 511 can_write = dwc2_readl(hsotg,
511 DTXFSTS(hs_ep->fifo_index)); 512 DTXFSTS(hs_ep->fifo_index));
512 513
513 can_write &= 0xffff; 514 can_write &= 0xffff;
514 can_write *= 4; 515 can_write *= 4;
@@ -598,7 +599,7 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
598 to_write = DIV_ROUND_UP(to_write, 4); 599 to_write = DIV_ROUND_UP(to_write, 4);
599 data = hs_req->req.buf + buf_pos; 600 data = hs_req->req.buf + buf_pos;
600 601
601 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write); 602 dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
602 603
603 return (to_write >= can_write) ? -ENOSPC : 0; 604 return (to_write >= can_write) ? -ENOSPC : 0;
604} 605}
@@ -652,7 +653,7 @@ static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
652{ 653{
653 u32 dsts; 654 u32 dsts;
654 655
655 dsts = dwc2_readl(hsotg->regs + DSTS); 656 dsts = dwc2_readl(hsotg, DSTS);
656 dsts &= DSTS_SOFFN_MASK; 657 dsts &= DSTS_SOFFN_MASK;
657 dsts >>= DSTS_SOFFN_SHIFT; 658 dsts >>= DSTS_SOFFN_SHIFT;
658 659
@@ -915,11 +916,11 @@ static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
915 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index); 916 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
916 917
917 /* write descriptor chain address to control register */ 918 /* write descriptor chain address to control register */
918 dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg); 919 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
919 920
920 ctrl = dwc2_readl(hsotg->regs + depctl); 921 ctrl = dwc2_readl(hsotg, depctl);
921 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK; 922 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
922 dwc2_writel(ctrl, hsotg->regs + depctl); 923 dwc2_writel(hsotg, ctrl, depctl);
923} 924}
924 925
925/** 926/**
@@ -967,11 +968,11 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
967 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); 968 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
968 969
969 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", 970 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
970 __func__, dwc2_readl(hsotg->regs + epctrl_reg), index, 971 __func__, dwc2_readl(hsotg, epctrl_reg), index,
971 hs_ep->dir_in ? "in" : "out"); 972 hs_ep->dir_in ? "in" : "out");
972 973
973 /* If endpoint is stalled, we will restart request later */ 974 /* If endpoint is stalled, we will restart request later */
974 ctrl = dwc2_readl(hsotg->regs + epctrl_reg); 975 ctrl = dwc2_readl(hsotg, epctrl_reg);
975 976
976 if (index && ctrl & DXEPCTL_STALL) { 977 if (index && ctrl & DXEPCTL_STALL) {
977 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); 978 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
@@ -1064,13 +1065,13 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1064 length); 1065 length);
1065 1066
1066 /* write descriptor chain address to control register */ 1067 /* write descriptor chain address to control register */
1067 dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg); 1068 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1068 1069
1069 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n", 1070 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1070 __func__, (u32)hs_ep->desc_list_dma, dma_reg); 1071 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1071 } else { 1072 } else {
1072 /* write size / packets */ 1073 /* write size / packets */
1073 dwc2_writel(epsize, hsotg->regs + epsize_reg); 1074 dwc2_writel(hsotg, epsize, epsize_reg);
1074 1075
1075 if (using_dma(hsotg) && !continuing && (length != 0)) { 1076 if (using_dma(hsotg) && !continuing && (length != 0)) {
1076 /* 1077 /*
@@ -1078,7 +1079,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1078 * already synced by dwc2_hsotg_ep_queue(). 1079 * already synced by dwc2_hsotg_ep_queue().
1079 */ 1080 */
1080 1081
1081 dwc2_writel(ureq->dma, hsotg->regs + dma_reg); 1082 dwc2_writel(hsotg, ureq->dma, dma_reg);
1082 1083
1083 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", 1084 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1084 __func__, &ureq->dma, dma_reg); 1085 __func__, &ureq->dma, dma_reg);
@@ -1104,7 +1105,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1104 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ 1105 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1105 1106
1106 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); 1107 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1107 dwc2_writel(ctrl, hsotg->regs + epctrl_reg); 1108 dwc2_writel(hsotg, ctrl, epctrl_reg);
1108 1109
1109 /* 1110 /*
1110 * set these, it seems that DMA support increments past the end 1111 * set these, it seems that DMA support increments past the end
@@ -1127,13 +1128,13 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1127 */ 1128 */
1128 1129
1129 /* check ep is enabled */ 1130 /* check ep is enabled */
1130 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) 1131 if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
1131 dev_dbg(hsotg->dev, 1132 dev_dbg(hsotg->dev,
1132 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", 1133 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1133 index, dwc2_readl(hsotg->regs + epctrl_reg)); 1134 index, dwc2_readl(hsotg, epctrl_reg));
1134 1135
1135 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", 1136 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1136 __func__, dwc2_readl(hsotg->regs + epctrl_reg)); 1137 __func__, dwc2_readl(hsotg, epctrl_reg));
1137 1138
1138 /* enable ep interrupts */ 1139 /* enable ep interrupts */
1139 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); 1140 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
@@ -1466,7 +1467,7 @@ static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1466 */ 1467 */
1467int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) 1468int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1468{ 1469{
1469 int dctl = dwc2_readl(hsotg->regs + DCTL); 1470 int dctl = dwc2_readl(hsotg, DCTL);
1470 1471
1471 dctl &= ~DCTL_TSTCTL_MASK; 1472 dctl &= ~DCTL_TSTCTL_MASK;
1472 switch (testmode) { 1473 switch (testmode) {
@@ -1480,7 +1481,7 @@ int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1480 default: 1481 default:
1481 return -EINVAL; 1482 return -EINVAL;
1482 } 1483 }
1483 dwc2_writel(dctl, hsotg->regs + DCTL); 1484 dwc2_writel(hsotg, dctl, DCTL);
1484 return 0; 1485 return 0;
1485} 1486}
1486 1487
@@ -1634,9 +1635,9 @@ static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1634 } else { 1635 } else {
1635 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n", 1636 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1636 __func__); 1637 __func__);
1637 mask = dwc2_readl(hsotg->regs + epmsk_reg); 1638 mask = dwc2_readl(hsotg, epmsk_reg);
1638 mask |= DOEPMSK_OUTTKNEPDISMSK; 1639 mask |= DOEPMSK_OUTTKNEPDISMSK;
1639 dwc2_writel(mask, hsotg->regs + epmsk_reg); 1640 dwc2_writel(hsotg, mask, epmsk_reg);
1640 } 1641 }
1641} 1642}
1642 1643
@@ -1773,14 +1774,14 @@ static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1773 * taken effect, so no need to clear later. 1774 * taken effect, so no need to clear later.
1774 */ 1775 */
1775 1776
1776 ctrl = dwc2_readl(hsotg->regs + reg); 1777 ctrl = dwc2_readl(hsotg, reg);
1777 ctrl |= DXEPCTL_STALL; 1778 ctrl |= DXEPCTL_STALL;
1778 ctrl |= DXEPCTL_CNAK; 1779 ctrl |= DXEPCTL_CNAK;
1779 dwc2_writel(ctrl, hsotg->regs + reg); 1780 dwc2_writel(hsotg, ctrl, reg);
1780 1781
1781 dev_dbg(hsotg->dev, 1782 dev_dbg(hsotg->dev,
1782 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", 1783 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1783 ctrl, reg, dwc2_readl(hsotg->regs + reg)); 1784 ctrl, reg, dwc2_readl(hsotg, reg));
1784 1785
1785 /* 1786 /*
1786 * complete won't be called, so we enqueue 1787 * complete won't be called, so we enqueue
@@ -1825,11 +1826,11 @@ static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1825 switch (ctrl->bRequest) { 1826 switch (ctrl->bRequest) {
1826 case USB_REQ_SET_ADDRESS: 1827 case USB_REQ_SET_ADDRESS:
1827 hsotg->connected = 1; 1828 hsotg->connected = 1;
1828 dcfg = dwc2_readl(hsotg->regs + DCFG); 1829 dcfg = dwc2_readl(hsotg, DCFG);
1829 dcfg &= ~DCFG_DEVADDR_MASK; 1830 dcfg &= ~DCFG_DEVADDR_MASK;
1830 dcfg |= (le16_to_cpu(ctrl->wValue) << 1831 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1831 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; 1832 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1832 dwc2_writel(dcfg, hsotg->regs + DCFG); 1833 dwc2_writel(hsotg, dcfg, DCFG);
1833 1834
1834 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); 1835 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1835 1836
@@ -1955,16 +1956,16 @@ static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1955 1956
1956 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0); 1957 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
1957 } else { 1958 } else {
1958 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | 1959 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1959 DXEPTSIZ_XFERSIZE(0), hsotg->regs + 1960 DXEPTSIZ_XFERSIZE(0),
1960 epsiz_reg); 1961 epsiz_reg);
1961 } 1962 }
1962 1963
1963 ctrl = dwc2_readl(hsotg->regs + epctl_reg); 1964 ctrl = dwc2_readl(hsotg, epctl_reg);
1964 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ 1965 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1965 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ 1966 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1966 ctrl |= DXEPCTL_USBACTEP; 1967 ctrl |= DXEPCTL_USBACTEP;
1967 dwc2_writel(ctrl, hsotg->regs + epctl_reg); 1968 dwc2_writel(hsotg, ctrl, epctl_reg);
1968} 1969}
1969 1970
1970/** 1971/**
@@ -2124,13 +2125,12 @@ static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2124{ 2125{
2125 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; 2126 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2126 struct dwc2_hsotg_req *hs_req = hs_ep->req; 2127 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2127 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
2128 int to_read; 2128 int to_read;
2129 int max_req; 2129 int max_req;
2130 int read_ptr; 2130 int read_ptr;
2131 2131
2132 if (!hs_req) { 2132 if (!hs_req) {
2133 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx)); 2133 u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
2134 int ptr; 2134 int ptr;
2135 2135
2136 dev_dbg(hsotg->dev, 2136 dev_dbg(hsotg->dev,
@@ -2139,7 +2139,7 @@ static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2139 2139
2140 /* dump the data from the FIFO, we've nothing we can do */ 2140 /* dump the data from the FIFO, we've nothing we can do */
2141 for (ptr = 0; ptr < size; ptr += 4) 2141 for (ptr = 0; ptr < size; ptr += 4)
2142 (void)dwc2_readl(fifo); 2142 (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
2143 2143
2144 return; 2144 return;
2145 } 2145 }
@@ -2169,7 +2169,8 @@ static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2169 * note, we might over-write the buffer end by 3 bytes depending on 2169 * note, we might over-write the buffer end by 3 bytes depending on
2170 * alignment of the data. 2170 * alignment of the data.
2171 */ 2171 */
2172 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read); 2172 dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
2173 hs_req->req.buf + read_ptr, to_read);
2173} 2174}
2174 2175
2175/** 2176/**
@@ -2198,12 +2199,12 @@ static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
2198{ 2199{
2199 u32 ctrl; 2200 u32 ctrl;
2200 2201
2201 ctrl = dwc2_readl(hsotg->regs + epctl_reg); 2202 ctrl = dwc2_readl(hsotg, epctl_reg);
2202 if (ctrl & DXEPCTL_EOFRNUM) 2203 if (ctrl & DXEPCTL_EOFRNUM)
2203 ctrl |= DXEPCTL_SETEVENFR; 2204 ctrl |= DXEPCTL_SETEVENFR;
2204 else 2205 else
2205 ctrl |= DXEPCTL_SETODDFR; 2206 ctrl |= DXEPCTL_SETODDFR;
2206 dwc2_writel(ctrl, hsotg->regs + epctl_reg); 2207 dwc2_writel(hsotg, ctrl, epctl_reg);
2207} 2208}
2208 2209
2209/* 2210/*
@@ -2247,7 +2248,7 @@ static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2247 */ 2248 */
2248static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) 2249static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2249{ 2250{
2250 u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum)); 2251 u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
2251 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; 2252 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2252 struct dwc2_hsotg_req *hs_req = hs_ep->req; 2253 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2253 struct usb_request *req = &hs_req->req; 2254 struct usb_request *req = &hs_req->req;
@@ -2343,7 +2344,7 @@ static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2343 */ 2344 */
2344static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) 2345static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2345{ 2346{
2346 u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP); 2347 u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
2347 u32 epnum, status, size; 2348 u32 epnum, status, size;
2348 2349
2349 WARN_ON(using_dma(hsotg)); 2350 WARN_ON(using_dma(hsotg));
@@ -2374,7 +2375,7 @@ static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2374 dev_dbg(hsotg->dev, 2375 dev_dbg(hsotg->dev,
2375 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", 2376 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2376 dwc2_hsotg_read_frameno(hsotg), 2377 dwc2_hsotg_read_frameno(hsotg),
2377 dwc2_readl(hsotg->regs + DOEPCTL(0))); 2378 dwc2_readl(hsotg, DOEPCTL(0)));
2378 /* 2379 /*
2379 * Call dwc2_hsotg_handle_outdone here if it was not called from 2380 * Call dwc2_hsotg_handle_outdone here if it was not called from
2380 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't 2381 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
@@ -2392,7 +2393,7 @@ static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2392 dev_dbg(hsotg->dev, 2393 dev_dbg(hsotg->dev,
2393 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", 2394 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2394 dwc2_hsotg_read_frameno(hsotg), 2395 dwc2_hsotg_read_frameno(hsotg),
2395 dwc2_readl(hsotg->regs + DOEPCTL(0))); 2396 dwc2_readl(hsotg, DOEPCTL(0)));
2396 2397
2397 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); 2398 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2398 2399
@@ -2446,7 +2447,6 @@ static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2446 unsigned int mc, unsigned int dir_in) 2447 unsigned int mc, unsigned int dir_in)
2447{ 2448{
2448 struct dwc2_hsotg_ep *hs_ep; 2449 struct dwc2_hsotg_ep *hs_ep;
2449 void __iomem *regs = hsotg->regs;
2450 u32 reg; 2450 u32 reg;
2451 2451
2452 hs_ep = index_to_ep(hsotg, ep, dir_in); 2452 hs_ep = index_to_ep(hsotg, ep, dir_in);
@@ -2472,15 +2472,15 @@ static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2472 } 2472 }
2473 2473
2474 if (dir_in) { 2474 if (dir_in) {
2475 reg = dwc2_readl(regs + DIEPCTL(ep)); 2475 reg = dwc2_readl(hsotg, DIEPCTL(ep));
2476 reg &= ~DXEPCTL_MPS_MASK; 2476 reg &= ~DXEPCTL_MPS_MASK;
2477 reg |= mps; 2477 reg |= mps;
2478 dwc2_writel(reg, regs + DIEPCTL(ep)); 2478 dwc2_writel(hsotg, reg, DIEPCTL(ep));
2479 } else { 2479 } else {
2480 reg = dwc2_readl(regs + DOEPCTL(ep)); 2480 reg = dwc2_readl(hsotg, DOEPCTL(ep));
2481 reg &= ~DXEPCTL_MPS_MASK; 2481 reg &= ~DXEPCTL_MPS_MASK;
2482 reg |= mps; 2482 reg |= mps;
2483 dwc2_writel(reg, regs + DOEPCTL(ep)); 2483 dwc2_writel(hsotg, reg, DOEPCTL(ep));
2484 } 2484 }
2485 2485
2486 return; 2486 return;
@@ -2496,8 +2496,8 @@ bad_mps:
2496 */ 2496 */
2497static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) 2497static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2498{ 2498{
2499 dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, 2499 dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2500 hsotg->regs + GRSTCTL); 2500 GRSTCTL);
2501 2501
2502 /* wait until the fifo is flushed */ 2502 /* wait until the fifo is flushed */
2503 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100)) 2503 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
@@ -2550,7 +2550,7 @@ static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2550 struct dwc2_hsotg_ep *hs_ep) 2550 struct dwc2_hsotg_ep *hs_ep)
2551{ 2551{
2552 struct dwc2_hsotg_req *hs_req = hs_ep->req; 2552 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2553 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); 2553 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
2554 int size_left, size_done; 2554 int size_left, size_done;
2555 2555
2556 if (!hs_req) { 2556 if (!hs_req) {
@@ -2654,12 +2654,12 @@ static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2654 u32 mask; 2654 u32 mask;
2655 u32 diepempmsk; 2655 u32 diepempmsk;
2656 2656
2657 mask = dwc2_readl(hsotg->regs + epmsk_reg); 2657 mask = dwc2_readl(hsotg, epmsk_reg);
2658 diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK); 2658 diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
2659 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0; 2659 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2660 mask |= DXEPINT_SETUP_RCVD; 2660 mask |= DXEPINT_SETUP_RCVD;
2661 2661
2662 ints = dwc2_readl(hsotg->regs + epint_reg); 2662 ints = dwc2_readl(hsotg, epint_reg);
2663 ints &= mask; 2663 ints &= mask;
2664 return ints; 2664 return ints;
2665} 2665}
@@ -2684,12 +2684,12 @@ static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2684 unsigned char idx = hs_ep->index; 2684 unsigned char idx = hs_ep->index;
2685 int dir_in = hs_ep->dir_in; 2685 int dir_in = hs_ep->dir_in;
2686 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); 2686 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2687 int dctl = dwc2_readl(hsotg->regs + DCTL); 2687 int dctl = dwc2_readl(hsotg, DCTL);
2688 2688
2689 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); 2689 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2690 2690
2691 if (dir_in) { 2691 if (dir_in) {
2692 int epctl = dwc2_readl(hsotg->regs + epctl_reg); 2692 int epctl = dwc2_readl(hsotg, epctl_reg);
2693 2693
2694 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); 2694 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2695 2695
@@ -2699,17 +2699,17 @@ static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2699 } 2699 }
2700 2700
2701 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) { 2701 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2702 int dctl = dwc2_readl(hsotg->regs + DCTL); 2702 int dctl = dwc2_readl(hsotg, DCTL);
2703 2703
2704 dctl |= DCTL_CGNPINNAK; 2704 dctl |= DCTL_CGNPINNAK;
2705 dwc2_writel(dctl, hsotg->regs + DCTL); 2705 dwc2_writel(hsotg, dctl, DCTL);
2706 } 2706 }
2707 return; 2707 return;
2708 } 2708 }
2709 2709
2710 if (dctl & DCTL_GOUTNAKSTS) { 2710 if (dctl & DCTL_GOUTNAKSTS) {
2711 dctl |= DCTL_CGOUTNAK; 2711 dctl |= DCTL_CGOUTNAK;
2712 dwc2_writel(dctl, hsotg->regs + DCTL); 2712 dwc2_writel(hsotg, dctl, DCTL);
2713 } 2713 }
2714 2714
2715 if (!hs_ep->isochronous) 2715 if (!hs_ep->isochronous)
@@ -2750,21 +2750,14 @@ static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2750 struct dwc2_hsotg *hsotg = ep->parent; 2750 struct dwc2_hsotg *hsotg = ep->parent;
2751 int dir_in = ep->dir_in; 2751 int dir_in = ep->dir_in;
2752 u32 doepmsk; 2752 u32 doepmsk;
2753 u32 tmp;
2754 2753
2755 if (dir_in || !ep->isochronous) 2754 if (dir_in || !ep->isochronous)
2756 return; 2755 return;
2757 2756
2758 /*
2759 * Store frame in which irq was asserted here, as
2760 * it can change while completing request below.
2761 */
2762 tmp = dwc2_hsotg_read_frameno(hsotg);
2763
2764 if (using_desc_dma(hsotg)) { 2757 if (using_desc_dma(hsotg)) {
2765 if (ep->target_frame == TARGET_FRAME_INITIAL) { 2758 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2766 /* Start first ISO Out */ 2759 /* Start first ISO Out */
2767 ep->target_frame = tmp; 2760 ep->target_frame = hsotg->frame_number;
2768 dwc2_gadget_start_isoc_ddma(ep); 2761 dwc2_gadget_start_isoc_ddma(ep);
2769 } 2762 }
2770 return; 2763 return;
@@ -2772,26 +2765,24 @@ static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2772 2765
2773 if (ep->interval > 1 && 2766 if (ep->interval > 1 &&
2774 ep->target_frame == TARGET_FRAME_INITIAL) { 2767 ep->target_frame == TARGET_FRAME_INITIAL) {
2775 u32 dsts;
2776 u32 ctrl; 2768 u32 ctrl;
2777 2769
2778 dsts = dwc2_readl(hsotg->regs + DSTS); 2770 ep->target_frame = hsotg->frame_number;
2779 ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
2780 dwc2_gadget_incr_frame_num(ep); 2771 dwc2_gadget_incr_frame_num(ep);
2781 2772
2782 ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index)); 2773 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2783 if (ep->target_frame & 0x1) 2774 if (ep->target_frame & 0x1)
2784 ctrl |= DXEPCTL_SETODDFR; 2775 ctrl |= DXEPCTL_SETODDFR;
2785 else 2776 else
2786 ctrl |= DXEPCTL_SETEVENFR; 2777 ctrl |= DXEPCTL_SETEVENFR;
2787 2778
2788 dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index)); 2779 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2789 } 2780 }
2790 2781
2791 dwc2_gadget_start_next_request(ep); 2782 dwc2_gadget_start_next_request(ep);
2792 doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); 2783 doepmsk = dwc2_readl(hsotg, DOEPMSK);
2793 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK; 2784 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
2794 dwc2_writel(doepmsk, hsotg->regs + DOEPMSK); 2785 dwc2_writel(hsotg, doepmsk, DOEPMSK);
2795} 2786}
2796 2787
2797/** 2788/**
@@ -2812,31 +2803,29 @@ static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2812{ 2803{
2813 struct dwc2_hsotg *hsotg = hs_ep->parent; 2804 struct dwc2_hsotg *hsotg = hs_ep->parent;
2814 int dir_in = hs_ep->dir_in; 2805 int dir_in = hs_ep->dir_in;
2815 u32 tmp;
2816 2806
2817 if (!dir_in || !hs_ep->isochronous) 2807 if (!dir_in || !hs_ep->isochronous)
2818 return; 2808 return;
2819 2809
2820 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) { 2810 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2821 2811
2822 tmp = dwc2_hsotg_read_frameno(hsotg);
2823 if (using_desc_dma(hsotg)) { 2812 if (using_desc_dma(hsotg)) {
2824 hs_ep->target_frame = tmp; 2813 hs_ep->target_frame = hsotg->frame_number;
2825 dwc2_gadget_incr_frame_num(hs_ep); 2814 dwc2_gadget_incr_frame_num(hs_ep);
2826 dwc2_gadget_start_isoc_ddma(hs_ep); 2815 dwc2_gadget_start_isoc_ddma(hs_ep);
2827 return; 2816 return;
2828 } 2817 }
2829 2818
2830 hs_ep->target_frame = tmp; 2819 hs_ep->target_frame = hsotg->frame_number;
2831 if (hs_ep->interval > 1) { 2820 if (hs_ep->interval > 1) {
2832 u32 ctrl = dwc2_readl(hsotg->regs + 2821 u32 ctrl = dwc2_readl(hsotg,
2833 DIEPCTL(hs_ep->index)); 2822 DIEPCTL(hs_ep->index));
2834 if (hs_ep->target_frame & 0x1) 2823 if (hs_ep->target_frame & 0x1)
2835 ctrl |= DXEPCTL_SETODDFR; 2824 ctrl |= DXEPCTL_SETODDFR;
2836 else 2825 else
2837 ctrl |= DXEPCTL_SETEVENFR; 2826 ctrl |= DXEPCTL_SETEVENFR;
2838 2827
2839 dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index)); 2828 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
2840 } 2829 }
2841 2830
2842 dwc2_hsotg_complete_request(hsotg, hs_ep, 2831 dwc2_hsotg_complete_request(hsotg, hs_ep,
@@ -2866,10 +2855,10 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
2866 u32 ctrl; 2855 u32 ctrl;
2867 2856
2868 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in); 2857 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
2869 ctrl = dwc2_readl(hsotg->regs + epctl_reg); 2858 ctrl = dwc2_readl(hsotg, epctl_reg);
2870 2859
2871 /* Clear endpoint interrupts */ 2860 /* Clear endpoint interrupts */
2872 dwc2_writel(ints, hsotg->regs + epint_reg); 2861 dwc2_writel(hsotg, ints, epint_reg);
2873 2862
2874 if (!hs_ep) { 2863 if (!hs_ep) {
2875 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", 2864 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
@@ -2897,8 +2886,8 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
2897 if (ints & DXEPINT_XFERCOMPL) { 2886 if (ints & DXEPINT_XFERCOMPL) {
2898 dev_dbg(hsotg->dev, 2887 dev_dbg(hsotg->dev,
2899 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", 2888 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
2900 __func__, dwc2_readl(hsotg->regs + epctl_reg), 2889 __func__, dwc2_readl(hsotg, epctl_reg),
2901 dwc2_readl(hsotg->regs + epsiz_reg)); 2890 dwc2_readl(hsotg, epsiz_reg));
2902 2891
2903 /* In DDMA handle isochronous requests separately */ 2892 /* In DDMA handle isochronous requests separately */
2904 if (using_desc_dma(hsotg) && hs_ep->isochronous) { 2893 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
@@ -3016,7 +3005,7 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
3016 */ 3005 */
3017static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) 3006static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3018{ 3007{
3019 u32 dsts = dwc2_readl(hsotg->regs + DSTS); 3008 u32 dsts = dwc2_readl(hsotg, DSTS);
3020 int ep0_mps = 0, ep_mps = 8; 3009 int ep0_mps = 0, ep_mps = 8;
3021 3010
3022 /* 3011 /*
@@ -3087,8 +3076,8 @@ static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3087 dwc2_hsotg_enqueue_setup(hsotg); 3076 dwc2_hsotg_enqueue_setup(hsotg);
3088 3077
3089 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", 3078 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3090 dwc2_readl(hsotg->regs + DIEPCTL0), 3079 dwc2_readl(hsotg, DIEPCTL0),
3091 dwc2_readl(hsotg->regs + DOEPCTL0)); 3080 dwc2_readl(hsotg, DOEPCTL0));
3092} 3081}
3093 3082
3094/** 3083/**
@@ -3115,7 +3104,7 @@ static void kill_all_requests(struct dwc2_hsotg *hsotg,
3115 3104
3116 if (!hsotg->dedicated_fifos) 3105 if (!hsotg->dedicated_fifos)
3117 return; 3106 return;
3118 size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->fifo_index)) & 0xffff) * 4; 3107 size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3119 if (size < ep->fifo_size) 3108 if (size < ep->fifo_size)
3120 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); 3109 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3121} 3110}
@@ -3216,7 +3205,7 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3216 */ 3205 */
3217 3206
3218 /* keep other bits untouched (so e.g. forced modes are not lost) */ 3207 /* keep other bits untouched (so e.g. forced modes are not lost) */
3219 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 3208 usbcfg = dwc2_readl(hsotg, GUSBCFG);
3220 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | 3209 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
3221 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK); 3210 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
3222 3211
@@ -3231,12 +3220,12 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3231 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | 3220 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3232 (val << GUSBCFG_USBTRDTIM_SHIFT); 3221 (val << GUSBCFG_USBTRDTIM_SHIFT);
3233 } 3222 }
3234 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 3223 dwc2_writel(hsotg, usbcfg, GUSBCFG);
3235 3224
3236 dwc2_hsotg_init_fifo(hsotg); 3225 dwc2_hsotg_init_fifo(hsotg);
3237 3226
3238 if (!is_usb_reset) 3227 if (!is_usb_reset)
3239 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); 3228 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3240 3229
3241 dcfg |= DCFG_EPMISCNT(1); 3230 dcfg |= DCFG_EPMISCNT(1);
3242 3231
@@ -3257,13 +3246,13 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3257 if (hsotg->params.ipg_isoc_en) 3246 if (hsotg->params.ipg_isoc_en)
3258 dcfg |= DCFG_IPG_ISOC_SUPPORDED; 3247 dcfg |= DCFG_IPG_ISOC_SUPPORDED;
3259 3248
3260 dwc2_writel(dcfg, hsotg->regs + DCFG); 3249 dwc2_writel(hsotg, dcfg, DCFG);
3261 3250
3262 /* Clear any pending OTG interrupts */ 3251 /* Clear any pending OTG interrupts */
3263 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); 3252 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
3264 3253
3265 /* Clear any pending interrupts */ 3254 /* Clear any pending interrupts */
3266 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 3255 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
3267 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | 3256 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3268 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | 3257 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3269 GINTSTS_USBRST | GINTSTS_RESETDET | 3258 GINTSTS_USBRST | GINTSTS_RESETDET |
@@ -3277,22 +3266,22 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3277 if (!hsotg->params.external_id_pin_ctl) 3266 if (!hsotg->params.external_id_pin_ctl)
3278 intmsk |= GINTSTS_CONIDSTSCHNG; 3267 intmsk |= GINTSTS_CONIDSTSCHNG;
3279 3268
3280 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 3269 dwc2_writel(hsotg, intmsk, GINTMSK);
3281 3270
3282 if (using_dma(hsotg)) { 3271 if (using_dma(hsotg)) {
3283 dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | 3272 dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3284 hsotg->params.ahbcfg, 3273 hsotg->params.ahbcfg,
3285 hsotg->regs + GAHBCFG); 3274 GAHBCFG);
3286 3275
3287 /* Set DDMA mode support in the core if needed */ 3276 /* Set DDMA mode support in the core if needed */
3288 if (using_desc_dma(hsotg)) 3277 if (using_desc_dma(hsotg))
3289 dwc2_set_bit(hsotg->regs + DCFG, DCFG_DESCDMA_EN); 3278 dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
3290 3279
3291 } else { 3280 } else {
3292 dwc2_writel(((hsotg->dedicated_fifos) ? 3281 dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
3293 (GAHBCFG_NP_TXF_EMP_LVL | 3282 (GAHBCFG_NP_TXF_EMP_LVL |
3294 GAHBCFG_P_TXF_EMP_LVL) : 0) | 3283 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3295 GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG); 3284 GAHBCFG_GLBL_INTR_EN, GAHBCFG);
3296 } 3285 }
3297 3286
3298 /* 3287 /*
@@ -3301,33 +3290,33 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3301 * interrupts. 3290 * interrupts.
3302 */ 3291 */
3303 3292
3304 dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ? 3293 dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3305 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | 3294 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3306 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | 3295 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3307 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK, 3296 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3308 hsotg->regs + DIEPMSK); 3297 DIEPMSK);
3309 3298
3310 /* 3299 /*
3311 * don't need XferCompl, we get that from RXFIFO in slave mode. In 3300 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3312 * DMA mode we may need this and StsPhseRcvd. 3301 * DMA mode we may need this and StsPhseRcvd.
3313 */ 3302 */
3314 dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | 3303 dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3315 DOEPMSK_STSPHSERCVDMSK) : 0) | 3304 DOEPMSK_STSPHSERCVDMSK) : 0) |
3316 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | 3305 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3317 DOEPMSK_SETUPMSK, 3306 DOEPMSK_SETUPMSK,
3318 hsotg->regs + DOEPMSK); 3307 DOEPMSK);
3319 3308
3320 /* Enable BNA interrupt for DDMA */ 3309 /* Enable BNA interrupt for DDMA */
3321 if (using_desc_dma(hsotg)) { 3310 if (using_desc_dma(hsotg)) {
3322 dwc2_set_bit(hsotg->regs + DOEPMSK, DOEPMSK_BNAMSK); 3311 dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
3323 dwc2_set_bit(hsotg->regs + DIEPMSK, DIEPMSK_BNAININTRMSK); 3312 dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
3324 } 3313 }
3325 3314
3326 dwc2_writel(0, hsotg->regs + DAINTMSK); 3315 dwc2_writel(hsotg, 0, DAINTMSK);
3327 3316
3328 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", 3317 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3329 dwc2_readl(hsotg->regs + DIEPCTL0), 3318 dwc2_readl(hsotg, DIEPCTL0),
3330 dwc2_readl(hsotg->regs + DOEPCTL0)); 3319 dwc2_readl(hsotg, DOEPCTL0));
3331 3320
3332 /* enable in and out endpoint interrupts */ 3321 /* enable in and out endpoint interrupts */
3333 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); 3322 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
@@ -3345,12 +3334,12 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3345 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1); 3334 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3346 3335
3347 if (!is_usb_reset) { 3336 if (!is_usb_reset) {
3348 dwc2_set_bit(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); 3337 dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3349 udelay(10); /* see openiboot */ 3338 udelay(10); /* see openiboot */
3350 dwc2_clear_bit(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); 3339 dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3351 } 3340 }
3352 3341
3353 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL)); 3342 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
3354 3343
3355 /* 3344 /*
3356 * DxEPCTL_USBActEp says RO in manual, but seems to be set by 3345 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
@@ -3358,23 +3347,23 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3358 */ 3347 */
3359 3348
3360 /* set to read 1 8byte packet */ 3349 /* set to read 1 8byte packet */
3361 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | 3350 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3362 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); 3351 DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
3363 3352
3364 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | 3353 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3365 DXEPCTL_CNAK | DXEPCTL_EPENA | 3354 DXEPCTL_CNAK | DXEPCTL_EPENA |
3366 DXEPCTL_USBACTEP, 3355 DXEPCTL_USBACTEP,
3367 hsotg->regs + DOEPCTL0); 3356 DOEPCTL0);
3368 3357
3369 /* enable, but don't activate EP0in */ 3358 /* enable, but don't activate EP0in */
3370 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | 3359 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3371 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); 3360 DXEPCTL_USBACTEP, DIEPCTL0);
3372 3361
3373 /* clear global NAKs */ 3362 /* clear global NAKs */
3374 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; 3363 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3375 if (!is_usb_reset) 3364 if (!is_usb_reset)
3376 val |= DCTL_SFTDISCON; 3365 val |= DCTL_SFTDISCON;
3377 dwc2_set_bit(hsotg->regs + DCTL, val); 3366 dwc2_set_bit(hsotg, DCTL, val);
3378 3367
3379 /* configure the core to support LPM */ 3368 /* configure the core to support LPM */
3380 dwc2_gadget_init_lpm(hsotg); 3369 dwc2_gadget_init_lpm(hsotg);
@@ -3387,20 +3376,20 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3387 dwc2_hsotg_enqueue_setup(hsotg); 3376 dwc2_hsotg_enqueue_setup(hsotg);
3388 3377
3389 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", 3378 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3390 dwc2_readl(hsotg->regs + DIEPCTL0), 3379 dwc2_readl(hsotg, DIEPCTL0),
3391 dwc2_readl(hsotg->regs + DOEPCTL0)); 3380 dwc2_readl(hsotg, DOEPCTL0));
3392} 3381}
3393 3382
3394static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) 3383static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3395{ 3384{
3396 /* set the soft-disconnect bit */ 3385 /* set the soft-disconnect bit */
3397 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); 3386 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3398} 3387}
3399 3388
3400void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) 3389void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3401{ 3390{
3402 /* remove the soft-disconnect and let's go */ 3391 /* remove the soft-disconnect and let's go */
3403 dwc2_clear_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); 3392 dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3404} 3393}
3405 3394
3406/** 3395/**
@@ -3425,7 +3414,7 @@ static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3425 3414
3426 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n"); 3415 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3427 3416
3428 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); 3417 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3429 3418
3430 for (idx = 1; idx < hsotg->num_of_eps; idx++) { 3419 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3431 hs_ep = hsotg->eps_in[idx]; 3420 hs_ep = hsotg->eps_in[idx];
@@ -3433,17 +3422,17 @@ static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3433 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) 3422 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3434 continue; 3423 continue;
3435 3424
3436 epctrl = dwc2_readl(hsotg->regs + DIEPCTL(idx)); 3425 epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
3437 if ((epctrl & DXEPCTL_EPENA) && 3426 if ((epctrl & DXEPCTL_EPENA) &&
3438 dwc2_gadget_target_frame_elapsed(hs_ep)) { 3427 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3439 epctrl |= DXEPCTL_SNAK; 3428 epctrl |= DXEPCTL_SNAK;
3440 epctrl |= DXEPCTL_EPDIS; 3429 epctrl |= DXEPCTL_EPDIS;
3441 dwc2_writel(epctrl, hsotg->regs + DIEPCTL(idx)); 3430 dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
3442 } 3431 }
3443 } 3432 }
3444 3433
3445 /* Clear interrupt */ 3434 /* Clear interrupt */
3446 dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS); 3435 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
3447} 3436}
3448 3437
3449/** 3438/**
@@ -3470,7 +3459,7 @@ static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3470 3459
3471 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__); 3460 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3472 3461
3473 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); 3462 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3474 daintmsk >>= DAINT_OUTEP_SHIFT; 3463 daintmsk >>= DAINT_OUTEP_SHIFT;
3475 3464
3476 for (idx = 1; idx < hsotg->num_of_eps; idx++) { 3465 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
@@ -3479,24 +3468,24 @@ static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3479 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) 3468 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3480 continue; 3469 continue;
3481 3470
3482 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); 3471 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3483 if ((epctrl & DXEPCTL_EPENA) && 3472 if ((epctrl & DXEPCTL_EPENA) &&
3484 dwc2_gadget_target_frame_elapsed(hs_ep)) { 3473 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3485 /* Unmask GOUTNAKEFF interrupt */ 3474 /* Unmask GOUTNAKEFF interrupt */
3486 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3475 gintmsk = dwc2_readl(hsotg, GINTMSK);
3487 gintmsk |= GINTSTS_GOUTNAKEFF; 3476 gintmsk |= GINTSTS_GOUTNAKEFF;
3488 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3477 dwc2_writel(hsotg, gintmsk, GINTMSK);
3489 3478
3490 gintsts = dwc2_readl(hsotg->regs + GINTSTS); 3479 gintsts = dwc2_readl(hsotg, GINTSTS);
3491 if (!(gintsts & GINTSTS_GOUTNAKEFF)) { 3480 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3492 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGOUTNAK); 3481 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3493 break; 3482 break;
3494 } 3483 }
3495 } 3484 }
3496 } 3485 }
3497 3486
3498 /* Clear interrupt */ 3487 /* Clear interrupt */
3499 dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS); 3488 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
3500} 3489}
3501 3490
3502/** 3491/**
@@ -3516,8 +3505,8 @@ static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3516 3505
3517 spin_lock(&hsotg->lock); 3506 spin_lock(&hsotg->lock);
3518irq_retry: 3507irq_retry:
3519 gintsts = dwc2_readl(hsotg->regs + GINTSTS); 3508 gintsts = dwc2_readl(hsotg, GINTSTS);
3520 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3509 gintmsk = dwc2_readl(hsotg, GINTMSK);
3521 3510
3522 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", 3511 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3523 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); 3512 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
@@ -3527,7 +3516,7 @@ irq_retry:
3527 if (gintsts & GINTSTS_RESETDET) { 3516 if (gintsts & GINTSTS_RESETDET) {
3528 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); 3517 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3529 3518
3530 dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS); 3519 dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
3531 3520
3532 /* This event must be used only if controller is suspended */ 3521 /* This event must be used only if controller is suspended */
3533 if (hsotg->lx_state == DWC2_L2) { 3522 if (hsotg->lx_state == DWC2_L2) {
@@ -3537,34 +3526,34 @@ irq_retry:
3537 } 3526 }
3538 3527
3539 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { 3528 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3540 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL); 3529 u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
3541 u32 connected = hsotg->connected; 3530 u32 connected = hsotg->connected;
3542 3531
3543 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); 3532 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3544 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", 3533 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3545 dwc2_readl(hsotg->regs + GNPTXSTS)); 3534 dwc2_readl(hsotg, GNPTXSTS));
3546 3535
3547 dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); 3536 dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
3548 3537
3549 /* Report disconnection if it is not already done. */ 3538 /* Report disconnection if it is not already done. */
3550 dwc2_hsotg_disconnect(hsotg); 3539 dwc2_hsotg_disconnect(hsotg);
3551 3540
3552 /* Reset device address to zero */ 3541 /* Reset device address to zero */
3553 dwc2_clear_bit(hsotg->regs + DCFG, DCFG_DEVADDR_MASK); 3542 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
3554 3543
3555 if (usb_status & GOTGCTL_BSESVLD && connected) 3544 if (usb_status & GOTGCTL_BSESVLD && connected)
3556 dwc2_hsotg_core_init_disconnected(hsotg, true); 3545 dwc2_hsotg_core_init_disconnected(hsotg, true);
3557 } 3546 }
3558 3547
3559 if (gintsts & GINTSTS_ENUMDONE) { 3548 if (gintsts & GINTSTS_ENUMDONE) {
3560 dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); 3549 dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
3561 3550
3562 dwc2_hsotg_irq_enumdone(hsotg); 3551 dwc2_hsotg_irq_enumdone(hsotg);
3563 } 3552 }
3564 3553
3565 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { 3554 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3566 u32 daint = dwc2_readl(hsotg->regs + DAINT); 3555 u32 daint = dwc2_readl(hsotg, DAINT);
3567 u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); 3556 u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3568 u32 daint_out, daint_in; 3557 u32 daint_out, daint_in;
3569 int ep; 3558 int ep;
3570 3559
@@ -3623,7 +3612,7 @@ irq_retry:
3623 3612
3624 if (gintsts & GINTSTS_ERLYSUSP) { 3613 if (gintsts & GINTSTS_ERLYSUSP) {
3625 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); 3614 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3626 dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); 3615 dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
3627 } 3616 }
3628 3617
3629 /* 3618 /*
@@ -3639,12 +3628,12 @@ irq_retry:
3639 u32 daintmsk; 3628 u32 daintmsk;
3640 struct dwc2_hsotg_ep *hs_ep; 3629 struct dwc2_hsotg_ep *hs_ep;
3641 3630
3642 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); 3631 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3643 daintmsk >>= DAINT_OUTEP_SHIFT; 3632 daintmsk >>= DAINT_OUTEP_SHIFT;
3644 /* Mask this interrupt */ 3633 /* Mask this interrupt */
3645 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3634 gintmsk = dwc2_readl(hsotg, GINTMSK);
3646 gintmsk &= ~GINTSTS_GOUTNAKEFF; 3635 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3647 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3636 dwc2_writel(hsotg, gintmsk, GINTMSK);
3648 3637
3649 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n"); 3638 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3650 for (idx = 1; idx < hsotg->num_of_eps; idx++) { 3639 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
@@ -3653,12 +3642,12 @@ irq_retry:
3653 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) 3642 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3654 continue; 3643 continue;
3655 3644
3656 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); 3645 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3657 3646
3658 if (epctrl & DXEPCTL_EPENA) { 3647 if (epctrl & DXEPCTL_EPENA) {
3659 epctrl |= DXEPCTL_SNAK; 3648 epctrl |= DXEPCTL_SNAK;
3660 epctrl |= DXEPCTL_EPDIS; 3649 epctrl |= DXEPCTL_EPDIS;
3661 dwc2_writel(epctrl, hsotg->regs + DOEPCTL(idx)); 3650 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3662 } 3651 }
3663 } 3652 }
3664 3653
@@ -3668,7 +3657,7 @@ irq_retry:
3668 if (gintsts & GINTSTS_GINNAKEFF) { 3657 if (gintsts & GINTSTS_GINNAKEFF) {
3669 dev_info(hsotg->dev, "GINNakEff triggered\n"); 3658 dev_info(hsotg->dev, "GINNakEff triggered\n");
3670 3659
3671 dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGNPINNAK); 3660 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3672 3661
3673 dwc2_hsotg_dump(hsotg); 3662 dwc2_hsotg_dump(hsotg);
3674 } 3663 }
@@ -3708,7 +3697,7 @@ static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3708 3697
3709 if (hs_ep->dir_in) { 3698 if (hs_ep->dir_in) {
3710 if (hsotg->dedicated_fifos || hs_ep->periodic) { 3699 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3711 dwc2_set_bit(hsotg->regs + epctrl_reg, DXEPCTL_SNAK); 3700 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
3712 /* Wait for Nak effect */ 3701 /* Wait for Nak effect */
3713 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, 3702 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3714 DXEPINT_INEPNAKEFF, 100)) 3703 DXEPINT_INEPNAKEFF, 100))
@@ -3716,7 +3705,7 @@ static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3716 "%s: timeout DIEPINT.NAKEFF\n", 3705 "%s: timeout DIEPINT.NAKEFF\n",
3717 __func__); 3706 __func__);
3718 } else { 3707 } else {
3719 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGNPINNAK); 3708 dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
3720 /* Wait for Nak effect */ 3709 /* Wait for Nak effect */
3721 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, 3710 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3722 GINTSTS_GINNAKEFF, 100)) 3711 GINTSTS_GINNAKEFF, 100))
@@ -3725,8 +3714,8 @@ static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3725 __func__); 3714 __func__);
3726 } 3715 }
3727 } else { 3716 } else {
3728 if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF)) 3717 if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
3729 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGOUTNAK); 3718 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3730 3719
3731 /* Wait for global nak to take effect */ 3720 /* Wait for global nak to take effect */
3732 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, 3721 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
@@ -3736,7 +3725,7 @@ static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3736 } 3725 }
3737 3726
3738 /* Disable ep */ 3727 /* Disable ep */
3739 dwc2_set_bit(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); 3728 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3740 3729
3741 /* Wait for ep to be disabled */ 3730 /* Wait for ep to be disabled */
3742 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100)) 3731 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
@@ -3744,7 +3733,7 @@ static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3744 "%s: timeout DOEPCTL.EPDisable\n", __func__); 3733 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3745 3734
3746 /* Clear EPDISBLD interrupt */ 3735 /* Clear EPDISBLD interrupt */
3747 dwc2_set_bit(hsotg->regs + epint_reg, DXEPINT_EPDISBLD); 3736 dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
3748 3737
3749 if (hs_ep->dir_in) { 3738 if (hs_ep->dir_in) {
3750 unsigned short fifo_index; 3739 unsigned short fifo_index;
@@ -3759,11 +3748,11 @@ static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3759 3748
3760 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */ 3749 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3761 if (!hsotg->dedicated_fifos && !hs_ep->periodic) 3750 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3762 dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGNPINNAK); 3751 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3763 3752
3764 } else { 3753 } else {
3765 /* Remove global NAKs */ 3754 /* Remove global NAKs */
3766 dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGOUTNAK); 3755 dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
3767 } 3756 }
3768} 3757}
3769 3758
@@ -3831,7 +3820,7 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3831 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ 3820 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
3832 3821
3833 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); 3822 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
3834 epctrl = dwc2_readl(hsotg->regs + epctrl_reg); 3823 epctrl = dwc2_readl(hsotg, epctrl_reg);
3835 3824
3836 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", 3825 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
3837 __func__, epctrl, epctrl_reg); 3826 __func__, epctrl, epctrl_reg);
@@ -3879,13 +3868,13 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3879 hs_ep->compl_desc = 0; 3868 hs_ep->compl_desc = 0;
3880 if (dir_in) { 3869 if (dir_in) {
3881 hs_ep->periodic = 1; 3870 hs_ep->periodic = 1;
3882 mask = dwc2_readl(hsotg->regs + DIEPMSK); 3871 mask = dwc2_readl(hsotg, DIEPMSK);
3883 mask |= DIEPMSK_NAKMSK; 3872 mask |= DIEPMSK_NAKMSK;
3884 dwc2_writel(mask, hsotg->regs + DIEPMSK); 3873 dwc2_writel(hsotg, mask, DIEPMSK);
3885 } else { 3874 } else {
3886 mask = dwc2_readl(hsotg->regs + DOEPMSK); 3875 mask = dwc2_readl(hsotg, DOEPMSK);
3887 mask |= DOEPMSK_OUTTKNEPDISMSK; 3876 mask |= DOEPMSK_OUTTKNEPDISMSK;
3888 dwc2_writel(mask, hsotg->regs + DOEPMSK); 3877 dwc2_writel(hsotg, mask, DOEPMSK);
3889 } 3878 }
3890 break; 3879 break;
3891 3880
@@ -3920,7 +3909,7 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3920 for (i = 1; i < hsotg->num_of_eps; ++i) { 3909 for (i = 1; i < hsotg->num_of_eps; ++i) {
3921 if (hsotg->fifo_map & (1 << i)) 3910 if (hsotg->fifo_map & (1 << i))
3922 continue; 3911 continue;
3923 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); 3912 val = dwc2_readl(hsotg, DPTXFSIZN(i));
3924 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4; 3913 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
3925 if (val < size) 3914 if (val < size)
3926 continue; 3915 continue;
@@ -3958,7 +3947,7 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3958 * to 4.00a (including both). Also for FS_IOT_1.00a 3947 * to 4.00a (including both). Also for FS_IOT_1.00a
3959 * and HS_IOT_1.00a. 3948 * and HS_IOT_1.00a.
3960 */ 3949 */
3961 u32 gsnpsid = dwc2_readl(hsotg->regs + GSNPSID); 3950 u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
3962 3951
3963 if ((gsnpsid >= DWC2_CORE_REV_2_72a && 3952 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
3964 gsnpsid <= DWC2_CORE_REV_4_00a) || 3953 gsnpsid <= DWC2_CORE_REV_4_00a) ||
@@ -3970,9 +3959,9 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3970 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", 3959 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
3971 __func__, epctrl); 3960 __func__, epctrl);
3972 3961
3973 dwc2_writel(epctrl, hsotg->regs + epctrl_reg); 3962 dwc2_writel(hsotg, epctrl, epctrl_reg);
3974 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", 3963 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
3975 __func__, dwc2_readl(hsotg->regs + epctrl_reg)); 3964 __func__, dwc2_readl(hsotg, epctrl_reg));
3976 3965
3977 /* enable the endpoint interrupt */ 3966 /* enable the endpoint interrupt */
3978 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); 3967 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
@@ -4021,7 +4010,7 @@ static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4021 4010
4022 spin_lock_irqsave(&hsotg->lock, flags); 4011 spin_lock_irqsave(&hsotg->lock, flags);
4023 4012
4024 ctrl = dwc2_readl(hsotg->regs + epctrl_reg); 4013 ctrl = dwc2_readl(hsotg, epctrl_reg);
4025 4014
4026 if (ctrl & DXEPCTL_EPENA) 4015 if (ctrl & DXEPCTL_EPENA)
4027 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep); 4016 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
@@ -4031,7 +4020,7 @@ static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4031 ctrl |= DXEPCTL_SNAK; 4020 ctrl |= DXEPCTL_SNAK;
4032 4021
4033 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); 4022 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4034 dwc2_writel(ctrl, hsotg->regs + epctrl_reg); 4023 dwc2_writel(hsotg, ctrl, epctrl_reg);
4035 4024
4036 /* disable endpoint interrupts */ 4025 /* disable endpoint interrupts */
4037 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); 4026 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
@@ -4138,7 +4127,7 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4138 4127
4139 if (hs_ep->dir_in) { 4128 if (hs_ep->dir_in) {
4140 epreg = DIEPCTL(index); 4129 epreg = DIEPCTL(index);
4141 epctl = dwc2_readl(hs->regs + epreg); 4130 epctl = dwc2_readl(hs, epreg);
4142 4131
4143 if (value) { 4132 if (value) {
4144 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; 4133 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
@@ -4151,10 +4140,10 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4151 xfertype == DXEPCTL_EPTYPE_INTERRUPT) 4140 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4152 epctl |= DXEPCTL_SETD0PID; 4141 epctl |= DXEPCTL_SETD0PID;
4153 } 4142 }
4154 dwc2_writel(epctl, hs->regs + epreg); 4143 dwc2_writel(hs, epctl, epreg);
4155 } else { 4144 } else {
4156 epreg = DOEPCTL(index); 4145 epreg = DOEPCTL(index);
4157 epctl = dwc2_readl(hs->regs + epreg); 4146 epctl = dwc2_readl(hs, epreg);
4158 4147
4159 if (value) { 4148 if (value) {
4160 epctl |= DXEPCTL_STALL; 4149 epctl |= DXEPCTL_STALL;
@@ -4165,7 +4154,7 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4165 xfertype == DXEPCTL_EPTYPE_INTERRUPT) 4154 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4166 epctl |= DXEPCTL_SETD0PID; 4155 epctl |= DXEPCTL_SETD0PID;
4167 } 4156 }
4168 dwc2_writel(epctl, hs->regs + epreg); 4157 dwc2_writel(hs, epctl, epreg);
4169 } 4158 }
4170 4159
4171 hs_ep->halted = value; 4160 hs_ep->halted = value;
@@ -4213,29 +4202,29 @@ static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4213 u32 usbcfg; 4202 u32 usbcfg;
4214 /* unmask subset of endpoint interrupts */ 4203 /* unmask subset of endpoint interrupts */
4215 4204
4216 dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | 4205 dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4217 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, 4206 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4218 hsotg->regs + DIEPMSK); 4207 DIEPMSK);
4219 4208
4220 dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | 4209 dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4221 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, 4210 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4222 hsotg->regs + DOEPMSK); 4211 DOEPMSK);
4223 4212
4224 dwc2_writel(0, hsotg->regs + DAINTMSK); 4213 dwc2_writel(hsotg, 0, DAINTMSK);
4225 4214
4226 /* Be in disconnected state until gadget is registered */ 4215 /* Be in disconnected state until gadget is registered */
4227 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); 4216 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
4228 4217
4229 /* setup fifos */ 4218 /* setup fifos */
4230 4219
4231 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", 4220 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4232 dwc2_readl(hsotg->regs + GRXFSIZ), 4221 dwc2_readl(hsotg, GRXFSIZ),
4233 dwc2_readl(hsotg->regs + GNPTXFSIZ)); 4222 dwc2_readl(hsotg, GNPTXFSIZ));
4234 4223
4235 dwc2_hsotg_init_fifo(hsotg); 4224 dwc2_hsotg_init_fifo(hsotg);
4236 4225
4237 /* keep other bits untouched (so e.g. forced modes are not lost) */ 4226 /* keep other bits untouched (so e.g. forced modes are not lost) */
4238 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 4227 usbcfg = dwc2_readl(hsotg, GUSBCFG);
4239 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | 4228 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
4240 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK); 4229 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
4241 4230
@@ -4243,10 +4232,10 @@ static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4243 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; 4232 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
4244 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | 4233 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
4245 (trdtim << GUSBCFG_USBTRDTIM_SHIFT); 4234 (trdtim << GUSBCFG_USBTRDTIM_SHIFT);
4246 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 4235 dwc2_writel(hsotg, usbcfg, GUSBCFG);
4247 4236
4248 if (using_dma(hsotg)) 4237 if (using_dma(hsotg))
4249 dwc2_set_bit(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN); 4238 dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
4250} 4239}
4251 4240
4252/** 4241/**
@@ -4536,9 +4525,9 @@ static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4536 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); 4525 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4537 4526
4538 if (dir_in) 4527 if (dir_in)
4539 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum)); 4528 dwc2_writel(hsotg, next, DIEPCTL(epnum));
4540 else 4529 else
4541 dwc2_writel(next, hsotg->regs + DOEPCTL(epnum)); 4530 dwc2_writel(hsotg, next, DOEPCTL(epnum));
4542 } 4531 }
4543} 4532}
4544 4533
@@ -4607,24 +4596,23 @@ static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4607{ 4596{
4608#ifdef DEBUG 4597#ifdef DEBUG
4609 struct device *dev = hsotg->dev; 4598 struct device *dev = hsotg->dev;
4610 void __iomem *regs = hsotg->regs;
4611 u32 val; 4599 u32 val;
4612 int idx; 4600 int idx;
4613 4601
4614 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", 4602 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4615 dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL), 4603 dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
4616 dwc2_readl(regs + DIEPMSK)); 4604 dwc2_readl(hsotg, DIEPMSK));
4617 4605
4618 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", 4606 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4619 dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1)); 4607 dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
4620 4608
4621 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", 4609 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4622 dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ)); 4610 dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
4623 4611
4624 /* show periodic fifo settings */ 4612 /* show periodic fifo settings */
4625 4613
4626 for (idx = 1; idx < hsotg->num_of_eps; idx++) { 4614 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4627 val = dwc2_readl(regs + DPTXFSIZN(idx)); 4615 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
4628 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, 4616 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4629 val >> FIFOSIZE_DEPTH_SHIFT, 4617 val >> FIFOSIZE_DEPTH_SHIFT,
4630 val & FIFOSIZE_STARTADDR_MASK); 4618 val & FIFOSIZE_STARTADDR_MASK);
@@ -4633,20 +4621,20 @@ static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4633 for (idx = 0; idx < hsotg->num_of_eps; idx++) { 4621 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4634 dev_info(dev, 4622 dev_info(dev,
4635 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, 4623 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4636 dwc2_readl(regs + DIEPCTL(idx)), 4624 dwc2_readl(hsotg, DIEPCTL(idx)),
4637 dwc2_readl(regs + DIEPTSIZ(idx)), 4625 dwc2_readl(hsotg, DIEPTSIZ(idx)),
4638 dwc2_readl(regs + DIEPDMA(idx))); 4626 dwc2_readl(hsotg, DIEPDMA(idx)));
4639 4627
4640 val = dwc2_readl(regs + DOEPCTL(idx)); 4628 val = dwc2_readl(hsotg, DOEPCTL(idx));
4641 dev_info(dev, 4629 dev_info(dev,
4642 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", 4630 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4643 idx, dwc2_readl(regs + DOEPCTL(idx)), 4631 idx, dwc2_readl(hsotg, DOEPCTL(idx)),
4644 dwc2_readl(regs + DOEPTSIZ(idx)), 4632 dwc2_readl(hsotg, DOEPTSIZ(idx)),
4645 dwc2_readl(regs + DOEPDMA(idx))); 4633 dwc2_readl(hsotg, DOEPDMA(idx)));
4646 } 4634 }
4647 4635
4648 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", 4636 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4649 dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE)); 4637 dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
4650#endif 4638#endif
4651} 4639}
4652 4640
@@ -4835,15 +4823,15 @@ int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
4835 /* Backup dev regs */ 4823 /* Backup dev regs */
4836 dr = &hsotg->dr_backup; 4824 dr = &hsotg->dr_backup;
4837 4825
4838 dr->dcfg = dwc2_readl(hsotg->regs + DCFG); 4826 dr->dcfg = dwc2_readl(hsotg, DCFG);
4839 dr->dctl = dwc2_readl(hsotg->regs + DCTL); 4827 dr->dctl = dwc2_readl(hsotg, DCTL);
4840 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); 4828 dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
4841 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK); 4829 dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
4842 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); 4830 dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
4843 4831
4844 for (i = 0; i < hsotg->num_of_eps; i++) { 4832 for (i = 0; i < hsotg->num_of_eps; i++) {
4845 /* Backup IN EPs */ 4833 /* Backup IN EPs */
4846 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i)); 4834 dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
4847 4835
4848 /* Ensure DATA PID is correctly configured */ 4836 /* Ensure DATA PID is correctly configured */
4849 if (dr->diepctl[i] & DXEPCTL_DPID) 4837 if (dr->diepctl[i] & DXEPCTL_DPID)
@@ -4851,11 +4839,11 @@ int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
4851 else 4839 else
4852 dr->diepctl[i] |= DXEPCTL_SETD0PID; 4840 dr->diepctl[i] |= DXEPCTL_SETD0PID;
4853 4841
4854 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i)); 4842 dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
4855 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i)); 4843 dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
4856 4844
4857 /* Backup OUT EPs */ 4845 /* Backup OUT EPs */
4858 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i)); 4846 dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
4859 4847
4860 /* Ensure DATA PID is correctly configured */ 4848 /* Ensure DATA PID is correctly configured */
4861 if (dr->doepctl[i] & DXEPCTL_DPID) 4849 if (dr->doepctl[i] & DXEPCTL_DPID)
@@ -4863,9 +4851,9 @@ int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
4863 else 4851 else
4864 dr->doepctl[i] |= DXEPCTL_SETD0PID; 4852 dr->doepctl[i] |= DXEPCTL_SETD0PID;
4865 4853
4866 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i)); 4854 dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
4867 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i)); 4855 dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
4868 dr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); 4856 dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
4869 } 4857 }
4870 dr->valid = true; 4858 dr->valid = true;
4871 return 0; 4859 return 0;
@@ -4898,17 +4886,17 @@ int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
4898 dr->valid = false; 4886 dr->valid = false;
4899 4887
4900 if (!remote_wakeup) 4888 if (!remote_wakeup)
4901 dwc2_writel(dr->dctl, hsotg->regs + DCTL); 4889 dwc2_writel(hsotg, dr->dctl, DCTL);
4902 4890
4903 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK); 4891 dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
4904 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK); 4892 dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
4905 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK); 4893 dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
4906 4894
4907 for (i = 0; i < hsotg->num_of_eps; i++) { 4895 for (i = 0; i < hsotg->num_of_eps; i++) {
4908 /* Restore IN EPs */ 4896 /* Restore IN EPs */
4909 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i)); 4897 dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
4910 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i)); 4898 dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
4911 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); 4899 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
4912 /** WA for enabled EPx's IN in DDMA mode. On entering to 4900 /** WA for enabled EPx's IN in DDMA mode. On entering to
4913 * hibernation wrong value read and saved from DIEPDMAx, 4901 * hibernation wrong value read and saved from DIEPDMAx,
4914 * as result BNA interrupt asserted on hibernation exit 4902 * as result BNA interrupt asserted on hibernation exit
@@ -4917,10 +4905,10 @@ int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
4917 if (hsotg->params.g_dma_desc && 4905 if (hsotg->params.g_dma_desc &&
4918 (dr->diepctl[i] & DXEPCTL_EPENA)) 4906 (dr->diepctl[i] & DXEPCTL_EPENA))
4919 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma; 4907 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
4920 dwc2_writel(dr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i)); 4908 dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
4921 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i)); 4909 dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
4922 /* Restore OUT EPs */ 4910 /* Restore OUT EPs */
4923 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); 4911 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
4924 /* WA for enabled EPx's OUT in DDMA mode. On entering to 4912 /* WA for enabled EPx's OUT in DDMA mode. On entering to
4925 * hibernation wrong value read and saved from DOEPDMAx, 4913 * hibernation wrong value read and saved from DOEPDMAx,
4926 * as result BNA interrupt asserted on hibernation exit 4914 * as result BNA interrupt asserted on hibernation exit
@@ -4929,8 +4917,8 @@ int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
4929 if (hsotg->params.g_dma_desc && 4917 if (hsotg->params.g_dma_desc &&
4930 (dr->doepctl[i] & DXEPCTL_EPENA)) 4918 (dr->doepctl[i] & DXEPCTL_EPENA))
4931 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma; 4919 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
4932 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i)); 4920 dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
4933 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i)); 4921 dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
4934 } 4922 }
4935 4923
4936 return 0; 4924 return 0;
@@ -4954,9 +4942,8 @@ void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
4954 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0; 4942 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
4955 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT; 4943 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
4956 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0; 4944 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
4957 dwc2_writel(val, hsotg->regs + GLPMCFG); 4945 dwc2_writel(hsotg, val, GLPMCFG);
4958 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg->regs 4946 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
4959 + GLPMCFG));
4960} 4947}
4961 4948
4962/** 4949/**
@@ -4989,40 +4976,40 @@ int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
4989 4976
4990 gpwrdn = GPWRDN_PWRDNRSTN; 4977 gpwrdn = GPWRDN_PWRDNRSTN;
4991 gpwrdn |= GPWRDN_PMUACTV; 4978 gpwrdn |= GPWRDN_PMUACTV;
4992 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 4979 dwc2_writel(hsotg, gpwrdn, GPWRDN);
4993 udelay(10); 4980 udelay(10);
4994 4981
4995 /* Set flag to indicate that we are in hibernation */ 4982 /* Set flag to indicate that we are in hibernation */
4996 hsotg->hibernated = 1; 4983 hsotg->hibernated = 1;
4997 4984
4998 /* Enable interrupts from wake up logic */ 4985 /* Enable interrupts from wake up logic */
4999 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 4986 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5000 gpwrdn |= GPWRDN_PMUINTSEL; 4987 gpwrdn |= GPWRDN_PMUINTSEL;
5001 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 4988 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5002 udelay(10); 4989 udelay(10);
5003 4990
5004 /* Unmask device mode interrupts in GPWRDN */ 4991 /* Unmask device mode interrupts in GPWRDN */
5005 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 4992 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5006 gpwrdn |= GPWRDN_RST_DET_MSK; 4993 gpwrdn |= GPWRDN_RST_DET_MSK;
5007 gpwrdn |= GPWRDN_LNSTSCHG_MSK; 4994 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5008 gpwrdn |= GPWRDN_STS_CHGINT_MSK; 4995 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5009 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 4996 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5010 udelay(10); 4997 udelay(10);
5011 4998
5012 /* Enable Power Down Clamp */ 4999 /* Enable Power Down Clamp */
5013 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5000 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5014 gpwrdn |= GPWRDN_PWRDNCLMP; 5001 gpwrdn |= GPWRDN_PWRDNCLMP;
5015 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5002 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5016 udelay(10); 5003 udelay(10);
5017 5004
5018 /* Switch off VDD */ 5005 /* Switch off VDD */
5019 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5006 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5020 gpwrdn |= GPWRDN_PWRDNSWTCH; 5007 gpwrdn |= GPWRDN_PWRDNSWTCH;
5021 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5008 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5022 udelay(10); 5009 udelay(10);
5023 5010
5024 /* Save gpwrdn register for further usage if stschng interrupt */ 5011 /* Save gpwrdn register for further usage if stschng interrupt */
5025 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5012 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
5026 dev_dbg(hsotg->dev, "Hibernation completed\n"); 5013 dev_dbg(hsotg->dev, "Hibernation completed\n");
5027 5014
5028 return ret; 5015 return ret;
@@ -5064,46 +5051,46 @@ int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5064 5051
5065 if (!reset) { 5052 if (!reset) {
5066 /* Clear all pending interupts */ 5053 /* Clear all pending interupts */
5067 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 5054 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5068 } 5055 }
5069 5056
5070 /* De-assert Restore */ 5057 /* De-assert Restore */
5071 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5058 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5072 gpwrdn &= ~GPWRDN_RESTORE; 5059 gpwrdn &= ~GPWRDN_RESTORE;
5073 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5060 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5074 udelay(10); 5061 udelay(10);
5075 5062
5076 if (!rem_wakeup) { 5063 if (!rem_wakeup) {
5077 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 5064 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5078 pcgcctl &= ~PCGCTL_RSTPDWNMODULE; 5065 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5079 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 5066 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5080 } 5067 }
5081 5068
5082 /* Restore GUSBCFG, DCFG and DCTL */ 5069 /* Restore GUSBCFG, DCFG and DCTL */
5083 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG); 5070 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5084 dwc2_writel(dr->dcfg, hsotg->regs + DCFG); 5071 dwc2_writel(hsotg, dr->dcfg, DCFG);
5085 dwc2_writel(dr->dctl, hsotg->regs + DCTL); 5072 dwc2_writel(hsotg, dr->dctl, DCTL);
5086 5073
5087 /* De-assert Wakeup Logic */ 5074 /* De-assert Wakeup Logic */
5088 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5075 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5089 gpwrdn &= ~GPWRDN_PMUACTV; 5076 gpwrdn &= ~GPWRDN_PMUACTV;
5090 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5077 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5091 5078
5092 if (rem_wakeup) { 5079 if (rem_wakeup) {
5093 udelay(10); 5080 udelay(10);
5094 /* Start Remote Wakeup Signaling */ 5081 /* Start Remote Wakeup Signaling */
5095 dwc2_writel(dr->dctl | DCTL_RMTWKUPSIG, hsotg->regs + DCTL); 5082 dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
5096 } else { 5083 } else {
5097 udelay(50); 5084 udelay(50);
5098 /* Set Device programming done bit */ 5085 /* Set Device programming done bit */
5099 dctl = dwc2_readl(hsotg->regs + DCTL); 5086 dctl = dwc2_readl(hsotg, DCTL);
5100 dctl |= DCTL_PWRONPRGDONE; 5087 dctl |= DCTL_PWRONPRGDONE;
5101 dwc2_writel(dctl, hsotg->regs + DCTL); 5088 dwc2_writel(hsotg, dctl, DCTL);
5102 } 5089 }
5103 /* Wait for interrupts which must be cleared */ 5090 /* Wait for interrupts which must be cleared */
5104 mdelay(2); 5091 mdelay(2);
5105 /* Clear all pending interupts */ 5092 /* Clear all pending interupts */
5106 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 5093 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5107 5094
5108 /* Restore global registers */ 5095 /* Restore global registers */
5109 ret = dwc2_restore_global_registers(hsotg); 5096 ret = dwc2_restore_global_registers(hsotg);
@@ -5123,9 +5110,9 @@ int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5123 5110
5124 if (rem_wakeup) { 5111 if (rem_wakeup) {
5125 mdelay(10); 5112 mdelay(10);
5126 dctl = dwc2_readl(hsotg->regs + DCTL); 5113 dctl = dwc2_readl(hsotg, DCTL);
5127 dctl &= ~DCTL_RMTWKUPSIG; 5114 dctl &= ~DCTL_RMTWKUPSIG;
5128 dwc2_writel(dctl, hsotg->regs + DCTL); 5115 dwc2_writel(hsotg, dctl, DCTL);
5129 } 5116 }
5130 5117
5131 hsotg->hibernated = 0; 5118 hsotg->hibernated = 0;
diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index 6e2cdd7b93d4..2bd6e6bfc241 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -75,10 +75,10 @@ static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
75 u32 intmsk; 75 u32 intmsk;
76 76
77 /* Clear any pending OTG Interrupts */ 77 /* Clear any pending OTG Interrupts */
78 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); 78 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
79 79
80 /* Clear any pending interrupts */ 80 /* Clear any pending interrupts */
81 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 81 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
82 82
83 /* Enable the interrupts in the GINTMSK */ 83 /* Enable the interrupts in the GINTMSK */
84 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; 84 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
@@ -94,7 +94,7 @@ static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
94 if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm) 94 if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm)
95 intmsk |= GINTSTS_LPMTRANRCVD; 95 intmsk |= GINTSTS_LPMTRANRCVD;
96 96
97 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 97 dwc2_writel(hsotg, intmsk, GINTMSK);
98} 98}
99 99
100/* 100/*
@@ -117,10 +117,10 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
117 } 117 }
118 118
119 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); 119 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
120 hcfg = dwc2_readl(hsotg->regs + HCFG); 120 hcfg = dwc2_readl(hsotg, HCFG);
121 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 121 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
122 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; 122 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
123 dwc2_writel(hcfg, hsotg->regs + HCFG); 123 dwc2_writel(hsotg, hcfg, HCFG);
124} 124}
125 125
126static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 126static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
@@ -135,10 +135,10 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
135 if (select_phy) { 135 if (select_phy) {
136 dev_dbg(hsotg->dev, "FS PHY selected\n"); 136 dev_dbg(hsotg->dev, "FS PHY selected\n");
137 137
138 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 138 usbcfg = dwc2_readl(hsotg, GUSBCFG);
139 if (!(usbcfg & GUSBCFG_PHYSEL)) { 139 if (!(usbcfg & GUSBCFG_PHYSEL)) {
140 usbcfg |= GUSBCFG_PHYSEL; 140 usbcfg |= GUSBCFG_PHYSEL;
141 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 141 dwc2_writel(hsotg, usbcfg, GUSBCFG);
142 142
143 /* Reset after a PHY select */ 143 /* Reset after a PHY select */
144 retval = dwc2_core_reset(hsotg, false); 144 retval = dwc2_core_reset(hsotg, false);
@@ -151,7 +151,7 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
151 } 151 }
152 152
153 if (hsotg->params.activate_stm_fs_transceiver) { 153 if (hsotg->params.activate_stm_fs_transceiver) {
154 ggpio = dwc2_readl(hsotg->regs + GGPIO); 154 ggpio = dwc2_readl(hsotg, GGPIO);
155 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) { 155 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
156 dev_dbg(hsotg->dev, "Activating transceiver\n"); 156 dev_dbg(hsotg->dev, "Activating transceiver\n");
157 /* 157 /*
@@ -159,7 +159,7 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
159 * core configuration register. 159 * core configuration register.
160 */ 160 */
161 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN; 161 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
162 dwc2_writel(ggpio, hsotg->regs + GGPIO); 162 dwc2_writel(hsotg, ggpio, GGPIO);
163 } 163 }
164 } 164 }
165 } 165 }
@@ -176,18 +176,18 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
176 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); 176 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
177 177
178 /* Program GUSBCFG.OtgUtmiFsSel to I2C */ 178 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
179 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 179 usbcfg = dwc2_readl(hsotg, GUSBCFG);
180 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; 180 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
181 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 181 dwc2_writel(hsotg, usbcfg, GUSBCFG);
182 182
183 /* Program GI2CCTL.I2CEn */ 183 /* Program GI2CCTL.I2CEn */
184 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL); 184 i2cctl = dwc2_readl(hsotg, GI2CCTL);
185 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; 185 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
186 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; 186 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
187 i2cctl &= ~GI2CCTL_I2CEN; 187 i2cctl &= ~GI2CCTL_I2CEN;
188 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); 188 dwc2_writel(hsotg, i2cctl, GI2CCTL);
189 i2cctl |= GI2CCTL_I2CEN; 189 i2cctl |= GI2CCTL_I2CEN;
190 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); 190 dwc2_writel(hsotg, i2cctl, GI2CCTL);
191 } 191 }
192 192
193 return retval; 193 return retval;
@@ -201,7 +201,7 @@ static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
201 if (!select_phy) 201 if (!select_phy)
202 return 0; 202 return 0;
203 203
204 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 204 usbcfg = dwc2_readl(hsotg, GUSBCFG);
205 usbcfg_old = usbcfg; 205 usbcfg_old = usbcfg;
206 206
207 /* 207 /*
@@ -236,7 +236,7 @@ static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
236 } 236 }
237 237
238 if (usbcfg != usbcfg_old) { 238 if (usbcfg != usbcfg_old) {
239 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 239 dwc2_writel(hsotg, usbcfg, GUSBCFG);
240 240
241 /* Reset after setting the PHY parameters */ 241 /* Reset after setting the PHY parameters */
242 retval = dwc2_core_reset(hsotg, false); 242 retval = dwc2_core_reset(hsotg, false);
@@ -273,15 +273,15 @@ static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
273 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 273 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
274 hsotg->params.ulpi_fs_ls) { 274 hsotg->params.ulpi_fs_ls) {
275 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); 275 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
276 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 276 usbcfg = dwc2_readl(hsotg, GUSBCFG);
277 usbcfg |= GUSBCFG_ULPI_FS_LS; 277 usbcfg |= GUSBCFG_ULPI_FS_LS;
278 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; 278 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
279 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 279 dwc2_writel(hsotg, usbcfg, GUSBCFG);
280 } else { 280 } else {
281 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 281 usbcfg = dwc2_readl(hsotg, GUSBCFG);
282 usbcfg &= ~GUSBCFG_ULPI_FS_LS; 282 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
283 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; 283 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
284 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 284 dwc2_writel(hsotg, usbcfg, GUSBCFG);
285 } 285 }
286 286
287 return retval; 287 return retval;
@@ -289,7 +289,7 @@ static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
289 289
290static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) 290static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
291{ 291{
292 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 292 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
293 293
294 switch (hsotg->hw_params.arch) { 294 switch (hsotg->hw_params.arch) {
295 case GHWCFG2_EXT_DMA_ARCH: 295 case GHWCFG2_EXT_DMA_ARCH:
@@ -316,7 +316,7 @@ static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
316 else 316 else
317 hsotg->params.dma_desc_enable = false; 317 hsotg->params.dma_desc_enable = false;
318 318
319 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 319 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
320 320
321 return 0; 321 return 0;
322} 322}
@@ -325,7 +325,7 @@ static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
325{ 325{
326 u32 usbcfg; 326 u32 usbcfg;
327 327
328 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 328 usbcfg = dwc2_readl(hsotg, GUSBCFG);
329 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); 329 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
330 330
331 switch (hsotg->hw_params.op_mode) { 331 switch (hsotg->hw_params.op_mode) {
@@ -353,7 +353,7 @@ static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
353 break; 353 break;
354 } 354 }
355 355
356 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 356 dwc2_writel(hsotg, usbcfg, GUSBCFG);
357} 357}
358 358
359static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg) 359static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg)
@@ -390,16 +390,16 @@ static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
390 dev_dbg(hsotg->dev, "%s()\n", __func__); 390 dev_dbg(hsotg->dev, "%s()\n", __func__);
391 391
392 /* Disable all interrupts */ 392 /* Disable all interrupts */
393 dwc2_writel(0, hsotg->regs + GINTMSK); 393 dwc2_writel(hsotg, 0, GINTMSK);
394 dwc2_writel(0, hsotg->regs + HAINTMSK); 394 dwc2_writel(hsotg, 0, HAINTMSK);
395 395
396 /* Enable the common interrupts */ 396 /* Enable the common interrupts */
397 dwc2_enable_common_interrupts(hsotg); 397 dwc2_enable_common_interrupts(hsotg);
398 398
399 /* Enable host mode interrupts without disturbing common interrupts */ 399 /* Enable host mode interrupts without disturbing common interrupts */
400 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 400 intmsk = dwc2_readl(hsotg, GINTMSK);
401 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; 401 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
402 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 402 dwc2_writel(hsotg, intmsk, GINTMSK);
403} 403}
404 404
405/** 405/**
@@ -409,12 +409,12 @@ static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
409 */ 409 */
410static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) 410static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
411{ 411{
412 u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 412 u32 intmsk = dwc2_readl(hsotg, GINTMSK);
413 413
414 /* Disable host mode interrupts without disturbing common interrupts */ 414 /* Disable host mode interrupts without disturbing common interrupts */
415 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | 415 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
416 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT); 416 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
417 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 417 dwc2_writel(hsotg, intmsk, GINTMSK);
418} 418}
419 419
420/* 420/*
@@ -494,37 +494,37 @@ static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
494 dwc2_calculate_dynamic_fifo(hsotg); 494 dwc2_calculate_dynamic_fifo(hsotg);
495 495
496 /* Rx FIFO */ 496 /* Rx FIFO */
497 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 497 grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
498 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); 498 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
499 grxfsiz &= ~GRXFSIZ_DEPTH_MASK; 499 grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
500 grxfsiz |= params->host_rx_fifo_size << 500 grxfsiz |= params->host_rx_fifo_size <<
501 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; 501 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
502 dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ); 502 dwc2_writel(hsotg, grxfsiz, GRXFSIZ);
503 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", 503 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
504 dwc2_readl(hsotg->regs + GRXFSIZ)); 504 dwc2_readl(hsotg, GRXFSIZ));
505 505
506 /* Non-periodic Tx FIFO */ 506 /* Non-periodic Tx FIFO */
507 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", 507 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
508 dwc2_readl(hsotg->regs + GNPTXFSIZ)); 508 dwc2_readl(hsotg, GNPTXFSIZ));
509 nptxfsiz = params->host_nperio_tx_fifo_size << 509 nptxfsiz = params->host_nperio_tx_fifo_size <<
510 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 510 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
511 nptxfsiz |= params->host_rx_fifo_size << 511 nptxfsiz |= params->host_rx_fifo_size <<
512 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 512 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
513 dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); 513 dwc2_writel(hsotg, nptxfsiz, GNPTXFSIZ);
514 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", 514 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
515 dwc2_readl(hsotg->regs + GNPTXFSIZ)); 515 dwc2_readl(hsotg, GNPTXFSIZ));
516 516
517 /* Periodic Tx FIFO */ 517 /* Periodic Tx FIFO */
518 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", 518 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
519 dwc2_readl(hsotg->regs + HPTXFSIZ)); 519 dwc2_readl(hsotg, HPTXFSIZ));
520 hptxfsiz = params->host_perio_tx_fifo_size << 520 hptxfsiz = params->host_perio_tx_fifo_size <<
521 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 521 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
522 hptxfsiz |= (params->host_rx_fifo_size + 522 hptxfsiz |= (params->host_rx_fifo_size +
523 params->host_nperio_tx_fifo_size) << 523 params->host_nperio_tx_fifo_size) <<
524 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 524 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
525 dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ); 525 dwc2_writel(hsotg, hptxfsiz, HPTXFSIZ);
526 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", 526 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
527 dwc2_readl(hsotg->regs + HPTXFSIZ)); 527 dwc2_readl(hsotg, HPTXFSIZ));
528 528
529 if (hsotg->params.en_multiple_tx_fifo && 529 if (hsotg->params.en_multiple_tx_fifo &&
530 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) { 530 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) {
@@ -533,14 +533,14 @@ static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
533 * Global DFIFOCFG calculation for Host mode - 533 * Global DFIFOCFG calculation for Host mode -
534 * include RxFIFO, NPTXFIFO and HPTXFIFO 534 * include RxFIFO, NPTXFIFO and HPTXFIFO
535 */ 535 */
536 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); 536 dfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
537 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; 537 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
538 dfifocfg |= (params->host_rx_fifo_size + 538 dfifocfg |= (params->host_rx_fifo_size +
539 params->host_nperio_tx_fifo_size + 539 params->host_nperio_tx_fifo_size +
540 params->host_perio_tx_fifo_size) << 540 params->host_perio_tx_fifo_size) <<
541 GDFIFOCFG_EPINFOBASE_SHIFT & 541 GDFIFOCFG_EPINFOBASE_SHIFT &
542 GDFIFOCFG_EPINFOBASE_MASK; 542 GDFIFOCFG_EPINFOBASE_MASK;
543 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG); 543 dwc2_writel(hsotg, dfifocfg, GDFIFOCFG);
544 } 544 }
545} 545}
546 546
@@ -560,8 +560,8 @@ u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
560 u32 hprt0; 560 u32 hprt0;
561 int clock = 60; /* default value */ 561 int clock = 60; /* default value */
562 562
563 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 563 usbcfg = dwc2_readl(hsotg, GUSBCFG);
564 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 564 hprt0 = dwc2_readl(hsotg, HPRT0);
565 565
566 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && 566 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
567 !(usbcfg & GUSBCFG_PHYIF16)) 567 !(usbcfg & GUSBCFG_PHYIF16))
@@ -603,7 +603,6 @@ u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
603 */ 603 */
604void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) 604void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
605{ 605{
606 u32 __iomem *fifo = hsotg->regs + HCFIFO(0);
607 u32 *data_buf = (u32 *)dest; 606 u32 *data_buf = (u32 *)dest;
608 int word_count = (bytes + 3) / 4; 607 int word_count = (bytes + 3) / 4;
609 int i; 608 int i;
@@ -617,7 +616,7 @@ void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
617 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); 616 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
618 617
619 for (i = 0; i < word_count; i++, data_buf++) 618 for (i = 0; i < word_count; i++, data_buf++)
620 *data_buf = dwc2_readl(fifo); 619 *data_buf = dwc2_readl(hsotg, HCFIFO(0));
621} 620}
622 621
623/** 622/**
@@ -646,10 +645,10 @@ static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
646 if (!chan) 645 if (!chan)
647 return; 646 return;
648 647
649 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 648 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
650 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 649 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
651 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num)); 650 hctsiz = dwc2_readl(hsotg, HCTSIZ(chan->hc_num));
652 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num)); 651 hc_dma = dwc2_readl(hsotg, HCDMA(chan->hc_num));
653 652
654 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 653 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
655 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 654 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
@@ -797,7 +796,7 @@ static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
797 break; 796 break;
798 } 797 }
799 798
800 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 799 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
801 if (dbg_hc(chan)) 800 if (dbg_hc(chan))
802 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 801 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
803} 802}
@@ -834,7 +833,7 @@ static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
834 } 833 }
835 } 834 }
836 835
837 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 836 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
838 if (dbg_hc(chan)) 837 if (dbg_hc(chan))
839 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 838 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
840} 839}
@@ -855,16 +854,16 @@ static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
855 } 854 }
856 855
857 /* Enable the top level host channel interrupt */ 856 /* Enable the top level host channel interrupt */
858 intmsk = dwc2_readl(hsotg->regs + HAINTMSK); 857 intmsk = dwc2_readl(hsotg, HAINTMSK);
859 intmsk |= 1 << chan->hc_num; 858 intmsk |= 1 << chan->hc_num;
860 dwc2_writel(intmsk, hsotg->regs + HAINTMSK); 859 dwc2_writel(hsotg, intmsk, HAINTMSK);
861 if (dbg_hc(chan)) 860 if (dbg_hc(chan))
862 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); 861 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
863 862
864 /* Make sure host channel interrupts are enabled */ 863 /* Make sure host channel interrupts are enabled */
865 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 864 intmsk = dwc2_readl(hsotg, GINTMSK);
866 intmsk |= GINTSTS_HCHINT; 865 intmsk |= GINTSTS_HCHINT;
867 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 866 dwc2_writel(hsotg, intmsk, GINTMSK);
868 if (dbg_hc(chan)) 867 if (dbg_hc(chan))
869 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); 868 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
870} 869}
@@ -893,7 +892,7 @@ static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
893 /* Clear old interrupt conditions for this host channel */ 892 /* Clear old interrupt conditions for this host channel */
894 hcintmsk = 0xffffffff; 893 hcintmsk = 0xffffffff;
895 hcintmsk &= ~HCINTMSK_RESERVED14_31; 894 hcintmsk &= ~HCINTMSK_RESERVED14_31;
896 dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num)); 895 dwc2_writel(hsotg, hcintmsk, HCINT(hc_num));
897 896
898 /* Enable channel interrupts required for this transfer */ 897 /* Enable channel interrupts required for this transfer */
899 dwc2_hc_enable_ints(hsotg, chan); 898 dwc2_hc_enable_ints(hsotg, chan);
@@ -910,7 +909,7 @@ static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
910 hcchar |= HCCHAR_LSPDDEV; 909 hcchar |= HCCHAR_LSPDDEV;
911 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; 910 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
912 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; 911 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
913 dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num)); 912 dwc2_writel(hsotg, hcchar, HCCHAR(hc_num));
914 if (dbg_hc(chan)) { 913 if (dbg_hc(chan)) {
915 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", 914 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
916 hc_num, hcchar); 915 hc_num, hcchar);
@@ -964,7 +963,7 @@ static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
964 } 963 }
965 } 964 }
966 965
967 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); 966 dwc2_writel(hsotg, hcsplt, HCSPLT(hc_num));
968} 967}
969 968
970/** 969/**
@@ -1034,14 +1033,14 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
1034 u32 hcintmsk = HCINTMSK_CHHLTD; 1033 u32 hcintmsk = HCINTMSK_CHHLTD;
1035 1034
1036 dev_vdbg(hsotg->dev, "dequeue/error\n"); 1035 dev_vdbg(hsotg->dev, "dequeue/error\n");
1037 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 1036 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
1038 1037
1039 /* 1038 /*
1040 * Make sure no other interrupts besides halt are currently 1039 * Make sure no other interrupts besides halt are currently
1041 * pending. Handling another interrupt could cause a crash due 1040 * pending. Handling another interrupt could cause a crash due
1042 * to the QTD and QH state. 1041 * to the QTD and QH state.
1043 */ 1042 */
1044 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); 1043 dwc2_writel(hsotg, ~hcintmsk, HCINT(chan->hc_num));
1045 1044
1046 /* 1045 /*
1047 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR 1046 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
@@ -1050,7 +1049,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
1050 */ 1049 */
1051 chan->halt_status = halt_status; 1050 chan->halt_status = halt_status;
1052 1051
1053 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1052 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1054 if (!(hcchar & HCCHAR_CHENA)) { 1053 if (!(hcchar & HCCHAR_CHENA)) {
1055 /* 1054 /*
1056 * The channel is either already halted or it hasn't 1055 * The channel is either already halted or it hasn't
@@ -1078,7 +1077,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
1078 return; 1077 return;
1079 } 1078 }
1080 1079
1081 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1080 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1082 1081
1083 /* No need to set the bit in DDMA for disabling the channel */ 1082 /* No need to set the bit in DDMA for disabling the channel */
1084 /* TODO check it everywhere channel is disabled */ 1083 /* TODO check it everywhere channel is disabled */
@@ -1101,7 +1100,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
1101 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || 1100 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1102 chan->ep_type == USB_ENDPOINT_XFER_BULK) { 1101 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1103 dev_vdbg(hsotg->dev, "control/bulk\n"); 1102 dev_vdbg(hsotg->dev, "control/bulk\n");
1104 nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); 1103 nptxsts = dwc2_readl(hsotg, GNPTXSTS);
1105 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { 1104 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1106 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1105 dev_vdbg(hsotg->dev, "Disabling channel\n");
1107 hcchar &= ~HCCHAR_CHENA; 1106 hcchar &= ~HCCHAR_CHENA;
@@ -1109,7 +1108,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
1109 } else { 1108 } else {
1110 if (dbg_perio()) 1109 if (dbg_perio())
1111 dev_vdbg(hsotg->dev, "isoc/intr\n"); 1110 dev_vdbg(hsotg->dev, "isoc/intr\n");
1112 hptxsts = dwc2_readl(hsotg->regs + HPTXSTS); 1111 hptxsts = dwc2_readl(hsotg, HPTXSTS);
1113 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || 1112 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1114 hsotg->queuing_high_bandwidth) { 1113 hsotg->queuing_high_bandwidth) {
1115 if (dbg_perio()) 1114 if (dbg_perio())
@@ -1122,7 +1121,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
1122 dev_vdbg(hsotg->dev, "DMA enabled\n"); 1121 dev_vdbg(hsotg->dev, "DMA enabled\n");
1123 } 1122 }
1124 1123
1125 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1124 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1126 chan->halt_status = halt_status; 1125 chan->halt_status = halt_status;
1127 1126
1128 if (hcchar & HCCHAR_CHENA) { 1127 if (hcchar & HCCHAR_CHENA) {
@@ -1171,10 +1170,10 @@ void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1171 * Clear channel interrupt enables and any unhandled channel interrupt 1170 * Clear channel interrupt enables and any unhandled channel interrupt
1172 * conditions 1171 * conditions
1173 */ 1172 */
1174 dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); 1173 dwc2_writel(hsotg, 0, HCINTMSK(chan->hc_num));
1175 hcintmsk = 0xffffffff; 1174 hcintmsk = 0xffffffff;
1176 hcintmsk &= ~HCINTMSK_RESERVED14_31; 1175 hcintmsk &= ~HCINTMSK_RESERVED14_31;
1177 dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); 1176 dwc2_writel(hsotg, hcintmsk, HCINT(chan->hc_num));
1178} 1177}
1179 1178
1180/** 1179/**
@@ -1228,7 +1227,7 @@ static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1228 !chan->do_split) ? chan->speed : USB_SPEED_HIGH; 1227 !chan->do_split) ? chan->speed : USB_SPEED_HIGH;
1229 1228
1230 /* See how many bytes are in the periodic FIFO right now */ 1229 /* See how many bytes are in the periodic FIFO right now */
1231 fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) & 1230 fifo_space = (dwc2_readl(hsotg, HPTXSTS) &
1232 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT; 1231 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;
1233 bytes_in_fifo = sizeof(u32) * 1232 bytes_in_fifo = sizeof(u32) *
1234 (hsotg->params.host_perio_tx_fifo_size - 1233 (hsotg->params.host_perio_tx_fifo_size -
@@ -1348,13 +1347,13 @@ static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1348 if (((unsigned long)data_buf & 0x3) == 0) { 1347 if (((unsigned long)data_buf & 0x3) == 0) {
1349 /* xfer_buf is DWORD aligned */ 1348 /* xfer_buf is DWORD aligned */
1350 for (i = 0; i < dword_count; i++, data_buf++) 1349 for (i = 0; i < dword_count; i++, data_buf++)
1351 dwc2_writel(*data_buf, data_fifo); 1350 dwc2_writel(hsotg, *data_buf, HCFIFO(chan->hc_num));
1352 } else { 1351 } else {
1353 /* xfer_buf is not DWORD aligned */ 1352 /* xfer_buf is not DWORD aligned */
1354 for (i = 0; i < dword_count; i++, data_buf++) { 1353 for (i = 0; i < dword_count; i++, data_buf++) {
1355 u32 data = data_buf[0] | data_buf[1] << 8 | 1354 u32 data = data_buf[0] | data_buf[1] << 8 |
1356 data_buf[2] << 16 | data_buf[3] << 24; 1355 data_buf[2] << 16 | data_buf[3] << 24;
1357 dwc2_writel(data, data_fifo); 1356 dwc2_writel(hsotg, data, HCFIFO(chan->hc_num));
1358 } 1357 }
1359 } 1358 }
1360 1359
@@ -1383,12 +1382,12 @@ static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
1383 1382
1384 hctsiz = TSIZ_DOPNG; 1383 hctsiz = TSIZ_DOPNG;
1385 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; 1384 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
1386 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1385 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1387 1386
1388 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1387 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1389 hcchar |= HCCHAR_CHENA; 1388 hcchar |= HCCHAR_CHENA;
1390 hcchar &= ~HCCHAR_CHDIS; 1389 hcchar &= ~HCCHAR_CHDIS;
1391 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1390 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1392} 1391}
1393 1392
1394/** 1393/**
@@ -1548,7 +1547,7 @@ static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1548 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; 1547 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1549 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1548 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1550 TSIZ_SC_MC_PID_MASK; 1549 TSIZ_SC_MC_PID_MASK;
1551 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1550 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1552 if (dbg_hc(chan)) { 1551 if (dbg_hc(chan)) {
1553 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", 1552 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1554 hctsiz, chan->hc_num); 1553 hctsiz, chan->hc_num);
@@ -1576,7 +1575,7 @@ static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1576 } else { 1575 } else {
1577 dma_addr = chan->xfer_dma; 1576 dma_addr = chan->xfer_dma;
1578 } 1577 }
1579 dwc2_writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num)); 1578 dwc2_writel(hsotg, (u32)dma_addr, HCDMA(chan->hc_num));
1580 1579
1581 if (dbg_hc(chan)) 1580 if (dbg_hc(chan))
1582 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", 1581 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
@@ -1585,13 +1584,13 @@ static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1585 1584
1586 /* Start the split */ 1585 /* Start the split */
1587 if (chan->do_split) { 1586 if (chan->do_split) {
1588 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 1587 u32 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
1589 1588
1590 hcsplt |= HCSPLT_SPLTENA; 1589 hcsplt |= HCSPLT_SPLTENA;
1591 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); 1590 dwc2_writel(hsotg, hcsplt, HCSPLT(chan->hc_num));
1592 } 1591 }
1593 1592
1594 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1593 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1595 hcchar &= ~HCCHAR_MULTICNT_MASK; 1594 hcchar &= ~HCCHAR_MULTICNT_MASK;
1596 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK; 1595 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK;
1597 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1596 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
@@ -1610,7 +1609,7 @@ static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1610 (hcchar & HCCHAR_MULTICNT_MASK) >> 1609 (hcchar & HCCHAR_MULTICNT_MASK) >>
1611 HCCHAR_MULTICNT_SHIFT); 1610 HCCHAR_MULTICNT_SHIFT);
1612 1611
1613 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1612 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1614 if (dbg_hc(chan)) 1613 if (dbg_hc(chan))
1615 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1614 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1616 chan->hc_num); 1615 chan->hc_num);
@@ -1668,18 +1667,18 @@ void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1668 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); 1667 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
1669 } 1668 }
1670 1669
1671 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1670 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1672 1671
1673 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr, 1672 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
1674 chan->desc_list_sz, DMA_TO_DEVICE); 1673 chan->desc_list_sz, DMA_TO_DEVICE);
1675 1674
1676 dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num)); 1675 dwc2_writel(hsotg, chan->desc_list_addr, HCDMA(chan->hc_num));
1677 1676
1678 if (dbg_hc(chan)) 1677 if (dbg_hc(chan))
1679 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n", 1678 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
1680 &chan->desc_list_addr, chan->hc_num); 1679 &chan->desc_list_addr, chan->hc_num);
1681 1680
1682 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1681 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1683 hcchar &= ~HCCHAR_MULTICNT_MASK; 1682 hcchar &= ~HCCHAR_MULTICNT_MASK;
1684 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & 1683 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1685 HCCHAR_MULTICNT_MASK; 1684 HCCHAR_MULTICNT_MASK;
@@ -1698,7 +1697,7 @@ void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1698 (hcchar & HCCHAR_MULTICNT_MASK) >> 1697 (hcchar & HCCHAR_MULTICNT_MASK) >>
1699 HCCHAR_MULTICNT_SHIFT); 1698 HCCHAR_MULTICNT_SHIFT);
1700 1699
1701 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1700 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1702 if (dbg_hc(chan)) 1701 if (dbg_hc(chan))
1703 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1702 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1704 chan->hc_num); 1703 chan->hc_num);
@@ -1755,7 +1754,7 @@ static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1755 * transfer completes, the extra requests for the channel will 1754 * transfer completes, the extra requests for the channel will
1756 * be flushed. 1755 * be flushed.
1757 */ 1756 */
1758 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1757 u32 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1759 1758
1760 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1759 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1761 hcchar |= HCCHAR_CHENA; 1760 hcchar |= HCCHAR_CHENA;
@@ -1763,7 +1762,7 @@ static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1763 if (dbg_hc(chan)) 1762 if (dbg_hc(chan))
1764 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", 1763 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
1765 hcchar); 1764 hcchar);
1766 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1765 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1767 chan->requests++; 1766 chan->requests++;
1768 return 1; 1767 return 1;
1769 } 1768 }
@@ -1773,7 +1772,7 @@ static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1773 if (chan->xfer_count < chan->xfer_len) { 1772 if (chan->xfer_count < chan->xfer_len) {
1774 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1773 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1775 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1774 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1776 u32 hcchar = dwc2_readl(hsotg->regs + 1775 u32 hcchar = dwc2_readl(hsotg,
1777 HCCHAR(chan->hc_num)); 1776 HCCHAR(chan->hc_num));
1778 1777
1779 dwc2_hc_set_even_odd_frame(hsotg, chan, 1778 dwc2_hc_set_even_odd_frame(hsotg, chan,
@@ -1887,7 +1886,7 @@ void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1887 */ 1886 */
1888 hprt0 = dwc2_read_hprt0(hsotg); 1887 hprt0 = dwc2_read_hprt0(hsotg);
1889 hprt0 |= HPRT0_RST; 1888 hprt0 |= HPRT0_RST;
1890 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1889 dwc2_writel(hsotg, hprt0, HPRT0);
1891 } 1890 }
1892 1891
1893 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 1892 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
@@ -1908,11 +1907,11 @@ static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1908 channel = hsotg->hc_ptr_array[i]; 1907 channel = hsotg->hc_ptr_array[i];
1909 if (!list_empty(&channel->hc_list_entry)) 1908 if (!list_empty(&channel->hc_list_entry))
1910 continue; 1909 continue;
1911 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1910 hcchar = dwc2_readl(hsotg, HCCHAR(i));
1912 if (hcchar & HCCHAR_CHENA) { 1911 if (hcchar & HCCHAR_CHENA) {
1913 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 1912 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
1914 hcchar |= HCCHAR_CHDIS; 1913 hcchar |= HCCHAR_CHDIS;
1915 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 1914 dwc2_writel(hsotg, hcchar, HCCHAR(i));
1916 } 1915 }
1917 } 1916 }
1918 } 1917 }
@@ -1921,11 +1920,11 @@ static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1921 channel = hsotg->hc_ptr_array[i]; 1920 channel = hsotg->hc_ptr_array[i];
1922 if (!list_empty(&channel->hc_list_entry)) 1921 if (!list_empty(&channel->hc_list_entry))
1923 continue; 1922 continue;
1924 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1923 hcchar = dwc2_readl(hsotg, HCCHAR(i));
1925 if (hcchar & HCCHAR_CHENA) { 1924 if (hcchar & HCCHAR_CHENA) {
1926 /* Halt the channel */ 1925 /* Halt the channel */
1927 hcchar |= HCCHAR_CHDIS; 1926 hcchar |= HCCHAR_CHDIS;
1928 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 1927 dwc2_writel(hsotg, hcchar, HCCHAR(i));
1929 } 1928 }
1930 1929
1931 dwc2_hc_cleanup(hsotg, channel); 1930 dwc2_hc_cleanup(hsotg, channel);
@@ -1985,11 +1984,11 @@ void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
1985 * interrupt mask and status bits and disabling subsequent host 1984 * interrupt mask and status bits and disabling subsequent host
1986 * channel interrupts. 1985 * channel interrupts.
1987 */ 1986 */
1988 intr = dwc2_readl(hsotg->regs + GINTMSK); 1987 intr = dwc2_readl(hsotg, GINTMSK);
1989 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 1988 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
1990 dwc2_writel(intr, hsotg->regs + GINTMSK); 1989 dwc2_writel(hsotg, intr, GINTMSK);
1991 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 1990 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
1992 dwc2_writel(intr, hsotg->regs + GINTSTS); 1991 dwc2_writel(hsotg, intr, GINTSTS);
1993 1992
1994 /* 1993 /*
1995 * Turn off the vbus power only if the core has transitioned to device 1994 * Turn off the vbus power only if the core has transitioned to device
@@ -1999,7 +1998,7 @@ void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
1999 if (dwc2_is_device_mode(hsotg)) { 1998 if (dwc2_is_device_mode(hsotg)) {
2000 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 1999 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
2001 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 2000 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
2002 dwc2_writel(0, hsotg->regs + HPRT0); 2001 dwc2_writel(hsotg, 0, HPRT0);
2003 } 2002 }
2004 2003
2005 dwc2_disable_host_interrupts(hsotg); 2004 dwc2_disable_host_interrupts(hsotg);
@@ -2027,7 +2026,7 @@ void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
2027 * and won't get any future interrupts to handle the connect. 2026 * and won't get any future interrupts to handle the connect.
2028 */ 2027 */
2029 if (!force) { 2028 if (!force) {
2030 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 2029 hprt0 = dwc2_readl(hsotg, HPRT0);
2031 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS)) 2030 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS))
2032 dwc2_hcd_connect(hsotg); 2031 dwc2_hcd_connect(hsotg);
2033 } 2032 }
@@ -2071,7 +2070,7 @@ void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
2071 2070
2072 /* Turn off the vbus power */ 2071 /* Turn off the vbus power */
2073 dev_dbg(hsotg->dev, "PortPower off\n"); 2072 dev_dbg(hsotg->dev, "PortPower off\n");
2074 dwc2_writel(0, hsotg->regs + HPRT0); 2073 dwc2_writel(hsotg, 0, HPRT0);
2075} 2074}
2076 2075
2077/* Caller must hold driver lock */ 2076/* Caller must hold driver lock */
@@ -2095,7 +2094,7 @@ static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
2095 if ((dev_speed == USB_SPEED_LOW) && 2094 if ((dev_speed == USB_SPEED_LOW) &&
2096 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 2095 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
2097 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 2096 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
2098 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 2097 u32 hprt0 = dwc2_readl(hsotg, HPRT0);
2099 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 2098 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
2100 2099
2101 if (prtspd == HPRT0_SPD_FULL_SPEED) 2100 if (prtspd == HPRT0_SPD_FULL_SPEED)
@@ -2114,7 +2113,7 @@ static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
2114 return retval; 2113 return retval;
2115 } 2114 }
2116 2115
2117 intr_mask = dwc2_readl(hsotg->regs + GINTMSK); 2116 intr_mask = dwc2_readl(hsotg, GINTMSK);
2118 if (!(intr_mask & GINTSTS_SOF)) { 2117 if (!(intr_mask & GINTSTS_SOF)) {
2119 enum dwc2_transaction_type tr_type; 2118 enum dwc2_transaction_type tr_type;
2120 2119
@@ -2279,7 +2278,7 @@ int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2279 2278
2280 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 2279 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2281 2280
2282 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 2281 usbcfg = dwc2_readl(hsotg, GUSBCFG);
2283 2282
2284 /* Set ULPI External VBUS bit if needed */ 2283 /* Set ULPI External VBUS bit if needed */
2285 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; 2284 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
@@ -2291,7 +2290,7 @@ int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2291 if (hsotg->params.ts_dline) 2290 if (hsotg->params.ts_dline)
2292 usbcfg |= GUSBCFG_TERMSELDLPULSE; 2291 usbcfg |= GUSBCFG_TERMSELDLPULSE;
2293 2292
2294 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 2293 dwc2_writel(hsotg, usbcfg, GUSBCFG);
2295 2294
2296 /* 2295 /*
2297 * Reset the Controller 2296 * Reset the Controller
@@ -2325,9 +2324,9 @@ int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2325 dwc2_gusbcfg_init(hsotg); 2324 dwc2_gusbcfg_init(hsotg);
2326 2325
2327 /* Program the GOTGCTL register */ 2326 /* Program the GOTGCTL register */
2328 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2327 otgctl = dwc2_readl(hsotg, GOTGCTL);
2329 otgctl &= ~GOTGCTL_OTGVER; 2328 otgctl &= ~GOTGCTL_OTGVER;
2330 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2329 dwc2_writel(hsotg, otgctl, GOTGCTL);
2331 2330
2332 /* Clear the SRP success bit for FS-I2c */ 2331 /* Clear the SRP success bit for FS-I2c */
2333 hsotg->srp_success = 0; 2332 hsotg->srp_success = 0;
@@ -2374,20 +2373,20 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2374 * introduced by the PHY in generating the linestate condition 2373 * introduced by the PHY in generating the linestate condition
2375 * can vary from one PHY to another. 2374 * can vary from one PHY to another.
2376 */ 2375 */
2377 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 2376 usbcfg = dwc2_readl(hsotg, GUSBCFG);
2378 usbcfg |= GUSBCFG_TOUTCAL(7); 2377 usbcfg |= GUSBCFG_TOUTCAL(7);
2379 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 2378 dwc2_writel(hsotg, usbcfg, GUSBCFG);
2380 2379
2381 /* Restart the Phy Clock */ 2380 /* Restart the Phy Clock */
2382 dwc2_writel(0, hsotg->regs + PCGCTL); 2381 dwc2_writel(hsotg, 0, PCGCTL);
2383 2382
2384 /* Initialize Host Configuration Register */ 2383 /* Initialize Host Configuration Register */
2385 dwc2_init_fs_ls_pclk_sel(hsotg); 2384 dwc2_init_fs_ls_pclk_sel(hsotg);
2386 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || 2385 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
2387 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) { 2386 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {
2388 hcfg = dwc2_readl(hsotg->regs + HCFG); 2387 hcfg = dwc2_readl(hsotg, HCFG);
2389 hcfg |= HCFG_FSLSSUPP; 2388 hcfg |= HCFG_FSLSSUPP;
2390 dwc2_writel(hcfg, hsotg->regs + HCFG); 2389 dwc2_writel(hsotg, hcfg, HCFG);
2391 } 2390 }
2392 2391
2393 /* 2392 /*
@@ -2396,9 +2395,9 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2396 * and its value must not be changed during runtime. 2395 * and its value must not be changed during runtime.
2397 */ 2396 */
2398 if (hsotg->params.reload_ctl) { 2397 if (hsotg->params.reload_ctl) {
2399 hfir = dwc2_readl(hsotg->regs + HFIR); 2398 hfir = dwc2_readl(hsotg, HFIR);
2400 hfir |= HFIR_RLDCTRL; 2399 hfir |= HFIR_RLDCTRL;
2401 dwc2_writel(hfir, hsotg->regs + HFIR); 2400 dwc2_writel(hsotg, hfir, HFIR);
2402 } 2401 }
2403 2402
2404 if (hsotg->params.dma_desc_enable) { 2403 if (hsotg->params.dma_desc_enable) {
@@ -2415,9 +2414,9 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2415 "falling back to buffer DMA mode.\n"); 2414 "falling back to buffer DMA mode.\n");
2416 hsotg->params.dma_desc_enable = false; 2415 hsotg->params.dma_desc_enable = false;
2417 } else { 2416 } else {
2418 hcfg = dwc2_readl(hsotg->regs + HCFG); 2417 hcfg = dwc2_readl(hsotg, HCFG);
2419 hcfg |= HCFG_DESCDMA; 2418 hcfg |= HCFG_DESCDMA;
2420 dwc2_writel(hcfg, hsotg->regs + HCFG); 2419 dwc2_writel(hsotg, hcfg, HCFG);
2421 } 2420 }
2422 } 2421 }
2423 2422
@@ -2426,18 +2425,18 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2426 2425
2427 /* TODO - check this */ 2426 /* TODO - check this */
2428 /* Clear Host Set HNP Enable in the OTG Control Register */ 2427 /* Clear Host Set HNP Enable in the OTG Control Register */
2429 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2428 otgctl = dwc2_readl(hsotg, GOTGCTL);
2430 otgctl &= ~GOTGCTL_HSTSETHNPEN; 2429 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2431 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2430 dwc2_writel(hsotg, otgctl, GOTGCTL);
2432 2431
2433 /* Make sure the FIFOs are flushed */ 2432 /* Make sure the FIFOs are flushed */
2434 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); 2433 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
2435 dwc2_flush_rx_fifo(hsotg); 2434 dwc2_flush_rx_fifo(hsotg);
2436 2435
2437 /* Clear Host Set HNP Enable in the OTG Control Register */ 2436 /* Clear Host Set HNP Enable in the OTG Control Register */
2438 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2437 otgctl = dwc2_readl(hsotg, GOTGCTL);
2439 otgctl &= ~GOTGCTL_HSTSETHNPEN; 2438 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2440 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2439 dwc2_writel(hsotg, otgctl, GOTGCTL);
2441 2440
2442 if (!hsotg->params.dma_desc_enable) { 2441 if (!hsotg->params.dma_desc_enable) {
2443 int num_channels, i; 2442 int num_channels, i;
@@ -2446,19 +2445,19 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2446 /* Flush out any leftover queued requests */ 2445 /* Flush out any leftover queued requests */
2447 num_channels = hsotg->params.host_channels; 2446 num_channels = hsotg->params.host_channels;
2448 for (i = 0; i < num_channels; i++) { 2447 for (i = 0; i < num_channels; i++) {
2449 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2448 hcchar = dwc2_readl(hsotg, HCCHAR(i));
2450 hcchar &= ~HCCHAR_CHENA; 2449 hcchar &= ~HCCHAR_CHENA;
2451 hcchar |= HCCHAR_CHDIS; 2450 hcchar |= HCCHAR_CHDIS;
2452 hcchar &= ~HCCHAR_EPDIR; 2451 hcchar &= ~HCCHAR_EPDIR;
2453 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 2452 dwc2_writel(hsotg, hcchar, HCCHAR(i));
2454 } 2453 }
2455 2454
2456 /* Halt all channels to put them into a known state */ 2455 /* Halt all channels to put them into a known state */
2457 for (i = 0; i < num_channels; i++) { 2456 for (i = 0; i < num_channels; i++) {
2458 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2457 hcchar = dwc2_readl(hsotg, HCCHAR(i));
2459 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; 2458 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
2460 hcchar &= ~HCCHAR_EPDIR; 2459 hcchar &= ~HCCHAR_EPDIR;
2461 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 2460 dwc2_writel(hsotg, hcchar, HCCHAR(i));
2462 dev_dbg(hsotg->dev, "%s: Halt channel %d\n", 2461 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2463 __func__, i); 2462 __func__, i);
2464 2463
@@ -2482,7 +2481,7 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2482 !!(hprt0 & HPRT0_PWR)); 2481 !!(hprt0 & HPRT0_PWR));
2483 if (!(hprt0 & HPRT0_PWR)) { 2482 if (!(hprt0 & HPRT0_PWR)) {
2484 hprt0 |= HPRT0_PWR; 2483 hprt0 |= HPRT0_PWR;
2485 dwc2_writel(hprt0, hsotg->regs + HPRT0); 2484 dwc2_writel(hsotg, hprt0, HPRT0);
2486 } 2485 }
2487 } 2486 }
2488 2487
@@ -3084,7 +3083,7 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
3084 if (dbg_perio()) 3083 if (dbg_perio())
3085 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 3084 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
3086 3085
3087 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 3086 tx_status = dwc2_readl(hsotg, HPTXSTS);
3088 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3087 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3089 TXSTS_QSPCAVAIL_SHIFT; 3088 TXSTS_QSPCAVAIL_SHIFT;
3090 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3089 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
@@ -3099,7 +3098,7 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
3099 3098
3100 qh_ptr = hsotg->periodic_sched_assigned.next; 3099 qh_ptr = hsotg->periodic_sched_assigned.next;
3101 while (qh_ptr != &hsotg->periodic_sched_assigned) { 3100 while (qh_ptr != &hsotg->periodic_sched_assigned) {
3102 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 3101 tx_status = dwc2_readl(hsotg, HPTXSTS);
3103 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3102 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3104 TXSTS_QSPCAVAIL_SHIFT; 3103 TXSTS_QSPCAVAIL_SHIFT;
3105 if (qspcavail == 0) { 3104 if (qspcavail == 0) {
@@ -3169,10 +3168,10 @@ exit:
3169 * level to ensure that new requests are loaded as 3168 * level to ensure that new requests are loaded as
3170 * soon as possible.) 3169 * soon as possible.)
3171 */ 3170 */
3172 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3171 gintmsk = dwc2_readl(hsotg, GINTMSK);
3173 if (!(gintmsk & GINTSTS_PTXFEMP)) { 3172 if (!(gintmsk & GINTSTS_PTXFEMP)) {
3174 gintmsk |= GINTSTS_PTXFEMP; 3173 gintmsk |= GINTSTS_PTXFEMP;
3175 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3174 dwc2_writel(hsotg, gintmsk, GINTMSK);
3176 } 3175 }
3177 } else { 3176 } else {
3178 /* 3177 /*
@@ -3182,10 +3181,10 @@ exit:
3182 * handlers to queue more transactions as transfer 3181 * handlers to queue more transactions as transfer
3183 * states change. 3182 * states change.
3184 */ 3183 */
3185 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3184 gintmsk = dwc2_readl(hsotg, GINTMSK);
3186 if (gintmsk & GINTSTS_PTXFEMP) { 3185 if (gintmsk & GINTSTS_PTXFEMP) {
3187 gintmsk &= ~GINTSTS_PTXFEMP; 3186 gintmsk &= ~GINTSTS_PTXFEMP;
3188 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3187 dwc2_writel(hsotg, gintmsk, GINTMSK);
3189 } 3188 }
3190 } 3189 }
3191} 3190}
@@ -3214,7 +3213,7 @@ static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
3214 3213
3215 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 3214 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
3216 3215
3217 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3216 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3218 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3217 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3219 TXSTS_QSPCAVAIL_SHIFT; 3218 TXSTS_QSPCAVAIL_SHIFT;
3220 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3219 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
@@ -3237,7 +3236,7 @@ static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
3237 * available in the request queue or the Tx FIFO 3236 * available in the request queue or the Tx FIFO
3238 */ 3237 */
3239 do { 3238 do {
3240 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3239 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3241 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3240 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3242 TXSTS_QSPCAVAIL_SHIFT; 3241 TXSTS_QSPCAVAIL_SHIFT;
3243 if (!hsotg->params.host_dma && qspcavail == 0) { 3242 if (!hsotg->params.host_dma && qspcavail == 0) {
@@ -3274,7 +3273,7 @@ next:
3274 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 3273 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
3275 3274
3276 if (!hsotg->params.host_dma) { 3275 if (!hsotg->params.host_dma) {
3277 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3276 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3278 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3277 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3279 TXSTS_QSPCAVAIL_SHIFT; 3278 TXSTS_QSPCAVAIL_SHIFT;
3280 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3279 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
@@ -3294,9 +3293,9 @@ next:
3294 * level to ensure that new requests are loaded as 3293 * level to ensure that new requests are loaded as
3295 * soon as possible.) 3294 * soon as possible.)
3296 */ 3295 */
3297 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3296 gintmsk = dwc2_readl(hsotg, GINTMSK);
3298 gintmsk |= GINTSTS_NPTXFEMP; 3297 gintmsk |= GINTSTS_NPTXFEMP;
3299 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3298 dwc2_writel(hsotg, gintmsk, GINTMSK);
3300 } else { 3299 } else {
3301 /* 3300 /*
3302 * Disable the Tx FIFO empty interrupt since there are 3301 * Disable the Tx FIFO empty interrupt since there are
@@ -3305,9 +3304,9 @@ next:
3305 * handlers to queue more transactions as transfer 3304 * handlers to queue more transactions as transfer
3306 * states change. 3305 * states change.
3307 */ 3306 */
3308 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3307 gintmsk = dwc2_readl(hsotg, GINTMSK);
3309 gintmsk &= ~GINTSTS_NPTXFEMP; 3308 gintmsk &= ~GINTSTS_NPTXFEMP;
3310 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3309 dwc2_writel(hsotg, gintmsk, GINTMSK);
3311 } 3310 }
3312 } 3311 }
3313} 3312}
@@ -3344,10 +3343,10 @@ void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
3344 * Ensure NP Tx FIFO empty interrupt is disabled when 3343 * Ensure NP Tx FIFO empty interrupt is disabled when
3345 * there are no non-periodic transfers to process 3344 * there are no non-periodic transfers to process
3346 */ 3345 */
3347 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3346 u32 gintmsk = dwc2_readl(hsotg, GINTMSK);
3348 3347
3349 gintmsk &= ~GINTSTS_NPTXFEMP; 3348 gintmsk &= ~GINTSTS_NPTXFEMP;
3350 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3349 dwc2_writel(hsotg, gintmsk, GINTMSK);
3351 } 3350 }
3352 } 3351 }
3353} 3352}
@@ -3362,7 +3361,7 @@ static void dwc2_conn_id_status_change(struct work_struct *work)
3362 3361
3363 dev_dbg(hsotg->dev, "%s()\n", __func__); 3362 dev_dbg(hsotg->dev, "%s()\n", __func__);
3364 3363
3365 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3364 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3366 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 3365 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
3367 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 3366 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
3368 !!(gotgctl & GOTGCTL_CONID_B)); 3367 !!(gotgctl & GOTGCTL_CONID_B));
@@ -3388,7 +3387,7 @@ static void dwc2_conn_id_status_change(struct work_struct *work)
3388 * check it again and jump to host mode if that was 3387 * check it again and jump to host mode if that was
3389 * the case. 3388 * the case.
3390 */ 3389 */
3391 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3390 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3392 if (!(gotgctl & GOTGCTL_CONID_B)) 3391 if (!(gotgctl & GOTGCTL_CONID_B))
3393 goto host; 3392 goto host;
3394 if (++count > 250) 3393 if (++count > 250)
@@ -3448,9 +3447,9 @@ static void dwc2_wakeup_detected(struct timer_list *t)
3448 hprt0 = dwc2_read_hprt0(hsotg); 3447 hprt0 = dwc2_read_hprt0(hsotg);
3449 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 3448 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
3450 hprt0 &= ~HPRT0_RES; 3449 hprt0 &= ~HPRT0_RES;
3451 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3450 dwc2_writel(hsotg, hprt0, HPRT0);
3452 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 3451 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
3453 dwc2_readl(hsotg->regs + HPRT0)); 3452 dwc2_readl(hsotg, HPRT0));
3454 3453
3455 dwc2_hcd_rem_wakeup(hsotg); 3454 dwc2_hcd_rem_wakeup(hsotg);
3456 hsotg->bus_suspended = false; 3455 hsotg->bus_suspended = false;
@@ -3479,15 +3478,15 @@ static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3479 spin_lock_irqsave(&hsotg->lock, flags); 3478 spin_lock_irqsave(&hsotg->lock, flags);
3480 3479
3481 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 3480 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
3482 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3481 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3483 gotgctl |= GOTGCTL_HSTSETHNPEN; 3482 gotgctl |= GOTGCTL_HSTSETHNPEN;
3484 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); 3483 dwc2_writel(hsotg, gotgctl, GOTGCTL);
3485 hsotg->op_state = OTG_STATE_A_SUSPEND; 3484 hsotg->op_state = OTG_STATE_A_SUSPEND;
3486 } 3485 }
3487 3486
3488 hprt0 = dwc2_read_hprt0(hsotg); 3487 hprt0 = dwc2_read_hprt0(hsotg);
3489 hprt0 |= HPRT0_SUSP; 3488 hprt0 |= HPRT0_SUSP;
3490 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3489 dwc2_writel(hsotg, hprt0, HPRT0);
3491 3490
3492 hsotg->bus_suspended = true; 3491 hsotg->bus_suspended = true;
3493 3492
@@ -3497,17 +3496,17 @@ static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3497 */ 3496 */
3498 if (!hsotg->params.power_down) { 3497 if (!hsotg->params.power_down) {
3499 /* Suspend the Phy Clock */ 3498 /* Suspend the Phy Clock */
3500 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3499 pcgctl = dwc2_readl(hsotg, PCGCTL);
3501 pcgctl |= PCGCTL_STOPPCLK; 3500 pcgctl |= PCGCTL_STOPPCLK;
3502 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3501 dwc2_writel(hsotg, pcgctl, PCGCTL);
3503 udelay(10); 3502 udelay(10);
3504 } 3503 }
3505 3504
3506 /* For HNP the bus must be suspended for at least 200ms */ 3505 /* For HNP the bus must be suspended for at least 200ms */
3507 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 3506 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
3508 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3507 pcgctl = dwc2_readl(hsotg, PCGCTL);
3509 pcgctl &= ~PCGCTL_STOPPCLK; 3508 pcgctl &= ~PCGCTL_STOPPCLK;
3510 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3509 dwc2_writel(hsotg, pcgctl, PCGCTL);
3511 3510
3512 spin_unlock_irqrestore(&hsotg->lock, flags); 3511 spin_unlock_irqrestore(&hsotg->lock, flags);
3513 3512
@@ -3531,9 +3530,9 @@ static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3531 * after registers restore. 3530 * after registers restore.
3532 */ 3531 */
3533 if (!hsotg->params.power_down) { 3532 if (!hsotg->params.power_down) {
3534 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3533 pcgctl = dwc2_readl(hsotg, PCGCTL);
3535 pcgctl &= ~PCGCTL_STOPPCLK; 3534 pcgctl &= ~PCGCTL_STOPPCLK;
3536 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3535 dwc2_writel(hsotg, pcgctl, PCGCTL);
3537 spin_unlock_irqrestore(&hsotg->lock, flags); 3536 spin_unlock_irqrestore(&hsotg->lock, flags);
3538 msleep(20); 3537 msleep(20);
3539 spin_lock_irqsave(&hsotg->lock, flags); 3538 spin_lock_irqsave(&hsotg->lock, flags);
@@ -3542,7 +3541,7 @@ static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3542 hprt0 = dwc2_read_hprt0(hsotg); 3541 hprt0 = dwc2_read_hprt0(hsotg);
3543 hprt0 |= HPRT0_RES; 3542 hprt0 |= HPRT0_RES;
3544 hprt0 &= ~HPRT0_SUSP; 3543 hprt0 &= ~HPRT0_SUSP;
3545 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3544 dwc2_writel(hsotg, hprt0, HPRT0);
3546 spin_unlock_irqrestore(&hsotg->lock, flags); 3545 spin_unlock_irqrestore(&hsotg->lock, flags);
3547 3546
3548 msleep(USB_RESUME_TIMEOUT); 3547 msleep(USB_RESUME_TIMEOUT);
@@ -3550,7 +3549,7 @@ static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3550 spin_lock_irqsave(&hsotg->lock, flags); 3549 spin_lock_irqsave(&hsotg->lock, flags);
3551 hprt0 = dwc2_read_hprt0(hsotg); 3550 hprt0 = dwc2_read_hprt0(hsotg);
3552 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP); 3551 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
3553 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3552 dwc2_writel(hsotg, hprt0, HPRT0);
3554 hsotg->bus_suspended = false; 3553 hsotg->bus_suspended = false;
3555 spin_unlock_irqrestore(&hsotg->lock, flags); 3554 spin_unlock_irqrestore(&hsotg->lock, flags);
3556} 3555}
@@ -3594,7 +3593,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3594 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 3593 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
3595 hprt0 = dwc2_read_hprt0(hsotg); 3594 hprt0 = dwc2_read_hprt0(hsotg);
3596 hprt0 |= HPRT0_ENA; 3595 hprt0 |= HPRT0_ENA;
3597 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3596 dwc2_writel(hsotg, hprt0, HPRT0);
3598 break; 3597 break;
3599 3598
3600 case USB_PORT_FEAT_SUSPEND: 3599 case USB_PORT_FEAT_SUSPEND:
@@ -3614,7 +3613,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3614 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 3613 "ClearPortFeature USB_PORT_FEAT_POWER\n");
3615 hprt0 = dwc2_read_hprt0(hsotg); 3614 hprt0 = dwc2_read_hprt0(hsotg);
3616 hprt0 &= ~HPRT0_PWR; 3615 hprt0 &= ~HPRT0_PWR;
3617 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3616 dwc2_writel(hsotg, hprt0, HPRT0);
3618 break; 3617 break;
3619 3618
3620 case USB_PORT_FEAT_INDICATOR: 3619 case USB_PORT_FEAT_INDICATOR:
@@ -3735,7 +3734,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3735 break; 3734 break;
3736 } 3735 }
3737 3736
3738 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 3737 hprt0 = dwc2_readl(hsotg, HPRT0);
3739 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 3738 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
3740 3739
3741 if (hprt0 & HPRT0_CONNSTS) 3740 if (hprt0 & HPRT0_CONNSTS)
@@ -3776,9 +3775,9 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3776 3775
3777 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n"); 3776 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
3778 hsotg->params.dma_desc_enable = true; 3777 hsotg->params.dma_desc_enable = true;
3779 hcfg = dwc2_readl(hsotg->regs + HCFG); 3778 hcfg = dwc2_readl(hsotg, HCFG);
3780 hcfg |= HCFG_DESCDMA; 3779 hcfg |= HCFG_DESCDMA;
3781 dwc2_writel(hcfg, hsotg->regs + HCFG); 3780 dwc2_writel(hsotg, hcfg, HCFG);
3782 hsotg->new_connection = false; 3781 hsotg->new_connection = false;
3783 } 3782 }
3784 } 3783 }
@@ -3825,7 +3824,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3825 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 3824 "SetPortFeature - USB_PORT_FEAT_POWER\n");
3826 hprt0 = dwc2_read_hprt0(hsotg); 3825 hprt0 = dwc2_read_hprt0(hsotg);
3827 hprt0 |= HPRT0_PWR; 3826 hprt0 |= HPRT0_PWR;
3828 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3827 dwc2_writel(hsotg, hprt0, HPRT0);
3829 break; 3828 break;
3830 3829
3831 case USB_PORT_FEAT_RESET: 3830 case USB_PORT_FEAT_RESET:
@@ -3835,11 +3834,11 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3835 hprt0 = dwc2_read_hprt0(hsotg); 3834 hprt0 = dwc2_read_hprt0(hsotg);
3836 dev_dbg(hsotg->dev, 3835 dev_dbg(hsotg->dev,
3837 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 3836 "SetPortFeature - USB_PORT_FEAT_RESET\n");
3838 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3837 pcgctl = dwc2_readl(hsotg, PCGCTL);
3839 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 3838 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
3840 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3839 dwc2_writel(hsotg, pcgctl, PCGCTL);
3841 /* ??? Original driver does this */ 3840 /* ??? Original driver does this */
3842 dwc2_writel(0, hsotg->regs + PCGCTL); 3841 dwc2_writel(hsotg, 0, PCGCTL);
3843 3842
3844 hprt0 = dwc2_read_hprt0(hsotg); 3843 hprt0 = dwc2_read_hprt0(hsotg);
3845 /* Clear suspend bit if resetting from suspend state */ 3844 /* Clear suspend bit if resetting from suspend state */
@@ -3854,13 +3853,13 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3854 hprt0 |= HPRT0_PWR | HPRT0_RST; 3853 hprt0 |= HPRT0_PWR | HPRT0_RST;
3855 dev_dbg(hsotg->dev, 3854 dev_dbg(hsotg->dev,
3856 "In host mode, hprt0=%08x\n", hprt0); 3855 "In host mode, hprt0=%08x\n", hprt0);
3857 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3856 dwc2_writel(hsotg, hprt0, HPRT0);
3858 } 3857 }
3859 3858
3860 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 3859 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
3861 msleep(50); 3860 msleep(50);
3862 hprt0 &= ~HPRT0_RST; 3861 hprt0 &= ~HPRT0_RST;
3863 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3862 dwc2_writel(hsotg, hprt0, HPRT0);
3864 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 3863 hsotg->lx_state = DWC2_L0; /* Now back to On state */
3865 break; 3864 break;
3866 3865
@@ -3876,7 +3875,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3876 "SetPortFeature - USB_PORT_FEAT_TEST\n"); 3875 "SetPortFeature - USB_PORT_FEAT_TEST\n");
3877 hprt0 &= ~HPRT0_TSTCTL_MASK; 3876 hprt0 &= ~HPRT0_TSTCTL_MASK;
3878 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; 3877 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
3879 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3878 dwc2_writel(hsotg, hprt0, HPRT0);
3880 break; 3879 break;
3881 3880
3882 default: 3881 default:
@@ -3933,7 +3932,7 @@ static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
3933 3932
3934int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 3933int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3935{ 3934{
3936 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3935 u32 hfnum = dwc2_readl(hsotg, HFNUM);
3937 3936
3938#ifdef DWC2_DEBUG_SOF 3937#ifdef DWC2_DEBUG_SOF
3939 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 3938 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
@@ -3944,9 +3943,9 @@ int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3944 3943
3945int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us) 3944int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us)
3946{ 3945{
3947 u32 hprt = dwc2_readl(hsotg->regs + HPRT0); 3946 u32 hprt = dwc2_readl(hsotg, HPRT0);
3948 u32 hfir = dwc2_readl(hsotg->regs + HFIR); 3947 u32 hfir = dwc2_readl(hsotg, HFIR);
3949 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3948 u32 hfnum = dwc2_readl(hsotg, HFNUM);
3950 unsigned int us_per_frame; 3949 unsigned int us_per_frame;
3951 unsigned int frame_number; 3950 unsigned int frame_number;
3952 unsigned int remaining; 3951 unsigned int remaining;
@@ -4065,11 +4064,11 @@ void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
4065 if (chan->xfer_started) { 4064 if (chan->xfer_started) {
4066 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; 4065 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
4067 4066
4068 hfnum = dwc2_readl(hsotg->regs + HFNUM); 4067 hfnum = dwc2_readl(hsotg, HFNUM);
4069 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 4068 hcchar = dwc2_readl(hsotg, HCCHAR(i));
4070 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i)); 4069 hctsiz = dwc2_readl(hsotg, HCTSIZ(i));
4071 hcint = dwc2_readl(hsotg->regs + HCINT(i)); 4070 hcint = dwc2_readl(hsotg, HCINT(i));
4072 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i)); 4071 hcintmsk = dwc2_readl(hsotg, HCINTMSK(i));
4073 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); 4072 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
4074 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); 4073 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
4075 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); 4074 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
@@ -4117,12 +4116,12 @@ void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
4117 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 4116 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
4118 hsotg->periodic_channels); 4117 hsotg->periodic_channels);
4119 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 4118 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
4120 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 4119 np_tx_status = dwc2_readl(hsotg, GNPTXSTS);
4121 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 4120 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
4122 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 4121 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
4123 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 4122 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
4124 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 4123 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
4125 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 4124 p_tx_status = dwc2_readl(hsotg, HPTXSTS);
4126 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 4125 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
4127 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 4126 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
4128 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 4127 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
@@ -4372,7 +4371,7 @@ static void dwc2_hcd_reset_func(struct work_struct *work)
4372 4371
4373 hprt0 = dwc2_read_hprt0(hsotg); 4372 hprt0 = dwc2_read_hprt0(hsotg);
4374 hprt0 &= ~HPRT0_RST; 4373 hprt0 &= ~HPRT0_RST;
4375 dwc2_writel(hprt0, hsotg->regs + HPRT0); 4374 dwc2_writel(hsotg, hprt0, HPRT0);
4376 hsotg->flags.b.port_reset_change = 1; 4375 hsotg->flags.b.port_reset_change = 1;
4377 4376
4378 spin_unlock_irqrestore(&hsotg->lock, flags); 4377 spin_unlock_irqrestore(&hsotg->lock, flags);
@@ -4482,7 +4481,7 @@ static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
4482 hprt0 = dwc2_read_hprt0(hsotg); 4481 hprt0 = dwc2_read_hprt0(hsotg);
4483 hprt0 |= HPRT0_SUSP; 4482 hprt0 |= HPRT0_SUSP;
4484 hprt0 &= ~HPRT0_PWR; 4483 hprt0 &= ~HPRT0_PWR;
4485 dwc2_writel(hprt0, hsotg->regs + HPRT0); 4484 dwc2_writel(hsotg, hprt0, HPRT0);
4486 dwc2_vbus_supply_exit(hsotg); 4485 dwc2_vbus_supply_exit(hsotg);
4487 } 4486 }
4488 4487
@@ -4573,8 +4572,8 @@ static int _dwc2_hcd_resume(struct usb_hcd *hcd)
4573 * Clear Port Enable and Port Status changes. 4572 * Clear Port Enable and Port Status changes.
4574 * Enable Port Power. 4573 * Enable Port Power.
4575 */ 4574 */
4576 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET | 4575 dwc2_writel(hsotg, HPRT0_PWR | HPRT0_CONNDET |
4577 HPRT0_ENACHG, hsotg->regs + HPRT0); 4576 HPRT0_ENACHG, HPRT0);
4578 /* Wait for controller to detect Port Connect */ 4577 /* Wait for controller to detect Port Connect */
4579 usleep_range(5000, 7000); 4578 usleep_range(5000, 7000);
4580 } 4579 }
@@ -5094,17 +5093,17 @@ static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
5094 hsotg->status_buf = NULL; 5093 hsotg->status_buf = NULL;
5095 } 5094 }
5096 5095
5097 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 5096 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
5098 5097
5099 /* Disable all interrupts */ 5098 /* Disable all interrupts */
5100 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 5099 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
5101 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 5100 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
5102 dwc2_writel(0, hsotg->regs + GINTMSK); 5101 dwc2_writel(hsotg, 0, GINTMSK);
5103 5102
5104 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 5103 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
5105 dctl = dwc2_readl(hsotg->regs + DCTL); 5104 dctl = dwc2_readl(hsotg, DCTL);
5106 dctl |= DCTL_SFTDISCON; 5105 dctl |= DCTL_SFTDISCON;
5107 dwc2_writel(dctl, hsotg->regs + DCTL); 5106 dwc2_writel(hsotg, dctl, DCTL);
5108 } 5107 }
5109 5108
5110 if (hsotg->wq_otg) { 5109 if (hsotg->wq_otg) {
@@ -5147,7 +5146,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
5147 5146
5148 retval = -ENOMEM; 5147 retval = -ENOMEM;
5149 5148
5150 hcfg = dwc2_readl(hsotg->regs + HCFG); 5149 hcfg = dwc2_readl(hsotg, HCFG);
5151 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); 5150 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
5152 5151
5153#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5152#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
@@ -5437,14 +5436,14 @@ int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
5437 5436
5438 /* Backup Host regs */ 5437 /* Backup Host regs */
5439 hr = &hsotg->hr_backup; 5438 hr = &hsotg->hr_backup;
5440 hr->hcfg = dwc2_readl(hsotg->regs + HCFG); 5439 hr->hcfg = dwc2_readl(hsotg, HCFG);
5441 hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK); 5440 hr->haintmsk = dwc2_readl(hsotg, HAINTMSK);
5442 for (i = 0; i < hsotg->params.host_channels; ++i) 5441 for (i = 0; i < hsotg->params.host_channels; ++i)
5443 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i)); 5442 hr->hcintmsk[i] = dwc2_readl(hsotg, HCINTMSK(i));
5444 5443
5445 hr->hprt0 = dwc2_read_hprt0(hsotg); 5444 hr->hprt0 = dwc2_read_hprt0(hsotg);
5446 hr->hfir = dwc2_readl(hsotg->regs + HFIR); 5445 hr->hfir = dwc2_readl(hsotg, HFIR);
5447 hr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); 5446 hr->hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
5448 hr->valid = true; 5447 hr->valid = true;
5449 5448
5450 return 0; 5449 return 0;
@@ -5473,15 +5472,15 @@ int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
5473 } 5472 }
5474 hr->valid = false; 5473 hr->valid = false;
5475 5474
5476 dwc2_writel(hr->hcfg, hsotg->regs + HCFG); 5475 dwc2_writel(hsotg, hr->hcfg, HCFG);
5477 dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK); 5476 dwc2_writel(hsotg, hr->haintmsk, HAINTMSK);
5478 5477
5479 for (i = 0; i < hsotg->params.host_channels; ++i) 5478 for (i = 0; i < hsotg->params.host_channels; ++i)
5480 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i)); 5479 dwc2_writel(hsotg, hr->hcintmsk[i], HCINTMSK(i));
5481 5480
5482 dwc2_writel(hr->hprt0, hsotg->regs + HPRT0); 5481 dwc2_writel(hsotg, hr->hprt0, HPRT0);
5483 dwc2_writel(hr->hfir, hsotg->regs + HFIR); 5482 dwc2_writel(hsotg, hr->hfir, HFIR);
5484 dwc2_writel(hr->hptxfsiz, hsotg->regs + HPTXFSIZ); 5483 dwc2_writel(hsotg, hr->hptxfsiz, HPTXFSIZ);
5485 hsotg->frame_number = 0; 5484 hsotg->frame_number = 0;
5486 5485
5487 return 0; 5486 return 0;
@@ -5516,10 +5515,10 @@ int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
5516 } 5515 }
5517 5516
5518 /* Enter USB Suspend Mode */ 5517 /* Enter USB Suspend Mode */
5519 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 5518 hprt0 = dwc2_readl(hsotg, HPRT0);
5520 hprt0 |= HPRT0_SUSP; 5519 hprt0 |= HPRT0_SUSP;
5521 hprt0 &= ~HPRT0_ENA; 5520 hprt0 &= ~HPRT0_ENA;
5522 dwc2_writel(hprt0, hsotg->regs + HPRT0); 5521 dwc2_writel(hsotg, hprt0, HPRT0);
5523 5522
5524 /* Wait for the HPRT0.PrtSusp register field to be set */ 5523 /* Wait for the HPRT0.PrtSusp register field to be set */
5525 if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 3000)) 5524 if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 3000))
@@ -5532,56 +5531,56 @@ int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
5532 spin_lock_irqsave(&hsotg->lock, flags); 5531 spin_lock_irqsave(&hsotg->lock, flags);
5533 hsotg->lx_state = DWC2_L2; 5532 hsotg->lx_state = DWC2_L2;
5534 5533
5535 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 5534 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
5536 if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) { 5535 if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) {
5537 /* ULPI interface */ 5536 /* ULPI interface */
5538 /* Suspend the Phy Clock */ 5537 /* Suspend the Phy Clock */
5539 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 5538 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5540 pcgcctl |= PCGCTL_STOPPCLK; 5539 pcgcctl |= PCGCTL_STOPPCLK;
5541 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 5540 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5542 udelay(10); 5541 udelay(10);
5543 5542
5544 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5543 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5545 gpwrdn |= GPWRDN_PMUACTV; 5544 gpwrdn |= GPWRDN_PMUACTV;
5546 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5545 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5547 udelay(10); 5546 udelay(10);
5548 } else { 5547 } else {
5549 /* UTMI+ Interface */ 5548 /* UTMI+ Interface */
5550 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5549 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5551 gpwrdn |= GPWRDN_PMUACTV; 5550 gpwrdn |= GPWRDN_PMUACTV;
5552 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5551 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5553 udelay(10); 5552 udelay(10);
5554 5553
5555 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 5554 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5556 pcgcctl |= PCGCTL_STOPPCLK; 5555 pcgcctl |= PCGCTL_STOPPCLK;
5557 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 5556 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5558 udelay(10); 5557 udelay(10);
5559 } 5558 }
5560 5559
5561 /* Enable interrupts from wake up logic */ 5560 /* Enable interrupts from wake up logic */
5562 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5561 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5563 gpwrdn |= GPWRDN_PMUINTSEL; 5562 gpwrdn |= GPWRDN_PMUINTSEL;
5564 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5563 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5565 udelay(10); 5564 udelay(10);
5566 5565
5567 /* Unmask host mode interrupts in GPWRDN */ 5566 /* Unmask host mode interrupts in GPWRDN */
5568 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5567 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5569 gpwrdn |= GPWRDN_DISCONN_DET_MSK; 5568 gpwrdn |= GPWRDN_DISCONN_DET_MSK;
5570 gpwrdn |= GPWRDN_LNSTSCHG_MSK; 5569 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5571 gpwrdn |= GPWRDN_STS_CHGINT_MSK; 5570 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5572 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5571 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5573 udelay(10); 5572 udelay(10);
5574 5573
5575 /* Enable Power Down Clamp */ 5574 /* Enable Power Down Clamp */
5576 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5575 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5577 gpwrdn |= GPWRDN_PWRDNCLMP; 5576 gpwrdn |= GPWRDN_PWRDNCLMP;
5578 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5577 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5579 udelay(10); 5578 udelay(10);
5580 5579
5581 /* Switch off VDD */ 5580 /* Switch off VDD */
5582 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5581 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5583 gpwrdn |= GPWRDN_PWRDNSWTCH; 5582 gpwrdn |= GPWRDN_PWRDNSWTCH;
5584 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5583 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5585 5584
5586 hsotg->hibernated = 1; 5585 hsotg->hibernated = 1;
5587 hsotg->bus_suspended = 1; 5586 hsotg->bus_suspended = 1;
@@ -5629,29 +5628,29 @@ int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
5629 mdelay(100); 5628 mdelay(100);
5630 5629
5631 /* Clear all pending interupts */ 5630 /* Clear all pending interupts */
5632 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 5631 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5633 5632
5634 /* De-assert Restore */ 5633 /* De-assert Restore */
5635 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5634 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5636 gpwrdn &= ~GPWRDN_RESTORE; 5635 gpwrdn &= ~GPWRDN_RESTORE;
5637 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5636 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5638 udelay(10); 5637 udelay(10);
5639 5638
5640 /* Restore GUSBCFG, HCFG */ 5639 /* Restore GUSBCFG, HCFG */
5641 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG); 5640 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5642 dwc2_writel(hr->hcfg, hsotg->regs + HCFG); 5641 dwc2_writel(hsotg, hr->hcfg, HCFG);
5643 5642
5644 /* De-assert Wakeup Logic */ 5643 /* De-assert Wakeup Logic */
5645 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5644 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5646 gpwrdn &= ~GPWRDN_PMUACTV; 5645 gpwrdn &= ~GPWRDN_PMUACTV;
5647 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5646 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5648 udelay(10); 5647 udelay(10);
5649 5648
5650 hprt0 = hr->hprt0; 5649 hprt0 = hr->hprt0;
5651 hprt0 |= HPRT0_PWR; 5650 hprt0 |= HPRT0_PWR;
5652 hprt0 &= ~HPRT0_ENA; 5651 hprt0 &= ~HPRT0_ENA;
5653 hprt0 &= ~HPRT0_SUSP; 5652 hprt0 &= ~HPRT0_SUSP;
5654 dwc2_writel(hprt0, hsotg->regs + HPRT0); 5653 dwc2_writel(hsotg, hprt0, HPRT0);
5655 5654
5656 hprt0 = hr->hprt0; 5655 hprt0 = hr->hprt0;
5657 hprt0 |= HPRT0_PWR; 5656 hprt0 |= HPRT0_PWR;
@@ -5660,32 +5659,32 @@ int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
5660 5659
5661 if (reset) { 5660 if (reset) {
5662 hprt0 |= HPRT0_RST; 5661 hprt0 |= HPRT0_RST;
5663 dwc2_writel(hprt0, hsotg->regs + HPRT0); 5662 dwc2_writel(hsotg, hprt0, HPRT0);
5664 5663
5665 /* Wait for Resume time and then program HPRT again */ 5664 /* Wait for Resume time and then program HPRT again */
5666 mdelay(60); 5665 mdelay(60);
5667 hprt0 &= ~HPRT0_RST; 5666 hprt0 &= ~HPRT0_RST;
5668 dwc2_writel(hprt0, hsotg->regs + HPRT0); 5667 dwc2_writel(hsotg, hprt0, HPRT0);
5669 } else { 5668 } else {
5670 hprt0 |= HPRT0_RES; 5669 hprt0 |= HPRT0_RES;
5671 dwc2_writel(hprt0, hsotg->regs + HPRT0); 5670 dwc2_writel(hsotg, hprt0, HPRT0);
5672 5671
5673 /* Wait for Resume time and then program HPRT again */ 5672 /* Wait for Resume time and then program HPRT again */
5674 mdelay(100); 5673 mdelay(100);
5675 hprt0 &= ~HPRT0_RES; 5674 hprt0 &= ~HPRT0_RES;
5676 dwc2_writel(hprt0, hsotg->regs + HPRT0); 5675 dwc2_writel(hsotg, hprt0, HPRT0);
5677 } 5676 }
5678 /* Clear all interrupt status */ 5677 /* Clear all interrupt status */
5679 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 5678 hprt0 = dwc2_readl(hsotg, HPRT0);
5680 hprt0 |= HPRT0_CONNDET; 5679 hprt0 |= HPRT0_CONNDET;
5681 hprt0 |= HPRT0_ENACHG; 5680 hprt0 |= HPRT0_ENACHG;
5682 hprt0 &= ~HPRT0_ENA; 5681 hprt0 &= ~HPRT0_ENA;
5683 dwc2_writel(hprt0, hsotg->regs + HPRT0); 5682 dwc2_writel(hsotg, hprt0, HPRT0);
5684 5683
5685 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 5684 hprt0 = dwc2_readl(hsotg, HPRT0);
5686 5685
5687 /* Clear all pending interupts */ 5686 /* Clear all pending interupts */
5688 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 5687 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5689 5688
5690 /* Restore global registers */ 5689 /* Restore global registers */
5691 ret = dwc2_restore_global_registers(hsotg); 5690 ret = dwc2_restore_global_registers(hsotg);
diff --git a/drivers/usb/dwc2/hcd.h b/drivers/usb/dwc2/hcd.h
index 5502a501f516..3f9bccc95add 100644
--- a/drivers/usb/dwc2/hcd.h
+++ b/drivers/usb/dwc2/hcd.h
@@ -469,10 +469,10 @@ static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg)
469 */ 469 */
470static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) 470static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr)
471{ 471{
472 u32 mask = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); 472 u32 mask = dwc2_readl(hsotg, HCINTMSK(chnum));
473 473
474 mask &= ~intr; 474 mask &= ~intr;
475 dwc2_writel(mask, hsotg->regs + HCINTMSK(chnum)); 475 dwc2_writel(hsotg, mask, HCINTMSK(chnum));
476} 476}
477 477
478void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 478void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan);
@@ -487,7 +487,7 @@ void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
487 */ 487 */
488static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg) 488static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg)
489{ 489{
490 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 490 u32 hprt0 = dwc2_readl(hsotg, HPRT0);
491 491
492 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG); 492 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG);
493 return hprt0; 493 return hprt0;
@@ -690,8 +690,8 @@ static inline u16 dwc2_micro_frame_num(u16 frame)
690 */ 690 */
691static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg) 691static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg)
692{ 692{
693 return dwc2_readl(hsotg->regs + GINTSTS) & 693 return dwc2_readl(hsotg, GINTSTS) &
694 dwc2_readl(hsotg->regs + GINTMSK); 694 dwc2_readl(hsotg, GINTMSK);
695} 695}
696 696
697static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb) 697static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb)
diff --git a/drivers/usb/dwc2/hcd_ddma.c b/drivers/usb/dwc2/hcd_ddma.c
index 74f11c823f79..a858b5f9c1d6 100644
--- a/drivers/usb/dwc2/hcd_ddma.c
+++ b/drivers/usb/dwc2/hcd_ddma.c
@@ -185,19 +185,19 @@ static void dwc2_per_sched_enable(struct dwc2_hsotg *hsotg, u32 fr_list_en)
185 185
186 spin_lock_irqsave(&hsotg->lock, flags); 186 spin_lock_irqsave(&hsotg->lock, flags);
187 187
188 hcfg = dwc2_readl(hsotg->regs + HCFG); 188 hcfg = dwc2_readl(hsotg, HCFG);
189 if (hcfg & HCFG_PERSCHEDENA) { 189 if (hcfg & HCFG_PERSCHEDENA) {
190 /* already enabled */ 190 /* already enabled */
191 spin_unlock_irqrestore(&hsotg->lock, flags); 191 spin_unlock_irqrestore(&hsotg->lock, flags);
192 return; 192 return;
193 } 193 }
194 194
195 dwc2_writel(hsotg->frame_list_dma, hsotg->regs + HFLBADDR); 195 dwc2_writel(hsotg, hsotg->frame_list_dma, HFLBADDR);
196 196
197 hcfg &= ~HCFG_FRLISTEN_MASK; 197 hcfg &= ~HCFG_FRLISTEN_MASK;
198 hcfg |= fr_list_en | HCFG_PERSCHEDENA; 198 hcfg |= fr_list_en | HCFG_PERSCHEDENA;
199 dev_vdbg(hsotg->dev, "Enabling Periodic schedule\n"); 199 dev_vdbg(hsotg->dev, "Enabling Periodic schedule\n");
200 dwc2_writel(hcfg, hsotg->regs + HCFG); 200 dwc2_writel(hsotg, hcfg, HCFG);
201 201
202 spin_unlock_irqrestore(&hsotg->lock, flags); 202 spin_unlock_irqrestore(&hsotg->lock, flags);
203} 203}
@@ -209,7 +209,7 @@ static void dwc2_per_sched_disable(struct dwc2_hsotg *hsotg)
209 209
210 spin_lock_irqsave(&hsotg->lock, flags); 210 spin_lock_irqsave(&hsotg->lock, flags);
211 211
212 hcfg = dwc2_readl(hsotg->regs + HCFG); 212 hcfg = dwc2_readl(hsotg, HCFG);
213 if (!(hcfg & HCFG_PERSCHEDENA)) { 213 if (!(hcfg & HCFG_PERSCHEDENA)) {
214 /* already disabled */ 214 /* already disabled */
215 spin_unlock_irqrestore(&hsotg->lock, flags); 215 spin_unlock_irqrestore(&hsotg->lock, flags);
@@ -218,7 +218,7 @@ static void dwc2_per_sched_disable(struct dwc2_hsotg *hsotg)
218 218
219 hcfg &= ~HCFG_PERSCHEDENA; 219 hcfg &= ~HCFG_PERSCHEDENA;
220 dev_vdbg(hsotg->dev, "Disabling Periodic schedule\n"); 220 dev_vdbg(hsotg->dev, "Disabling Periodic schedule\n");
221 dwc2_writel(hcfg, hsotg->regs + HCFG); 221 dwc2_writel(hsotg, hcfg, HCFG);
222 222
223 spin_unlock_irqrestore(&hsotg->lock, flags); 223 spin_unlock_irqrestore(&hsotg->lock, flags);
224} 224}
diff --git a/drivers/usb/dwc2/hcd_intr.c b/drivers/usb/dwc2/hcd_intr.c
index 8ce10caf3e19..88b5dcf3aefc 100644
--- a/drivers/usb/dwc2/hcd_intr.c
+++ b/drivers/usb/dwc2/hcd_intr.c
@@ -144,7 +144,7 @@ static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
144 enum dwc2_transaction_type tr_type; 144 enum dwc2_transaction_type tr_type;
145 145
146 /* Clear interrupt */ 146 /* Clear interrupt */
147 dwc2_writel(GINTSTS_SOF, hsotg->regs + GINTSTS); 147 dwc2_writel(hsotg, GINTSTS_SOF, GINTSTS);
148 148
149#ifdef DEBUG_SOF 149#ifdef DEBUG_SOF
150 dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n"); 150 dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
@@ -191,7 +191,7 @@ static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
191 if (dbg_perio()) 191 if (dbg_perio())
192 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n"); 192 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
193 193
194 grxsts = dwc2_readl(hsotg->regs + GRXSTSP); 194 grxsts = dwc2_readl(hsotg, GRXSTSP);
195 chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT; 195 chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT;
196 chan = hsotg->hc_ptr_array[chnum]; 196 chan = hsotg->hc_ptr_array[chnum];
197 if (!chan) { 197 if (!chan) {
@@ -274,11 +274,11 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
274 dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 274 dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
275 275
276 /* Every time when port enables calculate HFIR.FrInterval */ 276 /* Every time when port enables calculate HFIR.FrInterval */
277 hfir = dwc2_readl(hsotg->regs + HFIR); 277 hfir = dwc2_readl(hsotg, HFIR);
278 hfir &= ~HFIR_FRINT_MASK; 278 hfir &= ~HFIR_FRINT_MASK;
279 hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT & 279 hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
280 HFIR_FRINT_MASK; 280 HFIR_FRINT_MASK;
281 dwc2_writel(hfir, hsotg->regs + HFIR); 281 dwc2_writel(hsotg, hfir, HFIR);
282 282
283 /* Check if we need to adjust the PHY clock speed for low power */ 283 /* Check if we need to adjust the PHY clock speed for low power */
284 if (!params->host_support_fs_ls_low_power) { 284 if (!params->host_support_fs_ls_low_power) {
@@ -287,7 +287,7 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
287 return; 287 return;
288 } 288 }
289 289
290 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 290 usbcfg = dwc2_readl(hsotg, GUSBCFG);
291 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 291 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
292 292
293 if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) { 293 if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
@@ -295,11 +295,11 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
295 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) { 295 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
296 /* Set PHY low power clock select for FS/LS devices */ 296 /* Set PHY low power clock select for FS/LS devices */
297 usbcfg |= GUSBCFG_PHY_LP_CLK_SEL; 297 usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
298 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 298 dwc2_writel(hsotg, usbcfg, GUSBCFG);
299 do_reset = 1; 299 do_reset = 1;
300 } 300 }
301 301
302 hcfg = dwc2_readl(hsotg->regs + HCFG); 302 hcfg = dwc2_readl(hsotg, HCFG);
303 fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >> 303 fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
304 HCFG_FSLSPCLKSEL_SHIFT; 304 HCFG_FSLSPCLKSEL_SHIFT;
305 305
@@ -312,7 +312,7 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
312 fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ; 312 fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;
313 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 313 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
314 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT; 314 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
315 dwc2_writel(hcfg, hsotg->regs + HCFG); 315 dwc2_writel(hsotg, hcfg, HCFG);
316 do_reset = 1; 316 do_reset = 1;
317 } 317 }
318 } else { 318 } else {
@@ -323,7 +323,7 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
323 fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ; 323 fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;
324 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 324 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
325 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT; 325 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
326 dwc2_writel(hcfg, hsotg->regs + HCFG); 326 dwc2_writel(hsotg, hcfg, HCFG);
327 do_reset = 1; 327 do_reset = 1;
328 } 328 }
329 } 329 }
@@ -331,14 +331,14 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
331 /* Not low power */ 331 /* Not low power */
332 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) { 332 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
333 usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL; 333 usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
334 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 334 dwc2_writel(hsotg, usbcfg, GUSBCFG);
335 do_reset = 1; 335 do_reset = 1;
336 } 336 }
337 } 337 }
338 338
339 if (do_reset) { 339 if (do_reset) {
340 *hprt0_modify |= HPRT0_RST; 340 *hprt0_modify |= HPRT0_RST;
341 dwc2_writel(*hprt0_modify, hsotg->regs + HPRT0); 341 dwc2_writel(hsotg, *hprt0_modify, HPRT0);
342 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work, 342 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
343 msecs_to_jiffies(60)); 343 msecs_to_jiffies(60));
344 } else { 344 } else {
@@ -359,7 +359,7 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
359 359
360 dev_vdbg(hsotg->dev, "--Port Interrupt--\n"); 360 dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
361 361
362 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 362 hprt0 = dwc2_readl(hsotg, HPRT0);
363 hprt0_modify = hprt0; 363 hprt0_modify = hprt0;
364 364
365 /* 365 /*
@@ -374,7 +374,7 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
374 * Set flag and clear if detected 374 * Set flag and clear if detected
375 */ 375 */
376 if (hprt0 & HPRT0_CONNDET) { 376 if (hprt0 & HPRT0_CONNDET) {
377 dwc2_writel(hprt0_modify | HPRT0_CONNDET, hsotg->regs + HPRT0); 377 dwc2_writel(hsotg, hprt0_modify | HPRT0_CONNDET, HPRT0);
378 378
379 dev_vdbg(hsotg->dev, 379 dev_vdbg(hsotg->dev,
380 "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n", 380 "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n",
@@ -392,7 +392,7 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
392 * Clear if detected - Set internal flag if disabled 392 * Clear if detected - Set internal flag if disabled
393 */ 393 */
394 if (hprt0 & HPRT0_ENACHG) { 394 if (hprt0 & HPRT0_ENACHG) {
395 dwc2_writel(hprt0_modify | HPRT0_ENACHG, hsotg->regs + HPRT0); 395 dwc2_writel(hsotg, hprt0_modify | HPRT0_ENACHG, HPRT0);
396 dev_vdbg(hsotg->dev, 396 dev_vdbg(hsotg->dev,
397 " --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n", 397 " --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n",
398 hprt0, !!(hprt0 & HPRT0_ENA)); 398 hprt0, !!(hprt0 & HPRT0_ENA));
@@ -406,17 +406,17 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
406 406
407 hsotg->params.dma_desc_enable = false; 407 hsotg->params.dma_desc_enable = false;
408 hsotg->new_connection = false; 408 hsotg->new_connection = false;
409 hcfg = dwc2_readl(hsotg->regs + HCFG); 409 hcfg = dwc2_readl(hsotg, HCFG);
410 hcfg &= ~HCFG_DESCDMA; 410 hcfg &= ~HCFG_DESCDMA;
411 dwc2_writel(hcfg, hsotg->regs + HCFG); 411 dwc2_writel(hsotg, hcfg, HCFG);
412 } 412 }
413 } 413 }
414 } 414 }
415 415
416 /* Overcurrent Change Interrupt */ 416 /* Overcurrent Change Interrupt */
417 if (hprt0 & HPRT0_OVRCURRCHG) { 417 if (hprt0 & HPRT0_OVRCURRCHG) {
418 dwc2_writel(hprt0_modify | HPRT0_OVRCURRCHG, 418 dwc2_writel(hsotg, hprt0_modify | HPRT0_OVRCURRCHG,
419 hsotg->regs + HPRT0); 419 HPRT0);
420 dev_vdbg(hsotg->dev, 420 dev_vdbg(hsotg->dev,
421 " --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n", 421 " --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n",
422 hprt0); 422 hprt0);
@@ -441,7 +441,7 @@ static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
441{ 441{
442 u32 hctsiz, count, length; 442 u32 hctsiz, count, length;
443 443
444 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); 444 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
445 445
446 if (halt_status == DWC2_HC_XFER_COMPLETE) { 446 if (halt_status == DWC2_HC_XFER_COMPLETE) {
447 if (chan->ep_is_in) { 447 if (chan->ep_is_in) {
@@ -518,7 +518,7 @@ static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
518 urb->status = 0; 518 urb->status = 0;
519 } 519 }
520 520
521 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); 521 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
522 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", 522 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
523 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); 523 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
524 dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len); 524 dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len);
@@ -541,7 +541,7 @@ void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
541 struct dwc2_host_chan *chan, int chnum, 541 struct dwc2_host_chan *chan, int chnum,
542 struct dwc2_qtd *qtd) 542 struct dwc2_qtd *qtd)
543{ 543{
544 u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); 544 u32 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
545 u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT; 545 u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
546 546
547 if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) { 547 if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
@@ -780,9 +780,9 @@ cleanup:
780 } 780 }
781 } 781 }
782 782
783 haintmsk = dwc2_readl(hsotg->regs + HAINTMSK); 783 haintmsk = dwc2_readl(hsotg, HAINTMSK);
784 haintmsk &= ~(1 << chan->hc_num); 784 haintmsk &= ~(1 << chan->hc_num);
785 dwc2_writel(haintmsk, hsotg->regs + HAINTMSK); 785 dwc2_writel(hsotg, haintmsk, HAINTMSK);
786 786
787 /* Try to queue more transfers now that there's a free channel */ 787 /* Try to queue more transfers now that there's a free channel */
788 tr_type = dwc2_hcd_select_transactions(hsotg); 788 tr_type = dwc2_hcd_select_transactions(hsotg);
@@ -829,9 +829,9 @@ static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
829 * is enabled so that the non-periodic schedule will 829 * is enabled so that the non-periodic schedule will
830 * be processed 830 * be processed
831 */ 831 */
832 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 832 gintmsk = dwc2_readl(hsotg, GINTMSK);
833 gintmsk |= GINTSTS_NPTXFEMP; 833 gintmsk |= GINTSTS_NPTXFEMP;
834 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 834 dwc2_writel(hsotg, gintmsk, GINTMSK);
835 } else { 835 } else {
836 dev_vdbg(hsotg->dev, "isoc/intr\n"); 836 dev_vdbg(hsotg->dev, "isoc/intr\n");
837 /* 837 /*
@@ -848,9 +848,9 @@ static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
848 * enabled so that the periodic schedule will be 848 * enabled so that the periodic schedule will be
849 * processed 849 * processed
850 */ 850 */
851 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 851 gintmsk = dwc2_readl(hsotg, GINTMSK);
852 gintmsk |= GINTSTS_PTXFEMP; 852 gintmsk |= GINTSTS_PTXFEMP;
853 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 853 dwc2_writel(hsotg, gintmsk, GINTMSK);
854 } 854 }
855 } 855 }
856} 856}
@@ -915,7 +915,7 @@ static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
915 struct dwc2_qtd *qtd, 915 struct dwc2_qtd *qtd,
916 enum dwc2_halt_status halt_status) 916 enum dwc2_halt_status halt_status)
917{ 917{
918 u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); 918 u32 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
919 919
920 qtd->error_count = 0; 920 qtd->error_count = 0;
921 921
@@ -959,7 +959,7 @@ static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
959 959
960 qtd->isoc_split_offset += len; 960 qtd->isoc_split_offset += len;
961 961
962 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); 962 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
963 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT; 963 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
964 964
965 if (frame_desc->actual_length >= frame_desc->length || pid == 0) { 965 if (frame_desc->actual_length >= frame_desc->length || pid == 0) {
@@ -1185,7 +1185,7 @@ static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
1185 1185
1186 urb->actual_length += xfer_length; 1186 urb->actual_length += xfer_length;
1187 1187
1188 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); 1188 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
1189 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", 1189 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
1190 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); 1190 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
1191 dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n", 1191 dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n",
@@ -1566,10 +1566,10 @@ static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
1566 1566
1567 dwc2_hc_handle_tt_clear(hsotg, chan, qtd); 1567 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1568 1568
1569 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); 1569 hcchar = dwc2_readl(hsotg, HCCHAR(chnum));
1570 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum)); 1570 hcsplt = dwc2_readl(hsotg, HCSPLT(chnum));
1571 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); 1571 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
1572 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chnum)); 1572 hc_dma = dwc2_readl(hsotg, HCDMA(chnum));
1573 1573
1574 dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum); 1574 dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
1575 dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt); 1575 dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
@@ -1781,10 +1781,10 @@ static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1781 * This code is here only as a check. This condition should 1781 * This code is here only as a check. This condition should
1782 * never happen. Ignore the halt if it does occur. 1782 * never happen. Ignore the halt if it does occur.
1783 */ 1783 */
1784 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); 1784 hcchar = dwc2_readl(hsotg, HCCHAR(chnum));
1785 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); 1785 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
1786 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); 1786 hcintmsk = dwc2_readl(hsotg, HCINTMSK(chnum));
1787 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum)); 1787 hcsplt = dwc2_readl(hsotg, HCSPLT(chnum));
1788 dev_dbg(hsotg->dev, 1788 dev_dbg(hsotg->dev,
1789 "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n", 1789 "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
1790 __func__); 1790 __func__);
@@ -1808,7 +1808,7 @@ static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1808 * when the halt interrupt occurs. Halt the channel again if it does 1808 * when the halt interrupt occurs. Halt the channel again if it does
1809 * occur. 1809 * occur.
1810 */ 1810 */
1811 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); 1811 hcchar = dwc2_readl(hsotg, HCCHAR(chnum));
1812 if (hcchar & HCCHAR_CHDIS) { 1812 if (hcchar & HCCHAR_CHDIS) {
1813 dev_warn(hsotg->dev, 1813 dev_warn(hsotg->dev,
1814 "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n", 1814 "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
@@ -1868,7 +1868,7 @@ static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1868 return; 1868 return;
1869 } 1869 }
1870 1870
1871 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); 1871 hcintmsk = dwc2_readl(hsotg, HCINTMSK(chnum));
1872 1872
1873 if (chan->hcint & HCINTMSK_XFERCOMPL) { 1873 if (chan->hcint & HCINTMSK_XFERCOMPL) {
1874 /* 1874 /*
@@ -1963,7 +1963,7 @@ static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1963 dev_err(hsotg->dev, 1963 dev_err(hsotg->dev,
1964 "hcint 0x%08x, intsts 0x%08x\n", 1964 "hcint 0x%08x, intsts 0x%08x\n",
1965 chan->hcint, 1965 chan->hcint,
1966 dwc2_readl(hsotg->regs + GINTSTS)); 1966 dwc2_readl(hsotg, GINTSTS));
1967 goto error; 1967 goto error;
1968 } 1968 }
1969 } 1969 }
@@ -2036,11 +2036,11 @@ static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
2036 2036
2037 chan = hsotg->hc_ptr_array[chnum]; 2037 chan = hsotg->hc_ptr_array[chnum];
2038 2038
2039 hcint = dwc2_readl(hsotg->regs + HCINT(chnum)); 2039 hcint = dwc2_readl(hsotg, HCINT(chnum));
2040 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); 2040 hcintmsk = dwc2_readl(hsotg, HCINTMSK(chnum));
2041 if (!chan) { 2041 if (!chan) {
2042 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n"); 2042 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
2043 dwc2_writel(hcint, hsotg->regs + HCINT(chnum)); 2043 dwc2_writel(hsotg, hcint, HCINT(chnum));
2044 return; 2044 return;
2045 } 2045 }
2046 2046
@@ -2052,7 +2052,7 @@ static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
2052 hcint, hcintmsk, hcint & hcintmsk); 2052 hcint, hcintmsk, hcint & hcintmsk);
2053 } 2053 }
2054 2054
2055 dwc2_writel(hcint, hsotg->regs + HCINT(chnum)); 2055 dwc2_writel(hsotg, hcint, HCINT(chnum));
2056 2056
2057 /* 2057 /*
2058 * If we got an interrupt after someone called 2058 * If we got an interrupt after someone called
@@ -2187,7 +2187,7 @@ static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
2187 int i; 2187 int i;
2188 struct dwc2_host_chan *chan, *chan_tmp; 2188 struct dwc2_host_chan *chan, *chan_tmp;
2189 2189
2190 haint = dwc2_readl(hsotg->regs + HAINT); 2190 haint = dwc2_readl(hsotg, HAINT);
2191 if (dbg_perio()) { 2191 if (dbg_perio()) {
2192 dev_vdbg(hsotg->dev, "%s()\n", __func__); 2192 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2193 2193
@@ -2271,8 +2271,8 @@ irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
2271 "DWC OTG HCD Finished Servicing Interrupts\n"); 2271 "DWC OTG HCD Finished Servicing Interrupts\n");
2272 dev_vdbg(hsotg->dev, 2272 dev_vdbg(hsotg->dev,
2273 "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n", 2273 "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
2274 dwc2_readl(hsotg->regs + GINTSTS), 2274 dwc2_readl(hsotg, GINTSTS),
2275 dwc2_readl(hsotg->regs + GINTMSK)); 2275 dwc2_readl(hsotg, GINTMSK));
2276 } 2276 }
2277 } 2277 }
2278 2278
diff --git a/drivers/usb/dwc2/hcd_queue.c b/drivers/usb/dwc2/hcd_queue.c
index 301ced1618f8..40839591d2ec 100644
--- a/drivers/usb/dwc2/hcd_queue.c
+++ b/drivers/usb/dwc2/hcd_queue.c
@@ -1510,7 +1510,7 @@ static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
1510 bool ep_is_in = !!dwc2_hcd_is_pipe_in(&urb->pipe_info); 1510 bool ep_is_in = !!dwc2_hcd_is_pipe_in(&urb->pipe_info);
1511 bool ep_is_isoc = (ep_type == USB_ENDPOINT_XFER_ISOC); 1511 bool ep_is_isoc = (ep_type == USB_ENDPOINT_XFER_ISOC);
1512 bool ep_is_int = (ep_type == USB_ENDPOINT_XFER_INT); 1512 bool ep_is_int = (ep_type == USB_ENDPOINT_XFER_INT);
1513 u32 hprt = dwc2_readl(hsotg->regs + HPRT0); 1513 u32 hprt = dwc2_readl(hsotg, HPRT0);
1514 u32 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 1514 u32 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
1515 bool do_split = (prtspd == HPRT0_SPD_HIGH_SPEED && 1515 bool do_split = (prtspd == HPRT0_SPD_HIGH_SPEED &&
1516 dev_speed != USB_SPEED_HIGH); 1516 dev_speed != USB_SPEED_HIGH);
@@ -1747,9 +1747,9 @@ int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1747 if (status) 1747 if (status)
1748 return status; 1748 return status;
1749 if (!hsotg->periodic_qh_count) { 1749 if (!hsotg->periodic_qh_count) {
1750 intr_mask = dwc2_readl(hsotg->regs + GINTMSK); 1750 intr_mask = dwc2_readl(hsotg, GINTMSK);
1751 intr_mask |= GINTSTS_SOF; 1751 intr_mask |= GINTSTS_SOF;
1752 dwc2_writel(intr_mask, hsotg->regs + GINTMSK); 1752 dwc2_writel(hsotg, intr_mask, GINTMSK);
1753 } 1753 }
1754 hsotg->periodic_qh_count++; 1754 hsotg->periodic_qh_count++;
1755 1755
@@ -1788,9 +1788,9 @@ void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1788 hsotg->periodic_qh_count--; 1788 hsotg->periodic_qh_count--;
1789 if (!hsotg->periodic_qh_count && 1789 if (!hsotg->periodic_qh_count &&
1790 !hsotg->params.dma_desc_enable) { 1790 !hsotg->params.dma_desc_enable) {
1791 intr_mask = dwc2_readl(hsotg->regs + GINTMSK); 1791 intr_mask = dwc2_readl(hsotg, GINTMSK);
1792 intr_mask &= ~GINTSTS_SOF; 1792 intr_mask &= ~GINTSTS_SOF;
1793 dwc2_writel(intr_mask, hsotg->regs + GINTMSK); 1793 dwc2_writel(hsotg, intr_mask, GINTMSK);
1794 } 1794 }
1795} 1795}
1796 1796
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index af075d4da895..bf7052e037d6 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -47,7 +47,6 @@ static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
47 p->max_transfer_size = 65535; 47 p->max_transfer_size = 65535;
48 p->max_packet_count = 511; 48 p->max_packet_count = 511;
49 p->ahbcfg = 0x10; 49 p->ahbcfg = 0x10;
50 p->uframe_sched = false;
51} 50}
52 51
53static void dwc2_set_his_params(struct dwc2_hsotg *hsotg) 52static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
@@ -68,7 +67,6 @@ static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
68 p->reload_ctl = false; 67 p->reload_ctl = false;
69 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 68 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
70 GAHBCFG_HBSTLEN_SHIFT; 69 GAHBCFG_HBSTLEN_SHIFT;
71 p->uframe_sched = false;
72 p->change_speed_quirk = true; 70 p->change_speed_quirk = true;
73 p->power_down = false; 71 p->power_down = false;
74} 72}
@@ -112,7 +110,6 @@ static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
112 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 110 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
113 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << 111 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
114 GAHBCFG_HBSTLEN_SHIFT; 112 GAHBCFG_HBSTLEN_SHIFT;
115 p->uframe_sched = false;
116} 113}
117 114
118static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) 115static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
@@ -134,7 +131,6 @@ static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
134 p->max_packet_count = 256; 131 p->max_packet_count = 256;
135 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 132 p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
136 p->i2c_enable = false; 133 p->i2c_enable = false;
137 p->uframe_sched = false;
138 p->activate_stm_fs_transceiver = true; 134 p->activate_stm_fs_transceiver = true;
139} 135}
140 136
@@ -654,8 +650,8 @@ static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
654 650
655 dwc2_force_mode(hsotg, true); 651 dwc2_force_mode(hsotg, true);
656 652
657 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 653 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
658 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); 654 hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
659 655
660 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 656 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
661 FIFOSIZE_DEPTH_SHIFT; 657 FIFOSIZE_DEPTH_SHIFT;
@@ -679,13 +675,13 @@ static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
679 675
680 dwc2_force_mode(hsotg, false); 676 dwc2_force_mode(hsotg, false);
681 677
682 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 678 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
683 679
684 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 680 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
685 681
686 for (fifo = 1; fifo <= fifo_count; fifo++) { 682 for (fifo = 1; fifo <= fifo_count; fifo++) {
687 hw->g_tx_fifo_size[fifo] = 683 hw->g_tx_fifo_size[fifo] =
688 (dwc2_readl(hsotg->regs + DPTXFSIZN(fifo)) & 684 (dwc2_readl(hsotg, DPTXFSIZN(fifo)) &
689 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; 685 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
690 } 686 }
691 687
@@ -713,7 +709,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
713 * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx 709 * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx
714 */ 710 */
715 711
716 hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID); 712 hw->snpsid = dwc2_readl(hsotg, GSNPSID);
717 if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID && 713 if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID &&
718 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID && 714 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID &&
719 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) { 715 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) {
@@ -726,11 +722,11 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
726 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, 722 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
727 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); 723 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
728 724
729 hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1); 725 hwcfg1 = dwc2_readl(hsotg, GHWCFG1);
730 hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); 726 hwcfg2 = dwc2_readl(hsotg, GHWCFG2);
731 hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3); 727 hwcfg3 = dwc2_readl(hsotg, GHWCFG3);
732 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); 728 hwcfg4 = dwc2_readl(hsotg, GHWCFG4);
733 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 729 grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
734 730
735 /* hwcfg1 */ 731 /* hwcfg1 */
736 hw->dev_ep_dirs = hwcfg1; 732 hw->dev_ep_dirs = hwcfg1;
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 4c0819554bcd..9a53a58e676e 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -353,6 +353,23 @@ static void dwc2_driver_shutdown(struct platform_device *dev)
353} 353}
354 354
355/** 355/**
356 * dwc2_check_core_endianness() - Returns true if core and AHB have
357 * opposite endianness.
358 * @hsotg: Programming view of the DWC_otg controller.
359 */
360static bool dwc2_check_core_endianness(struct dwc2_hsotg *hsotg)
361{
362 u32 snpsid;
363
364 snpsid = ioread32(hsotg->regs + GSNPSID);
365 if ((snpsid & GSNPSID_ID_MASK) == DWC2_OTG_ID ||
366 (snpsid & GSNPSID_ID_MASK) == DWC2_FS_IOT_ID ||
367 (snpsid & GSNPSID_ID_MASK) == DWC2_HS_IOT_ID)
368 return false;
369 return true;
370}
371
372/**
356 * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg 373 * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
357 * driver 374 * driver
358 * 375 *
@@ -395,6 +412,8 @@ static int dwc2_driver_probe(struct platform_device *dev)
395 dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n", 412 dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
396 (unsigned long)res->start, hsotg->regs); 413 (unsigned long)res->start, hsotg->regs);
397 414
415 hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
416
398 retval = dwc2_lowlevel_hw_init(hsotg); 417 retval = dwc2_lowlevel_hw_init(hsotg);
399 if (retval) 418 if (retval)
400 return retval; 419 return retval;
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 451012ea1294..518ead12458d 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -74,11 +74,16 @@ config USB_DWC3_PCI
74 depends on USB_PCI && ACPI 74 depends on USB_PCI && ACPI
75 default USB_DWC3 75 default USB_DWC3
76 help 76 help
77 If you're using the DesignWare Core IP with a PCIe, please say 77 If you're using the DesignWare Core IP with a PCIe (but not HAPS
78 'Y' or 'M' here. 78 platform), please say 'Y' or 'M' here.
79 79
80 One such PCIe-based platform is Synopsys' PCIe HAPS model of 80config USB_DWC3_HAPS
81 this IP. 81 tristate "Synopsys PCIe-based HAPS Platforms"
82 depends on USB_PCI
83 default USB_DWC3
84 help
85 If you're using the DesignWare Core IP with a Synopsys PCIe HAPS
86 platform, please say 'Y' or 'M' here.
82 87
83config USB_DWC3_KEYSTONE 88config USB_DWC3_KEYSTONE
84 tristate "Texas Instruments Keystone2 Platforms" 89 tristate "Texas Instruments Keystone2 Platforms"
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index 5c07d8f925e0..6e3ef6144e5d 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -45,6 +45,7 @@ endif
45obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o 45obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
46obj-$(CONFIG_USB_DWC3_EXYNOS) += dwc3-exynos.o 46obj-$(CONFIG_USB_DWC3_EXYNOS) += dwc3-exynos.o
47obj-$(CONFIG_USB_DWC3_PCI) += dwc3-pci.o 47obj-$(CONFIG_USB_DWC3_PCI) += dwc3-pci.o
48obj-$(CONFIG_USB_DWC3_HAPS) += dwc3-haps.o
48obj-$(CONFIG_USB_DWC3_KEYSTONE) += dwc3-keystone.o 49obj-$(CONFIG_USB_DWC3_KEYSTONE) += dwc3-keystone.o
49obj-$(CONFIG_USB_DWC3_OF_SIMPLE) += dwc3-of-simple.o 50obj-$(CONFIG_USB_DWC3_OF_SIMPLE) += dwc3-of-simple.o
50obj-$(CONFIG_USB_DWC3_ST) += dwc3-st.o 51obj-$(CONFIG_USB_DWC3_ST) += dwc3-st.o
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 103807587dc6..88c80fcc39f5 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -78,6 +78,14 @@ static int dwc3_get_dr_mode(struct dwc3 *dwc)
78 mode = USB_DR_MODE_HOST; 78 mode = USB_DR_MODE_HOST;
79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
80 mode = USB_DR_MODE_PERIPHERAL; 80 mode = USB_DR_MODE_PERIPHERAL;
81
82 /*
83 * dwc_usb31 does not support OTG mode. If the controller
84 * supports DRD but the dr_mode is not specified or set to OTG,
85 * then set the mode to peripheral.
86 */
87 if (mode == USB_DR_MODE_OTG && dwc3_is_usb31(dwc))
88 mode = USB_DR_MODE_PERIPHERAL;
81 } 89 }
82 90
83 if (mode != dwc->dr_mode) { 91 if (mode != dwc->dr_mode) {
@@ -778,6 +786,98 @@ static void dwc3_core_setup_global_control(struct dwc3 *dwc)
778static int dwc3_core_get_phy(struct dwc3 *dwc); 786static int dwc3_core_get_phy(struct dwc3 *dwc);
779static int dwc3_core_ulpi_init(struct dwc3 *dwc); 787static int dwc3_core_ulpi_init(struct dwc3 *dwc);
780 788
789/* set global incr burst type configuration registers */
790static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
791{
792 struct device *dev = dwc->dev;
793 /* incrx_mode : for INCR burst type. */
794 bool incrx_mode;
795 /* incrx_size : for size of INCRX burst. */
796 u32 incrx_size;
797 u32 *vals;
798 u32 cfg;
799 int ntype;
800 int ret;
801 int i;
802
803 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
804
805 /*
806 * Handle property "snps,incr-burst-type-adjustment".
807 * Get the number of value from this property:
808 * result <= 0, means this property is not supported.
809 * result = 1, means INCRx burst mode supported.
810 * result > 1, means undefined length burst mode supported.
811 */
812 ntype = device_property_read_u32_array(dev,
813 "snps,incr-burst-type-adjustment", NULL, 0);
814 if (ntype <= 0)
815 return;
816
817 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
818 if (!vals) {
819 dev_err(dev, "Error to get memory\n");
820 return;
821 }
822
823 /* Get INCR burst type, and parse it */
824 ret = device_property_read_u32_array(dev,
825 "snps,incr-burst-type-adjustment", vals, ntype);
826 if (ret) {
827 dev_err(dev, "Error to get property\n");
828 return;
829 }
830
831 incrx_size = *vals;
832
833 if (ntype > 1) {
834 /* INCRX (undefined length) burst mode */
835 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
836 for (i = 1; i < ntype; i++) {
837 if (vals[i] > incrx_size)
838 incrx_size = vals[i];
839 }
840 } else {
841 /* INCRX burst mode */
842 incrx_mode = INCRX_BURST_MODE;
843 }
844
845 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
846 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
847 if (incrx_mode)
848 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
849 switch (incrx_size) {
850 case 256:
851 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
852 break;
853 case 128:
854 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
855 break;
856 case 64:
857 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
858 break;
859 case 32:
860 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
861 break;
862 case 16:
863 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
864 break;
865 case 8:
866 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
867 break;
868 case 4:
869 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
870 break;
871 case 1:
872 break;
873 default:
874 dev_err(dev, "Invalid property\n");
875 break;
876 }
877
878 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
879}
880
781/** 881/**
782 * dwc3_core_init - Low-level initialization of DWC3 Core 882 * dwc3_core_init - Low-level initialization of DWC3 Core
783 * @dwc: Pointer to our controller context structure 883 * @dwc: Pointer to our controller context structure
@@ -840,6 +940,8 @@ static int dwc3_core_init(struct dwc3 *dwc)
840 /* Adjust Frame Length */ 940 /* Adjust Frame Length */
841 dwc3_frame_length_adjustment(dwc); 941 dwc3_frame_length_adjustment(dwc);
842 942
943 dwc3_set_incr_burst_type(dwc);
944
843 usb_phy_set_suspend(dwc->usb2_phy, 0); 945 usb_phy_set_suspend(dwc->usb2_phy, 0);
844 usb_phy_set_suspend(dwc->usb3_phy, 0); 946 usb_phy_set_suspend(dwc->usb3_phy, 0);
845 ret = phy_power_on(dwc->usb2_generic_phy); 947 ret = phy_power_on(dwc->usb2_generic_phy);
@@ -883,6 +985,22 @@ static int dwc3_core_init(struct dwc3 *dwc)
883 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 985 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
884 } 986 }
885 987
988 if (dwc->dr_mode == USB_DR_MODE_HOST ||
989 dwc->dr_mode == USB_DR_MODE_OTG) {
990 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
991
992 /*
993 * Enable Auto retry Feature to make the controller operating in
994 * Host mode on seeing transaction errors(CRC errors or internal
995 * overrun scenerios) on IN transfers to reply to the device
996 * with a non-terminating retry ACK (i.e, an ACK transcation
997 * packet with Retry=1 & Nump != 0)
998 */
999 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1000
1001 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1002 }
1003
886 /* 1004 /*
887 * Must config both number of packets and max burst settings to enable 1005 * Must config both number of packets and max burst settings to enable
888 * RX and/or TX threshold. 1006 * RX and/or TX threshold.
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 285ce0ef3b91..5bfb62533e0f 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -163,6 +163,17 @@
163 163
164/* Bit fields */ 164/* Bit fields */
165 165
166/* Global SoC Bus Configuration INCRx Register 0 */
167#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
168#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
169#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
170#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */
171#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */
172#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */
173#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */
174#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
175#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
176
166/* Global Debug Queue/FIFO Space Available Register */ 177/* Global Debug Queue/FIFO Space Available Register */
167#define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) 178#define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
168#define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) 179#define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
@@ -227,6 +238,9 @@
227#define DWC3_GCTL_GBLHIBERNATIONEN BIT(1) 238#define DWC3_GCTL_GBLHIBERNATIONEN BIT(1)
228#define DWC3_GCTL_DSBLCLKGTNG BIT(0) 239#define DWC3_GCTL_DSBLCLKGTNG BIT(0)
229 240
241/* Global User Control Register */
242#define DWC3_GUCTL_HSTINAUTORETRY BIT(14)
243
230/* Global User Control 1 Register */ 244/* Global User Control 1 Register */
231#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) 245#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
232#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) 246#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
@@ -1157,6 +1171,9 @@ struct dwc3 {
1157 u16 imod_interval; 1171 u16 imod_interval;
1158}; 1172};
1159 1173
1174#define INCRX_BURST_MODE 0
1175#define INCRX_UNDEF_LENGTH_BURST_MODE 1
1176
1160#define work_to_dwc(w) (container_of((w), struct dwc3, drd_work)) 1177#define work_to_dwc(w) (container_of((w), struct dwc3, drd_work))
1161 1178
1162/* -------------------------------------------------------------------------- */ 1179/* -------------------------------------------------------------------------- */
diff --git a/drivers/usb/dwc3/dwc3-haps.c b/drivers/usb/dwc3/dwc3-haps.c
new file mode 100644
index 000000000000..c9cc33881bef
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-haps.c
@@ -0,0 +1,137 @@
1// SPDX-License-Identifier: GPL-2.0
2/**
3 * dwc3-haps.c - Synopsys HAPS PCI Specific glue layer
4 *
5 * Copyright (C) 2018 Synopsys, Inc.
6 *
7 * Authors: Thinh Nguyen <thinhn@synopsys.com>,
8 * John Youn <johnyoun@synopsys.com>
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/slab.h>
14#include <linux/pci.h>
15#include <linux/platform_device.h>
16#include <linux/property.h>
17
18#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd
19#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI 0xabce
20#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31 0xabcf
21
22/**
23 * struct dwc3_haps - Driver private structure
24 * @dwc3: child dwc3 platform_device
25 * @pci: our link to PCI bus
26 */
27struct dwc3_haps {
28 struct platform_device *dwc3;
29 struct pci_dev *pci;
30};
31
32static const struct property_entry initial_properties[] = {
33 PROPERTY_ENTRY_BOOL("snps,usb3_lpm_capable"),
34 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
35 PROPERTY_ENTRY_BOOL("snps,dis_enblslpm_quirk"),
36 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
37 { },
38};
39
40static int dwc3_haps_probe(struct pci_dev *pci,
41 const struct pci_device_id *id)
42{
43 struct dwc3_haps *dwc;
44 struct device *dev = &pci->dev;
45 struct resource res[2];
46 int ret;
47
48 ret = pcim_enable_device(pci);
49 if (ret) {
50 dev_err(dev, "failed to enable pci device\n");
51 return -ENODEV;
52 }
53
54 pci_set_master(pci);
55
56 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
57 if (!dwc)
58 return -ENOMEM;
59
60 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
61 if (!dwc->dwc3)
62 return -ENOMEM;
63
64 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
65
66 res[0].start = pci_resource_start(pci, 0);
67 res[0].end = pci_resource_end(pci, 0);
68 res[0].name = "dwc_usb3";
69 res[0].flags = IORESOURCE_MEM;
70
71 res[1].start = pci->irq;
72 res[1].name = "dwc_usb3";
73 res[1].flags = IORESOURCE_IRQ;
74
75 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
76 if (ret) {
77 dev_err(dev, "couldn't add resources to dwc3 device\n");
78 goto err;
79 }
80
81 dwc->pci = pci;
82 dwc->dwc3->dev.parent = dev;
83
84 ret = platform_device_add_properties(dwc->dwc3, initial_properties);
85 if (ret)
86 goto err;
87
88 ret = platform_device_add(dwc->dwc3);
89 if (ret) {
90 dev_err(dev, "failed to register dwc3 device\n");
91 goto err;
92 }
93
94 pci_set_drvdata(pci, dwc);
95
96 return 0;
97err:
98 platform_device_put(dwc->dwc3);
99 return ret;
100}
101
102static void dwc3_haps_remove(struct pci_dev *pci)
103{
104 struct dwc3_haps *dwc = pci_get_drvdata(pci);
105
106 platform_device_unregister(dwc->dwc3);
107}
108
109static const struct pci_device_id dwc3_haps_id_table[] = {
110 {
111 PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
112 PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3),
113 },
114 {
115 PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
116 PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI),
117 },
118 {
119 PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
120 PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31),
121 },
122 { } /* Terminating Entry */
123};
124MODULE_DEVICE_TABLE(pci, dwc3_haps_id_table);
125
126static struct pci_driver dwc3_haps_driver = {
127 .name = "dwc3-haps",
128 .id_table = dwc3_haps_id_table,
129 .probe = dwc3_haps_probe,
130 .remove = dwc3_haps_remove,
131};
132
133MODULE_AUTHOR("Thinh Nguyen <thinhn@synopsys.com>");
134MODULE_LICENSE("GPL v2");
135MODULE_DESCRIPTION("Synopsys HAPS PCI Glue Layer");
136
137module_pci_driver(dwc3_haps_driver);
diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
index dbeff5e6ad14..40bf9e0bbc59 100644
--- a/drivers/usb/dwc3/dwc3-of-simple.c
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
@@ -28,6 +28,7 @@ struct dwc3_of_simple {
28 int num_clocks; 28 int num_clocks;
29 struct reset_control *resets; 29 struct reset_control *resets;
30 bool pulse_resets; 30 bool pulse_resets;
31 bool need_reset;
31}; 32};
32 33
33static int dwc3_of_simple_clk_init(struct dwc3_of_simple *simple, int count) 34static int dwc3_of_simple_clk_init(struct dwc3_of_simple *simple, int count)
@@ -93,6 +94,13 @@ static int dwc3_of_simple_probe(struct platform_device *pdev)
93 platform_set_drvdata(pdev, simple); 94 platform_set_drvdata(pdev, simple);
94 simple->dev = dev; 95 simple->dev = dev;
95 96
97 /*
98 * Some controllers need to toggle the usb3-otg reset before trying to
99 * initialize the PHY, otherwise the PHY times out.
100 */
101 if (of_device_is_compatible(np, "rockchip,rk3399-dwc3"))
102 simple->need_reset = true;
103
96 if (of_device_is_compatible(np, "amlogic,meson-axg-dwc3") || 104 if (of_device_is_compatible(np, "amlogic,meson-axg-dwc3") ||
97 of_device_is_compatible(np, "amlogic,meson-gxl-dwc3")) { 105 of_device_is_compatible(np, "amlogic,meson-gxl-dwc3")) {
98 shared_resets = true; 106 shared_resets = true;
@@ -201,9 +209,30 @@ static int dwc3_of_simple_runtime_resume(struct device *dev)
201 209
202 return 0; 210 return 0;
203} 211}
212
213static int dwc3_of_simple_suspend(struct device *dev)
214{
215 struct dwc3_of_simple *simple = dev_get_drvdata(dev);
216
217 if (simple->need_reset)
218 reset_control_assert(simple->resets);
219
220 return 0;
221}
222
223static int dwc3_of_simple_resume(struct device *dev)
224{
225 struct dwc3_of_simple *simple = dev_get_drvdata(dev);
226
227 if (simple->need_reset)
228 reset_control_deassert(simple->resets);
229
230 return 0;
231}
204#endif 232#endif
205 233
206static const struct dev_pm_ops dwc3_of_simple_dev_pm_ops = { 234static const struct dev_pm_ops dwc3_of_simple_dev_pm_ops = {
235 SET_SYSTEM_SLEEP_PM_OPS(dwc3_of_simple_suspend, dwc3_of_simple_resume)
207 SET_RUNTIME_PM_OPS(dwc3_of_simple_runtime_suspend, 236 SET_RUNTIME_PM_OPS(dwc3_of_simple_runtime_suspend,
208 dwc3_of_simple_runtime_resume, NULL) 237 dwc3_of_simple_runtime_resume, NULL)
209}; 238};
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index f57e7c94b8e5..5edd79470368 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -16,12 +16,10 @@
16#include <linux/pm_runtime.h> 16#include <linux/pm_runtime.h>
17#include <linux/platform_device.h> 17#include <linux/platform_device.h>
18#include <linux/gpio/consumer.h> 18#include <linux/gpio/consumer.h>
19#include <linux/gpio/machine.h>
19#include <linux/acpi.h> 20#include <linux/acpi.h>
20#include <linux/delay.h> 21#include <linux/delay.h>
21 22
22#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd
23#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI 0xabce
24#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31 0xabcf
25#define PCI_DEVICE_ID_INTEL_BYT 0x0f37 23#define PCI_DEVICE_ID_INTEL_BYT 0x0f37
26#define PCI_DEVICE_ID_INTEL_MRFLD 0x119e 24#define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
27#define PCI_DEVICE_ID_INTEL_BSW 0x22b7 25#define PCI_DEVICE_ID_INTEL_BSW 0x22b7
@@ -41,12 +39,17 @@
41#define PCI_INTEL_BXT_STATE_D0 0 39#define PCI_INTEL_BXT_STATE_D0 0
42#define PCI_INTEL_BXT_STATE_D3 3 40#define PCI_INTEL_BXT_STATE_D3 3
43 41
42#define GP_RWBAR 1
43#define GP_RWREG1 0xa0
44#define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17)
45
44/** 46/**
45 * struct dwc3_pci - Driver private structure 47 * struct dwc3_pci - Driver private structure
46 * @dwc3: child dwc3 platform_device 48 * @dwc3: child dwc3 platform_device
47 * @pci: our link to PCI bus 49 * @pci: our link to PCI bus
48 * @guid: _DSM GUID 50 * @guid: _DSM GUID
49 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM 51 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
52 * @wakeup_work: work for asynchronous resume
50 */ 53 */
51struct dwc3_pci { 54struct dwc3_pci {
52 struct platform_device *dwc3; 55 struct platform_device *dwc3;
@@ -67,52 +70,74 @@ static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
67 { }, 70 { },
68}; 71};
69 72
70static int dwc3_pci_quirks(struct dwc3_pci *dwc) 73static struct gpiod_lookup_table platform_bytcr_gpios = {
74 .dev_id = "0000:00:16.0",
75 .table = {
76 GPIO_LOOKUP("INT33FC:00", 54, "reset", GPIO_ACTIVE_HIGH),
77 GPIO_LOOKUP("INT33FC:02", 14, "cs", GPIO_ACTIVE_HIGH),
78 {}
79 },
80};
81
82static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
71{ 83{
72 struct platform_device *dwc3 = dwc->dwc3; 84 void __iomem *reg;
73 struct pci_dev *pdev = dwc->pci; 85 u32 value;
86
87 reg = pcim_iomap(pci, GP_RWBAR, 0);
88 if (IS_ERR(reg))
89 return PTR_ERR(reg);
90
91 value = readl(reg + GP_RWREG1);
92 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
93 goto unmap; /* ULPI refclk already enabled */
94
95 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
96 writel(value, reg + GP_RWREG1);
97 /* This comes from the Intel Android x86 tree w/o any explanation */
98 msleep(100);
99unmap:
100 pcim_iounmap(pci, reg);
101 return 0;
102}
74 103
75 if (pdev->vendor == PCI_VENDOR_ID_AMD && 104static const struct property_entry dwc3_pci_intel_properties[] = {
76 pdev->device == PCI_DEVICE_ID_AMD_NL_USB) { 105 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
77 struct property_entry properties[] = { 106 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
78 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"), 107 {}
79 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf), 108};
80 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
81 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
82 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
83 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
84 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
85 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
86 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
87 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
88 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
89 /*
90 * FIXME these quirks should be removed when AMD NL
91 * tapes out
92 */
93 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
94 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
95 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
96 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
97 { },
98 };
99
100 return platform_device_add_properties(dwc3, properties);
101 }
102 109
103 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 110static const struct property_entry dwc3_pci_mrfld_properties[] = {
104 int ret; 111 PROPERTY_ENTRY_STRING("dr_mode", "otg"),
112 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
113 {}
114};
105 115
106 struct property_entry properties[] = { 116static const struct property_entry dwc3_pci_amd_properties[] = {
107 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 117 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
108 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 118 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
109 { } 119 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
110 }; 120 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
121 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
122 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
123 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
124 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
125 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
126 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
127 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
128 /* FIXME these quirks should be removed when AMD NL tapes out */
129 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
130 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
131 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
132 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
133 {}
134};
111 135
112 ret = platform_device_add_properties(dwc3, properties); 136static int dwc3_pci_quirks(struct dwc3_pci *dwc)
113 if (ret < 0) 137{
114 return ret; 138 struct pci_dev *pdev = dwc->pci;
115 139
140 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
116 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT || 141 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
117 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M) { 142 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M) {
118 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid); 143 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
@@ -121,6 +146,12 @@ static int dwc3_pci_quirks(struct dwc3_pci *dwc)
121 146
122 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) { 147 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
123 struct gpio_desc *gpio; 148 struct gpio_desc *gpio;
149 int ret;
150
151 /* On BYT the FW does not always enable the refclock */
152 ret = dwc3_byt_enable_ulpi_refclock(pdev);
153 if (ret)
154 return ret;
124 155
125 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev, 156 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
126 acpi_dwc3_byt_gpios); 157 acpi_dwc3_byt_gpios);
@@ -128,44 +159,36 @@ static int dwc3_pci_quirks(struct dwc3_pci *dwc)
128 dev_dbg(&pdev->dev, "failed to add mapping table\n"); 159 dev_dbg(&pdev->dev, "failed to add mapping table\n");
129 160
130 /* 161 /*
162 * A lot of BYT devices lack ACPI resource entries for
163 * the GPIOs, add a fallback mapping to the reference
164 * design GPIOs which all boards seem to use.
165 */
166 gpiod_add_lookup_table(&platform_bytcr_gpios);
167
168 /*
131 * These GPIOs will turn on the USB2 PHY. Note that we have to 169 * These GPIOs will turn on the USB2 PHY. Note that we have to
132 * put the gpio descriptors again here because the phy driver 170 * put the gpio descriptors again here because the phy driver
133 * might want to grab them, too. 171 * might want to grab them, too.
134 */ 172 */
135 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW); 173 gpio = devm_gpiod_get_optional(&pdev->dev, "cs",
174 GPIOD_OUT_LOW);
136 if (IS_ERR(gpio)) 175 if (IS_ERR(gpio))
137 return PTR_ERR(gpio); 176 return PTR_ERR(gpio);
138 177
139 gpiod_set_value_cansleep(gpio, 1); 178 gpiod_set_value_cansleep(gpio, 1);
140 gpiod_put(gpio);
141 179
142 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW); 180 gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
181 GPIOD_OUT_LOW);
143 if (IS_ERR(gpio)) 182 if (IS_ERR(gpio))
144 return PTR_ERR(gpio); 183 return PTR_ERR(gpio);
145 184
146 if (gpio) { 185 if (gpio) {
147 gpiod_set_value_cansleep(gpio, 1); 186 gpiod_set_value_cansleep(gpio, 1);
148 gpiod_put(gpio);
149 usleep_range(10000, 11000); 187 usleep_range(10000, 11000);
150 } 188 }
151 } 189 }
152 } 190 }
153 191
154 if (pdev->vendor == PCI_VENDOR_ID_SYNOPSYS &&
155 (pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 ||
156 pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI ||
157 pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31)) {
158 struct property_entry properties[] = {
159 PROPERTY_ENTRY_BOOL("snps,usb3_lpm_capable"),
160 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
161 PROPERTY_ENTRY_BOOL("snps,dis_enblslpm_quirk"),
162 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
163 { },
164 };
165
166 return platform_device_add_properties(dwc3, properties);
167 }
168
169 return 0; 192 return 0;
170} 193}
171 194
@@ -185,9 +208,9 @@ static void dwc3_pci_resume_work(struct work_struct *work)
185} 208}
186#endif 209#endif
187 210
188static int dwc3_pci_probe(struct pci_dev *pci, 211static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
189 const struct pci_device_id *id)
190{ 212{
213 struct property_entry *p = (struct property_entry *)id->driver_data;
191 struct dwc3_pci *dwc; 214 struct dwc3_pci *dwc;
192 struct resource res[2]; 215 struct resource res[2];
193 int ret; 216 int ret;
@@ -230,6 +253,10 @@ static int dwc3_pci_probe(struct pci_dev *pci,
230 dwc->dwc3->dev.parent = dev; 253 dwc->dwc3->dev.parent = dev;
231 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev)); 254 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
232 255
256 ret = platform_device_add_properties(dwc->dwc3, p);
257 if (ret < 0)
258 return ret;
259
233 ret = dwc3_pci_quirks(dwc); 260 ret = dwc3_pci_quirks(dwc);
234 if (ret) 261 if (ret)
235 goto err; 262 goto err;
@@ -257,6 +284,7 @@ static void dwc3_pci_remove(struct pci_dev *pci)
257{ 284{
258 struct dwc3_pci *dwc = pci_get_drvdata(pci); 285 struct dwc3_pci *dwc = pci_get_drvdata(pci);
259 286
287 gpiod_remove_lookup_table(&platform_bytcr_gpios);
260#ifdef CONFIG_PM 288#ifdef CONFIG_PM
261 cancel_work_sync(&dwc->wakeup_work); 289 cancel_work_sync(&dwc->wakeup_work);
262#endif 290#endif
@@ -266,32 +294,47 @@ static void dwc3_pci_remove(struct pci_dev *pci)
266} 294}
267 295
268static const struct pci_device_id dwc3_pci_id_table[] = { 296static const struct pci_device_id dwc3_pci_id_table[] = {
269 { 297 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW),
270 PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, 298 (kernel_ulong_t) &dwc3_pci_intel_properties },
271 PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3), 299
272 }, 300 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT),
273 { 301 (kernel_ulong_t) &dwc3_pci_intel_properties, },
274 PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, 302
275 PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI), 303 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD),
276 }, 304 (kernel_ulong_t) &dwc3_pci_mrfld_properties, },
277 { 305
278 PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, 306 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP),
279 PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31), 307 (kernel_ulong_t) &dwc3_pci_intel_properties, },
280 }, 308
281 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW), }, 309 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH),
282 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT), }, 310 (kernel_ulong_t) &dwc3_pci_intel_properties, },
283 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MRFLD), }, 311
284 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTLP), }, 312 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT),
285 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTH), }, 313 (kernel_ulong_t) &dwc3_pci_intel_properties, },
286 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT), }, 314
287 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT_M), }, 315 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M),
288 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL), }, 316 (kernel_ulong_t) &dwc3_pci_intel_properties, },
289 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBP), }, 317
290 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK), }, 318 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL),
291 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CNPLP), }, 319 (kernel_ulong_t) &dwc3_pci_intel_properties, },
292 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CNPH), }, 320
293 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICLLP), }, 321 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP),
294 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB), }, 322 (kernel_ulong_t) &dwc3_pci_intel_properties, },
323
324 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK),
325 (kernel_ulong_t) &dwc3_pci_intel_properties, },
326
327 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP),
328 (kernel_ulong_t) &dwc3_pci_intel_properties, },
329
330 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH),
331 (kernel_ulong_t) &dwc3_pci_intel_properties, },
332
333 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP),
334 (kernel_ulong_t) &dwc3_pci_intel_properties, },
335
336 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
337 (kernel_ulong_t) &dwc3_pci_amd_properties, },
295 { } /* Terminating Entry */ 338 { } /* Terminating Entry */
296}; 339};
297MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table); 340MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 69bf137aab37..032ea7d709ba 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -1121,7 +1121,7 @@ static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1121 req->request.short_not_ok, 1121 req->request.short_not_ok,
1122 req->request.no_interrupt); 1122 req->request.no_interrupt);
1123 } else if (req->request.zero && req->request.length && 1123 } else if (req->request.zero && req->request.length &&
1124 (IS_ALIGNED(req->request.length,dep->endpoint.maxpacket))) { 1124 (IS_ALIGNED(req->request.length, maxp))) {
1125 struct dwc3 *dwc = dep->dwc; 1125 struct dwc3 *dwc = dep->dwc;
1126 struct dwc3_trb *trb; 1126 struct dwc3_trb *trb;
1127 1127
diff --git a/drivers/usb/dwc3/gadget.h b/drivers/usb/dwc3/gadget.h
index db610c56f1d6..2aacd1afd9ff 100644
--- a/drivers/usb/dwc3/gadget.h
+++ b/drivers/usb/dwc3/gadget.h
@@ -25,7 +25,7 @@ struct dwc3;
25#define DWC3_DEPCFG_XFER_IN_PROGRESS_EN BIT(9) 25#define DWC3_DEPCFG_XFER_IN_PROGRESS_EN BIT(9)
26#define DWC3_DEPCFG_XFER_NOT_READY_EN BIT(10) 26#define DWC3_DEPCFG_XFER_NOT_READY_EN BIT(10)
27#define DWC3_DEPCFG_FIFO_ERROR_EN BIT(11) 27#define DWC3_DEPCFG_FIFO_ERROR_EN BIT(11)
28#define DWC3_DEPCFG_STREAM_EVENT_EN BIT(12) 28#define DWC3_DEPCFG_STREAM_EVENT_EN BIT(13)
29#define DWC3_DEPCFG_BINTERVAL_M1(n) (((n) & 0xff) << 16) 29#define DWC3_DEPCFG_BINTERVAL_M1(n) (((n) & 0xff) << 16)
30#define DWC3_DEPCFG_STREAM_CAPABLE BIT(24) 30#define DWC3_DEPCFG_STREAM_CAPABLE BIT(24)
31#define DWC3_DEPCFG_EP_NUMBER(n) (((n) & 0x1f) << 25) 31#define DWC3_DEPCFG_EP_NUMBER(n) (((n) & 0x1f) << 25)
diff --git a/drivers/usb/gadget/configfs.c b/drivers/usb/gadget/configfs.c
index efba66ca0719..025129942894 100644
--- a/drivers/usb/gadget/configfs.c
+++ b/drivers/usb/gadget/configfs.c
@@ -1217,8 +1217,8 @@ static void purge_configs_funcs(struct gadget_info *gi)
1217 list_move_tail(&f->list, &cfg->func_list); 1217 list_move_tail(&f->list, &cfg->func_list);
1218 if (f->unbind) { 1218 if (f->unbind) {
1219 dev_dbg(&gi->cdev.gadget->dev, 1219 dev_dbg(&gi->cdev.gadget->dev,
1220 "unbind function '%s'/%p\n", 1220 "unbind function '%s'/%p\n",
1221 f->name, f); 1221 f->name, f);
1222 f->unbind(c, f); 1222 f->unbind(c, f);
1223 } 1223 }
1224 } 1224 }
diff --git a/drivers/usb/gadget/function/f_mass_storage.c b/drivers/usb/gadget/function/f_mass_storage.c
index acecd13dcbd9..ca8a4b53c59f 100644
--- a/drivers/usb/gadget/function/f_mass_storage.c
+++ b/drivers/usb/gadget/function/f_mass_storage.c
@@ -206,7 +206,6 @@
206#include <linux/fcntl.h> 206#include <linux/fcntl.h>
207#include <linux/file.h> 207#include <linux/file.h>
208#include <linux/fs.h> 208#include <linux/fs.h>
209#include <linux/kref.h>
210#include <linux/kthread.h> 209#include <linux/kthread.h>
211#include <linux/sched/signal.h> 210#include <linux/sched/signal.h>
212#include <linux/limits.h> 211#include <linux/limits.h>
@@ -312,8 +311,6 @@ struct fsg_common {
312 void *private_data; 311 void *private_data;
313 312
314 char inquiry_string[INQUIRY_STRING_LEN]; 313 char inquiry_string[INQUIRY_STRING_LEN];
315
316 struct kref ref;
317}; 314};
318 315
319struct fsg_dev { 316struct fsg_dev {
@@ -2551,25 +2548,11 @@ static DEVICE_ATTR(file, 0, file_show, file_store);
2551 2548
2552/****************************** FSG COMMON ******************************/ 2549/****************************** FSG COMMON ******************************/
2553 2550
2554static void fsg_common_release(struct kref *ref);
2555
2556static void fsg_lun_release(struct device *dev) 2551static void fsg_lun_release(struct device *dev)
2557{ 2552{
2558 /* Nothing needs to be done */ 2553 /* Nothing needs to be done */
2559} 2554}
2560 2555
2561void fsg_common_get(struct fsg_common *common)
2562{
2563 kref_get(&common->ref);
2564}
2565EXPORT_SYMBOL_GPL(fsg_common_get);
2566
2567void fsg_common_put(struct fsg_common *common)
2568{
2569 kref_put(&common->ref, fsg_common_release);
2570}
2571EXPORT_SYMBOL_GPL(fsg_common_put);
2572
2573static struct fsg_common *fsg_common_setup(struct fsg_common *common) 2556static struct fsg_common *fsg_common_setup(struct fsg_common *common)
2574{ 2557{
2575 if (!common) { 2558 if (!common) {
@@ -2582,7 +2565,6 @@ static struct fsg_common *fsg_common_setup(struct fsg_common *common)
2582 } 2565 }
2583 init_rwsem(&common->filesem); 2566 init_rwsem(&common->filesem);
2584 spin_lock_init(&common->lock); 2567 spin_lock_init(&common->lock);
2585 kref_init(&common->ref);
2586 init_completion(&common->thread_notifier); 2568 init_completion(&common->thread_notifier);
2587 init_waitqueue_head(&common->io_wait); 2569 init_waitqueue_head(&common->io_wait);
2588 init_waitqueue_head(&common->fsg_wait); 2570 init_waitqueue_head(&common->fsg_wait);
@@ -2870,9 +2852,8 @@ void fsg_common_set_inquiry_string(struct fsg_common *common, const char *vn,
2870} 2852}
2871EXPORT_SYMBOL_GPL(fsg_common_set_inquiry_string); 2853EXPORT_SYMBOL_GPL(fsg_common_set_inquiry_string);
2872 2854
2873static void fsg_common_release(struct kref *ref) 2855static void fsg_common_release(struct fsg_common *common)
2874{ 2856{
2875 struct fsg_common *common = container_of(ref, struct fsg_common, ref);
2876 int i; 2857 int i;
2877 2858
2878 /* If the thread isn't already dead, tell it to exit now */ 2859 /* If the thread isn't already dead, tell it to exit now */
@@ -3308,7 +3289,9 @@ static ssize_t fsg_opts_num_buffers_store(struct config_item *item,
3308 if (ret) 3289 if (ret)
3309 goto end; 3290 goto end;
3310 3291
3311 fsg_common_set_num_buffers(opts->common, num); 3292 ret = fsg_common_set_num_buffers(opts->common, num);
3293 if (ret)
3294 goto end;
3312 ret = len; 3295 ret = len;
3313 3296
3314end: 3297end:
@@ -3344,7 +3327,7 @@ static void fsg_free_inst(struct usb_function_instance *fi)
3344 struct fsg_opts *opts; 3327 struct fsg_opts *opts;
3345 3328
3346 opts = fsg_opts_from_func_inst(fi); 3329 opts = fsg_opts_from_func_inst(fi);
3347 fsg_common_put(opts->common); 3330 fsg_common_release(opts->common);
3348 kfree(opts); 3331 kfree(opts);
3349} 3332}
3350 3333
@@ -3368,7 +3351,7 @@ static struct usb_function_instance *fsg_alloc_inst(void)
3368 rc = fsg_common_set_num_buffers(opts->common, 3351 rc = fsg_common_set_num_buffers(opts->common,
3369 CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS); 3352 CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS);
3370 if (rc) 3353 if (rc)
3371 goto release_opts; 3354 goto release_common;
3372 3355
3373 pr_info(FSG_DRIVER_DESC ", version: " FSG_DRIVER_VERSION "\n"); 3356 pr_info(FSG_DRIVER_DESC ", version: " FSG_DRIVER_VERSION "\n");
3374 3357
@@ -3391,6 +3374,8 @@ static struct usb_function_instance *fsg_alloc_inst(void)
3391 3374
3392release_buffers: 3375release_buffers:
3393 fsg_common_free_buffers(opts->common); 3376 fsg_common_free_buffers(opts->common);
3377release_common:
3378 kfree(opts->common);
3394release_opts: 3379release_opts:
3395 kfree(opts); 3380 kfree(opts);
3396 return ERR_PTR(rc); 3381 return ERR_PTR(rc);
diff --git a/drivers/usb/gadget/function/f_mass_storage.h b/drivers/usb/gadget/function/f_mass_storage.h
index 58857fcf199f..3b8c4ce2a40a 100644
--- a/drivers/usb/gadget/function/f_mass_storage.h
+++ b/drivers/usb/gadget/function/f_mass_storage.h
@@ -115,10 +115,6 @@ fsg_opts_from_func_inst(const struct usb_function_instance *fi)
115 return container_of(fi, struct fsg_opts, func_inst); 115 return container_of(fi, struct fsg_opts, func_inst);
116} 116}
117 117
118void fsg_common_get(struct fsg_common *common);
119
120void fsg_common_put(struct fsg_common *common);
121
122void fsg_common_set_sysfs(struct fsg_common *common, bool sysfs); 118void fsg_common_set_sysfs(struct fsg_common *common, bool sysfs);
123 119
124int fsg_common_set_num_buffers(struct fsg_common *common, unsigned int n); 120int fsg_common_set_num_buffers(struct fsg_common *common, unsigned int n);
diff --git a/drivers/usb/gadget/function/f_uvc.c b/drivers/usb/gadget/function/f_uvc.c
index 439eba660e95..d8ce7868fe22 100644
--- a/drivers/usb/gadget/function/f_uvc.c
+++ b/drivers/usb/gadget/function/f_uvc.c
@@ -6,16 +6,17 @@
6 * Laurent Pinchart (laurent.pinchart@ideasonboard.com) 6 * Laurent Pinchart (laurent.pinchart@ideasonboard.com)
7 */ 7 */
8 8
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/device.h> 9#include <linux/device.h>
12#include <linux/errno.h> 10#include <linux/errno.h>
13#include <linux/fs.h> 11#include <linux/fs.h>
12#include <linux/kernel.h>
14#include <linux/list.h> 13#include <linux/list.h>
14#include <linux/module.h>
15#include <linux/mutex.h> 15#include <linux/mutex.h>
16#include <linux/string.h> 16#include <linux/string.h>
17#include <linux/usb/ch9.h> 17#include <linux/usb/ch9.h>
18#include <linux/usb/gadget.h> 18#include <linux/usb/gadget.h>
19#include <linux/usb/g_uvc.h>
19#include <linux/usb/video.h> 20#include <linux/usb/video.h>
20#include <linux/vmalloc.h> 21#include <linux/vmalloc.h>
21#include <linux/wait.h> 22#include <linux/wait.h>
@@ -30,6 +31,8 @@
30#include "uvc_video.h" 31#include "uvc_video.h"
31 32
32unsigned int uvc_gadget_trace_param; 33unsigned int uvc_gadget_trace_param;
34module_param_named(trace, uvc_gadget_trace_param, uint, 0644);
35MODULE_PARM_DESC(trace, "Trace level bitmask");
33 36
34/* -------------------------------------------------------------------------- 37/* --------------------------------------------------------------------------
35 * Function descriptors 38 * Function descriptors
@@ -410,10 +413,21 @@ uvc_function_disconnect(struct uvc_device *uvc)
410 * USB probe and disconnect 413 * USB probe and disconnect
411 */ 414 */
412 415
416static ssize_t function_name_show(struct device *dev,
417 struct device_attribute *attr, char *buf)
418{
419 struct uvc_device *uvc = dev_get_drvdata(dev);
420
421 return sprintf(buf, "%s\n", uvc->func.fi->group.cg_item.ci_name);
422}
423
424static DEVICE_ATTR_RO(function_name);
425
413static int 426static int
414uvc_register_video(struct uvc_device *uvc) 427uvc_register_video(struct uvc_device *uvc)
415{ 428{
416 struct usb_composite_dev *cdev = uvc->func.config->cdev; 429 struct usb_composite_dev *cdev = uvc->func.config->cdev;
430 int ret;
417 431
418 /* TODO reference counting. */ 432 /* TODO reference counting. */
419 uvc->vdev.v4l2_dev = &uvc->v4l2_dev; 433 uvc->vdev.v4l2_dev = &uvc->v4l2_dev;
@@ -426,7 +440,17 @@ uvc_register_video(struct uvc_device *uvc)
426 440
427 video_set_drvdata(&uvc->vdev, uvc); 441 video_set_drvdata(&uvc->vdev, uvc);
428 442
429 return video_register_device(&uvc->vdev, VFL_TYPE_GRABBER, -1); 443 ret = video_register_device(&uvc->vdev, VFL_TYPE_GRABBER, -1);
444 if (ret < 0)
445 return ret;
446
447 ret = device_create_file(&uvc->vdev.dev, &dev_attr_function_name);
448 if (ret < 0) {
449 video_unregister_device(&uvc->vdev);
450 return ret;
451 }
452
453 return 0;
430} 454}
431 455
432#define UVC_COPY_DESCRIPTOR(mem, dst, desc) \ 456#define UVC_COPY_DESCRIPTOR(mem, dst, desc) \
@@ -864,6 +888,7 @@ static void uvc_unbind(struct usb_configuration *c, struct usb_function *f)
864 888
865 INFO(cdev, "%s\n", __func__); 889 INFO(cdev, "%s\n", __func__);
866 890
891 device_remove_file(&uvc->vdev.dev, &dev_attr_function_name);
867 video_unregister_device(&uvc->vdev); 892 video_unregister_device(&uvc->vdev);
868 v4l2_device_unregister(&uvc->v4l2_dev); 893 v4l2_device_unregister(&uvc->v4l2_dev);
869 894
diff --git a/drivers/usb/gadget/function/f_uvc.h b/drivers/usb/gadget/function/f_uvc.h
index 81defe4557fe..a81a17765558 100644
--- a/drivers/usb/gadget/function/f_uvc.h
+++ b/drivers/usb/gadget/function/f_uvc.h
@@ -9,10 +9,7 @@
9#ifndef _F_UVC_H_ 9#ifndef _F_UVC_H_
10#define _F_UVC_H_ 10#define _F_UVC_H_
11 11
12#include <linux/usb/composite.h> 12struct uvc_device;
13#include <linux/usb/video.h>
14
15#include "uvc.h"
16 13
17void uvc_function_setup_continue(struct uvc_device *uvc); 14void uvc_function_setup_continue(struct uvc_device *uvc);
18 15
@@ -21,4 +18,3 @@ void uvc_function_connect(struct uvc_device *uvc);
21void uvc_function_disconnect(struct uvc_device *uvc); 18void uvc_function_disconnect(struct uvc_device *uvc);
22 19
23#endif /* _F_UVC_H_ */ 20#endif /* _F_UVC_H_ */
24
diff --git a/drivers/usb/gadget/function/u_uvc.h b/drivers/usb/gadget/function/u_uvc.h
index d00d3ded71c0..2ed292e94fbc 100644
--- a/drivers/usb/gadget/function/u_uvc.h
+++ b/drivers/usb/gadget/function/u_uvc.h
@@ -13,6 +13,7 @@
13#ifndef U_UVC_H 13#ifndef U_UVC_H
14#define U_UVC_H 14#define U_UVC_H
15 15
16#include <linux/mutex.h>
16#include <linux/usb/composite.h> 17#include <linux/usb/composite.h>
17#include <linux/usb/video.h> 18#include <linux/usb/video.h>
18 19
@@ -20,7 +21,6 @@
20 21
21struct f_uvc_opts { 22struct f_uvc_opts {
22 struct usb_function_instance func_inst; 23 struct usb_function_instance func_inst;
23 unsigned int uvc_gadget_trace_param;
24 unsigned int streaming_interval; 24 unsigned int streaming_interval;
25 unsigned int streaming_maxpacket; 25 unsigned int streaming_maxpacket;
26 unsigned int streaming_maxburst; 26 unsigned int streaming_maxburst;
@@ -80,7 +80,4 @@ struct f_uvc_opts {
80 int refcnt; 80 int refcnt;
81}; 81};
82 82
83void uvc_set_trace_param(unsigned int trace);
84
85#endif /* U_UVC_H */ 83#endif /* U_UVC_H */
86
diff --git a/drivers/usb/gadget/function/uvc.h b/drivers/usb/gadget/function/uvc.h
index a64e07e61f8c..93cf78b420fe 100644
--- a/drivers/usb/gadget/function/uvc.h
+++ b/drivers/usb/gadget/function/uvc.h
@@ -9,52 +9,26 @@
9#ifndef _UVC_GADGET_H_ 9#ifndef _UVC_GADGET_H_
10#define _UVC_GADGET_H_ 10#define _UVC_GADGET_H_
11 11
12#include <linux/ioctl.h> 12#include <linux/list.h>
13#include <linux/types.h> 13#include <linux/mutex.h>
14#include <linux/usb/ch9.h> 14#include <linux/spinlock.h>
15 15#include <linux/usb/composite.h>
16#define UVC_EVENT_FIRST (V4L2_EVENT_PRIVATE_START + 0) 16#include <linux/videodev2.h>
17#define UVC_EVENT_CONNECT (V4L2_EVENT_PRIVATE_START + 0)
18#define UVC_EVENT_DISCONNECT (V4L2_EVENT_PRIVATE_START + 1)
19#define UVC_EVENT_STREAMON (V4L2_EVENT_PRIVATE_START + 2)
20#define UVC_EVENT_STREAMOFF (V4L2_EVENT_PRIVATE_START + 3)
21#define UVC_EVENT_SETUP (V4L2_EVENT_PRIVATE_START + 4)
22#define UVC_EVENT_DATA (V4L2_EVENT_PRIVATE_START + 5)
23#define UVC_EVENT_LAST (V4L2_EVENT_PRIVATE_START + 5)
24
25struct uvc_request_data {
26 __s32 length;
27 __u8 data[60];
28};
29 17
30struct uvc_event { 18#include <media/v4l2-device.h>
31 union { 19#include <media/v4l2-dev.h>
32 enum usb_device_speed speed; 20#include <media/v4l2-fh.h>
33 struct usb_ctrlrequest req;
34 struct uvc_request_data data;
35 };
36};
37 21
38#define UVCIOC_SEND_RESPONSE _IOW('U', 1, struct uvc_request_data) 22#include "uvc_queue.h"
39 23
40#define UVC_INTF_CONTROL 0 24struct usb_ep;
41#define UVC_INTF_STREAMING 1 25struct usb_request;
26struct uvc_descriptor_header;
42 27
43/* ------------------------------------------------------------------------ 28/* ------------------------------------------------------------------------
44 * Debugging, printing and logging 29 * Debugging, printing and logging
45 */ 30 */
46 31
47#ifdef __KERNEL__
48
49#include <linux/usb.h> /* For usb_endpoint_* */
50#include <linux/usb/composite.h>
51#include <linux/usb/gadget.h>
52#include <linux/videodev2.h>
53#include <media/v4l2-fh.h>
54#include <media/v4l2-device.h>
55
56#include "uvc_queue.h"
57
58#define UVC_TRACE_PROBE (1 << 0) 32#define UVC_TRACE_PROBE (1 << 0)
59#define UVC_TRACE_DESCR (1 << 1) 33#define UVC_TRACE_DESCR (1 << 1)
60#define UVC_TRACE_CONTROL (1 << 2) 34#define UVC_TRACE_CONTROL (1 << 2)
@@ -184,7 +158,4 @@ extern void uvc_endpoint_stream(struct uvc_device *dev);
184extern void uvc_function_connect(struct uvc_device *uvc); 158extern void uvc_function_connect(struct uvc_device *uvc);
185extern void uvc_function_disconnect(struct uvc_device *uvc); 159extern void uvc_function_disconnect(struct uvc_device *uvc);
186 160
187#endif /* __KERNEL__ */
188
189#endif /* _UVC_GADGET_H_ */ 161#endif /* _UVC_GADGET_H_ */
190
diff --git a/drivers/usb/gadget/function/uvc_configfs.c b/drivers/usb/gadget/function/uvc_configfs.c
index c9b8cc4aae5a..b51f0d278826 100644
--- a/drivers/usb/gadget/function/uvc_configfs.c
+++ b/drivers/usb/gadget/function/uvc_configfs.c
@@ -31,7 +31,11 @@ static struct configfs_attribute prefix##attr_##cname = { \
31 .show = prefix##cname##_show, \ 31 .show = prefix##cname##_show, \
32} 32}
33 33
34static inline struct f_uvc_opts *to_f_uvc_opts(struct config_item *item); 34static inline struct f_uvc_opts *to_f_uvc_opts(struct config_item *item)
35{
36 return container_of(to_config_group(item), struct f_uvc_opts,
37 func_inst.group);
38}
35 39
36/* control/header/<NAME> */ 40/* control/header/<NAME> */
37DECLARE_UVC_HEADER_DESCRIPTOR(1); 41DECLARE_UVC_HEADER_DESCRIPTOR(1);
@@ -2105,12 +2109,6 @@ static const struct config_item_type uvcg_streaming_grp_type = {
2105 .ct_owner = THIS_MODULE, 2109 .ct_owner = THIS_MODULE,
2106}; 2110};
2107 2111
2108static inline struct f_uvc_opts *to_f_uvc_opts(struct config_item *item)
2109{
2110 return container_of(to_config_group(item), struct f_uvc_opts,
2111 func_inst.group);
2112}
2113
2114static void uvc_attr_release(struct config_item *item) 2112static void uvc_attr_release(struct config_item *item)
2115{ 2113{
2116 struct f_uvc_opts *opts = to_f_uvc_opts(item); 2114 struct f_uvc_opts *opts = to_f_uvc_opts(item);
diff --git a/drivers/usb/gadget/function/uvc_queue.h b/drivers/usb/gadget/function/uvc_queue.h
index f9f65b5c1062..2f0fff769843 100644
--- a/drivers/usb/gadget/function/uvc_queue.h
+++ b/drivers/usb/gadget/function/uvc_queue.h
@@ -2,13 +2,15 @@
2#ifndef _UVC_QUEUE_H_ 2#ifndef _UVC_QUEUE_H_
3#define _UVC_QUEUE_H_ 3#define _UVC_QUEUE_H_
4 4
5#ifdef __KERNEL__ 5#include <linux/list.h>
6
7#include <linux/kernel.h>
8#include <linux/poll.h> 6#include <linux/poll.h>
9#include <linux/videodev2.h> 7#include <linux/spinlock.h>
8
10#include <media/videobuf2-v4l2.h> 9#include <media/videobuf2-v4l2.h>
11 10
11struct file;
12struct mutex;
13
12/* Maximum frame size in bytes, for sanity checking. */ 14/* Maximum frame size in bytes, for sanity checking. */
13#define UVC_MAX_FRAME_SIZE (16*1024*1024) 15#define UVC_MAX_FRAME_SIZE (16*1024*1024)
14/* Maximum number of video buffers. */ 16/* Maximum number of video buffers. */
@@ -91,7 +93,5 @@ struct uvc_buffer *uvcg_queue_next_buffer(struct uvc_video_queue *queue,
91 93
92struct uvc_buffer *uvcg_queue_head(struct uvc_video_queue *queue); 94struct uvc_buffer *uvcg_queue_head(struct uvc_video_queue *queue);
93 95
94#endif /* __KERNEL__ */
95
96#endif /* _UVC_QUEUE_H_ */ 96#endif /* _UVC_QUEUE_H_ */
97 97
diff --git a/drivers/usb/gadget/function/uvc_v4l2.c b/drivers/usb/gadget/function/uvc_v4l2.c
index 9a9019625496..7f1ca3b57823 100644
--- a/drivers/usb/gadget/function/uvc_v4l2.c
+++ b/drivers/usb/gadget/function/uvc_v4l2.c
@@ -6,10 +6,11 @@
6 * Laurent Pinchart (laurent.pinchart@ideasonboard.com) 6 * Laurent Pinchart (laurent.pinchart@ideasonboard.com)
7 */ 7 */
8 8
9#include <linux/kernel.h>
10#include <linux/device.h> 9#include <linux/device.h>
11#include <linux/errno.h> 10#include <linux/errno.h>
11#include <linux/kernel.h>
12#include <linux/list.h> 12#include <linux/list.h>
13#include <linux/usb/g_uvc.h>
13#include <linux/videodev2.h> 14#include <linux/videodev2.h>
14#include <linux/vmalloc.h> 15#include <linux/vmalloc.h>
15#include <linux/wait.h> 16#include <linux/wait.h>
diff --git a/drivers/usb/gadget/function/uvc_video.h b/drivers/usb/gadget/function/uvc_video.h
index 6c20aa75f966..7d77122b0ff9 100644
--- a/drivers/usb/gadget/function/uvc_video.h
+++ b/drivers/usb/gadget/function/uvc_video.h
@@ -12,6 +12,8 @@
12#ifndef __UVC_VIDEO_H__ 12#ifndef __UVC_VIDEO_H__
13#define __UVC_VIDEO_H__ 13#define __UVC_VIDEO_H__
14 14
15struct uvc_video;
16
15int uvcg_video_pump(struct uvc_video *video); 17int uvcg_video_pump(struct uvc_video *video);
16 18
17int uvcg_video_enable(struct uvc_video *video, int enable); 19int uvcg_video_enable(struct uvc_video *video, int enable);
diff --git a/drivers/usb/gadget/legacy/tcm_usb_gadget.c b/drivers/usb/gadget/legacy/tcm_usb_gadget.c
index 682bf99dcf76..40870227999a 100644
--- a/drivers/usb/gadget/legacy/tcm_usb_gadget.c
+++ b/drivers/usb/gadget/legacy/tcm_usb_gadget.c
@@ -41,7 +41,7 @@ static struct usb_device_descriptor usbg_device_desc = {
41#define USB_G_STR_CONFIG USB_GADGET_FIRST_AVAIL_IDX 41#define USB_G_STR_CONFIG USB_GADGET_FIRST_AVAIL_IDX
42 42
43static struct usb_string usbg_us_strings[] = { 43static struct usb_string usbg_us_strings[] = {
44 [USB_GADGET_MANUFACTURER_IDX].s = "Target Manufactor", 44 [USB_GADGET_MANUFACTURER_IDX].s = "Target Manufacturer",
45 [USB_GADGET_PRODUCT_IDX].s = "Target Product", 45 [USB_GADGET_PRODUCT_IDX].s = "Target Product",
46 [USB_GADGET_SERIAL_IDX].s = "000000000001", 46 [USB_GADGET_SERIAL_IDX].s = "000000000001",
47 [USB_G_STR_CONFIG].s = "default config", 47 [USB_G_STR_CONFIG].s = "default config",
diff --git a/drivers/usb/gadget/legacy/webcam.c b/drivers/usb/gadget/legacy/webcam.c
index 6b86568c9157..a9f8eb8e1c76 100644
--- a/drivers/usb/gadget/legacy/webcam.c
+++ b/drivers/usb/gadget/legacy/webcam.c
@@ -30,9 +30,6 @@ static unsigned int streaming_maxburst;
30module_param(streaming_maxburst, uint, S_IRUGO|S_IWUSR); 30module_param(streaming_maxburst, uint, S_IRUGO|S_IWUSR);
31MODULE_PARM_DESC(streaming_maxburst, "0 - 15 (ss only)"); 31MODULE_PARM_DESC(streaming_maxburst, "0 - 15 (ss only)");
32 32
33static unsigned int trace;
34module_param(trace, uint, S_IRUGO|S_IWUSR);
35MODULE_PARM_DESC(trace, "Trace level bitmask");
36/* -------------------------------------------------------------------------- 33/* --------------------------------------------------------------------------
37 * Device descriptor 34 * Device descriptor
38 */ 35 */
@@ -379,7 +376,6 @@ webcam_bind(struct usb_composite_dev *cdev)
379 uvc_opts->streaming_interval = streaming_interval; 376 uvc_opts->streaming_interval = streaming_interval;
380 uvc_opts->streaming_maxpacket = streaming_maxpacket; 377 uvc_opts->streaming_maxpacket = streaming_maxpacket;
381 uvc_opts->streaming_maxburst = streaming_maxburst; 378 uvc_opts->streaming_maxburst = streaming_maxburst;
382 uvc_set_trace_param(trace);
383 379
384 uvc_opts->fs_control = uvc_fs_control_cls; 380 uvc_opts->fs_control = uvc_fs_control_cls;
385 uvc_opts->ss_control = uvc_ss_control_cls; 381 uvc_opts->ss_control = uvc_ss_control_cls;
diff --git a/drivers/usb/gadget/udc/Kconfig b/drivers/usb/gadget/udc/Kconfig
index 1df4dedffe86..0a16cbd4e528 100644
--- a/drivers/usb/gadget/udc/Kconfig
+++ b/drivers/usb/gadget/udc/Kconfig
@@ -193,6 +193,7 @@ config USB_RENESAS_USB3
193 tristate 'Renesas USB3.0 Peripheral controller' 193 tristate 'Renesas USB3.0 Peripheral controller'
194 depends on ARCH_RENESAS || COMPILE_TEST 194 depends on ARCH_RENESAS || COMPILE_TEST
195 depends on EXTCON 195 depends on EXTCON
196 select USB_ROLE_SWITCH
196 help 197 help
197 Renesas USB3.0 Peripheral controller is a USB peripheral controller 198 Renesas USB3.0 Peripheral controller is a USB peripheral controller
198 that supports super, high, and full speed USB 3.0 data transfers. 199 that supports super, high, and full speed USB 3.0 data transfers.
diff --git a/drivers/usb/gadget/udc/core.c b/drivers/usb/gadget/udc/core.c
index cab5e4f09924..af88b48c1cea 100644
--- a/drivers/usb/gadget/udc/core.c
+++ b/drivers/usb/gadget/udc/core.c
@@ -87,6 +87,8 @@ EXPORT_SYMBOL_GPL(usb_ep_set_maxpacket_limit);
87 * configurable, with more generic names like "ep-a". (remember that for 87 * configurable, with more generic names like "ep-a". (remember that for
88 * USB, "in" means "towards the USB master".) 88 * USB, "in" means "towards the USB master".)
89 * 89 *
90 * This routine must be called in process context.
91 *
90 * returns zero, or a negative error code. 92 * returns zero, or a negative error code.
91 */ 93 */
92int usb_ep_enable(struct usb_ep *ep) 94int usb_ep_enable(struct usb_ep *ep)
@@ -119,6 +121,8 @@ EXPORT_SYMBOL_GPL(usb_ep_enable);
119 * gadget drivers must call usb_ep_enable() again before queueing 121 * gadget drivers must call usb_ep_enable() again before queueing
120 * requests to the endpoint. 122 * requests to the endpoint.
121 * 123 *
124 * This routine must be called in process context.
125 *
122 * returns zero, or a negative error code. 126 * returns zero, or a negative error code.
123 */ 127 */
124int usb_ep_disable(struct usb_ep *ep) 128int usb_ep_disable(struct usb_ep *ep)
@@ -241,6 +245,8 @@ EXPORT_SYMBOL_GPL(usb_ep_free_request);
241 * Note that @req's ->complete() callback must never be called from 245 * Note that @req's ->complete() callback must never be called from
242 * within usb_ep_queue() as that can create deadlock situations. 246 * within usb_ep_queue() as that can create deadlock situations.
243 * 247 *
248 * This routine may be called in interrupt context.
249 *
244 * Returns zero, or a negative error code. Endpoints that are not enabled 250 * Returns zero, or a negative error code. Endpoints that are not enabled
245 * report errors; errors will also be 251 * report errors; errors will also be
246 * reported when the usb peripheral is disconnected. 252 * reported when the usb peripheral is disconnected.
@@ -284,6 +290,8 @@ EXPORT_SYMBOL_GPL(usb_ep_queue);
284 * at the head of the queue) except as part of disconnecting from usb. Such 290 * at the head of the queue) except as part of disconnecting from usb. Such
285 * restrictions prevent drivers from supporting configuration changes, 291 * restrictions prevent drivers from supporting configuration changes,
286 * even to configuration zero (a "chapter 9" requirement). 292 * even to configuration zero (a "chapter 9" requirement).
293 *
294 * This routine may be called in interrupt context.
287 */ 295 */
288int usb_ep_dequeue(struct usb_ep *ep, struct usb_request *req) 296int usb_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
289{ 297{
@@ -311,6 +319,8 @@ EXPORT_SYMBOL_GPL(usb_ep_dequeue);
311 * current altsetting, see usb_ep_clear_halt(). When switching altsettings, 319 * current altsetting, see usb_ep_clear_halt(). When switching altsettings,
312 * it's simplest to use usb_ep_enable() or usb_ep_disable() for the endpoints. 320 * it's simplest to use usb_ep_enable() or usb_ep_disable() for the endpoints.
313 * 321 *
322 * This routine may be called in interrupt context.
323 *
314 * Returns zero, or a negative error code. On success, this call sets 324 * Returns zero, or a negative error code. On success, this call sets
315 * underlying hardware state that blocks data transfers. 325 * underlying hardware state that blocks data transfers.
316 * Attempts to halt IN endpoints will fail (returning -EAGAIN) if any 326 * Attempts to halt IN endpoints will fail (returning -EAGAIN) if any
@@ -336,6 +346,8 @@ EXPORT_SYMBOL_GPL(usb_ep_set_halt);
336 * for endpoints that aren't reconfigured, after clearing any other state 346 * for endpoints that aren't reconfigured, after clearing any other state
337 * in the endpoint's i/o queue. 347 * in the endpoint's i/o queue.
338 * 348 *
349 * This routine may be called in interrupt context.
350 *
339 * Returns zero, or a negative error code. On success, this call clears 351 * Returns zero, or a negative error code. On success, this call clears
340 * the underlying hardware state reflecting endpoint halt and data toggle. 352 * the underlying hardware state reflecting endpoint halt and data toggle.
341 * Note that some hardware can't support this request (like pxa2xx_udc), 353 * Note that some hardware can't support this request (like pxa2xx_udc),
@@ -360,6 +372,8 @@ EXPORT_SYMBOL_GPL(usb_ep_clear_halt);
360 * requests. If the gadget driver clears the halt status, it will 372 * requests. If the gadget driver clears the halt status, it will
361 * automatically unwedge the endpoint. 373 * automatically unwedge the endpoint.
362 * 374 *
375 * This routine may be called in interrupt context.
376 *
363 * Returns zero on success, else negative errno. 377 * Returns zero on success, else negative errno.
364 */ 378 */
365int usb_ep_set_wedge(struct usb_ep *ep) 379int usb_ep_set_wedge(struct usb_ep *ep)
@@ -388,6 +402,8 @@ EXPORT_SYMBOL_GPL(usb_ep_set_wedge);
388 * written OUT to it by the host. Drivers that need precise handling for 402 * written OUT to it by the host. Drivers that need precise handling for
389 * fault reporting or recovery may need to use this call. 403 * fault reporting or recovery may need to use this call.
390 * 404 *
405 * This routine may be called in interrupt context.
406 *
391 * This returns the number of such bytes in the fifo, or a negative 407 * This returns the number of such bytes in the fifo, or a negative
392 * errno if the endpoint doesn't use a FIFO or doesn't support such 408 * errno if the endpoint doesn't use a FIFO or doesn't support such
393 * precise handling. 409 * precise handling.
@@ -415,6 +431,8 @@ EXPORT_SYMBOL_GPL(usb_ep_fifo_status);
415 * an endpoint fifo after abnormal transaction terminations. The call 431 * an endpoint fifo after abnormal transaction terminations. The call
416 * must never be used except when endpoint is not being used for any 432 * must never be used except when endpoint is not being used for any
417 * protocol translation. 433 * protocol translation.
434 *
435 * This routine may be called in interrupt context.
418 */ 436 */
419void usb_ep_fifo_flush(struct usb_ep *ep) 437void usb_ep_fifo_flush(struct usb_ep *ep)
420{ 438{
diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c
index 7cf98c793e04..1f879b3f2c96 100644
--- a/drivers/usb/gadget/udc/renesas_usb3.c
+++ b/drivers/usb/gadget/udc/renesas_usb3.c
@@ -23,6 +23,8 @@
23#include <linux/uaccess.h> 23#include <linux/uaccess.h>
24#include <linux/usb/ch9.h> 24#include <linux/usb/ch9.h>
25#include <linux/usb/gadget.h> 25#include <linux/usb/gadget.h>
26#include <linux/usb/of.h>
27#include <linux/usb/role.h>
26 28
27/* register definitions */ 29/* register definitions */
28#define USB3_AXI_INT_STA 0x008 30#define USB3_AXI_INT_STA 0x008
@@ -335,6 +337,11 @@ struct renesas_usb3 {
335 struct phy *phy; 337 struct phy *phy;
336 struct dentry *dentry; 338 struct dentry *dentry;
337 339
340 struct usb_role_switch *role_sw;
341 struct device *host_dev;
342 struct work_struct role_work;
343 enum usb_role role;
344
338 struct renesas_usb3_ep *usb3_ep; 345 struct renesas_usb3_ep *usb3_ep;
339 int num_usb3_eps; 346 int num_usb3_eps;
340 347
@@ -651,6 +658,14 @@ static void usb3_check_vbus(struct renesas_usb3 *usb3)
651 } 658 }
652} 659}
653 660
661static void renesas_usb3_role_work(struct work_struct *work)
662{
663 struct renesas_usb3 *usb3 =
664 container_of(work, struct renesas_usb3, role_work);
665
666 usb_role_switch_set_role(usb3->role_sw, usb3->role);
667}
668
654static void usb3_set_mode(struct renesas_usb3 *usb3, bool host) 669static void usb3_set_mode(struct renesas_usb3 *usb3, bool host)
655{ 670{
656 if (host) 671 if (host)
@@ -659,6 +674,16 @@ static void usb3_set_mode(struct renesas_usb3 *usb3, bool host)
659 usb3_set_bit(usb3, DRD_CON_PERI_CON, USB3_DRD_CON); 674 usb3_set_bit(usb3, DRD_CON_PERI_CON, USB3_DRD_CON);
660} 675}
661 676
677static void usb3_set_mode_by_role_sw(struct renesas_usb3 *usb3, bool host)
678{
679 if (usb3->role_sw) {
680 usb3->role = host ? USB_ROLE_HOST : USB_ROLE_DEVICE;
681 schedule_work(&usb3->role_work);
682 } else {
683 usb3_set_mode(usb3, host);
684 }
685}
686
662static void usb3_vbus_out(struct renesas_usb3 *usb3, bool enable) 687static void usb3_vbus_out(struct renesas_usb3 *usb3, bool enable)
663{ 688{
664 if (enable) 689 if (enable)
@@ -672,7 +697,7 @@ static void usb3_mode_config(struct renesas_usb3 *usb3, bool host, bool a_dev)
672 unsigned long flags; 697 unsigned long flags;
673 698
674 spin_lock_irqsave(&usb3->lock, flags); 699 spin_lock_irqsave(&usb3->lock, flags);
675 usb3_set_mode(usb3, host); 700 usb3_set_mode_by_role_sw(usb3, host);
676 usb3_vbus_out(usb3, a_dev); 701 usb3_vbus_out(usb3, a_dev);
677 /* for A-Peripheral or forced B-device mode */ 702 /* for A-Peripheral or forced B-device mode */
678 if ((!host && a_dev) || 703 if ((!host && a_dev) ||
@@ -2302,6 +2327,41 @@ static const struct usb_gadget_ops renesas_usb3_gadget_ops = {
2302 .set_selfpowered = renesas_usb3_set_selfpowered, 2327 .set_selfpowered = renesas_usb3_set_selfpowered,
2303}; 2328};
2304 2329
2330static enum usb_role renesas_usb3_role_switch_get(struct device *dev)
2331{
2332 struct renesas_usb3 *usb3 = dev_get_drvdata(dev);
2333 enum usb_role cur_role;
2334
2335 pm_runtime_get_sync(dev);
2336 cur_role = usb3_is_host(usb3) ? USB_ROLE_HOST : USB_ROLE_DEVICE;
2337 pm_runtime_put(dev);
2338
2339 return cur_role;
2340}
2341
2342static int renesas_usb3_role_switch_set(struct device *dev,
2343 enum usb_role role)
2344{
2345 struct renesas_usb3 *usb3 = dev_get_drvdata(dev);
2346 struct device *host = usb3->host_dev;
2347 enum usb_role cur_role = renesas_usb3_role_switch_get(dev);
2348
2349 pm_runtime_get_sync(dev);
2350 if (cur_role == USB_ROLE_HOST && role == USB_ROLE_DEVICE) {
2351 device_release_driver(host);
2352 usb3_set_mode(usb3, false);
2353 } else if (cur_role == USB_ROLE_DEVICE && role == USB_ROLE_HOST) {
2354 /* Must set the mode before device_attach of the host */
2355 usb3_set_mode(usb3, true);
2356 /* This device_attach() might sleep */
2357 if (device_attach(host) < 0)
2358 dev_err(dev, "device_attach(host) failed\n");
2359 }
2360 pm_runtime_put(dev);
2361
2362 return 0;
2363}
2364
2305static ssize_t role_store(struct device *dev, struct device_attribute *attr, 2365static ssize_t role_store(struct device *dev, struct device_attribute *attr,
2306 const char *buf, size_t count) 2366 const char *buf, size_t count)
2307{ 2367{
@@ -2405,6 +2465,8 @@ static int renesas_usb3_remove(struct platform_device *pdev)
2405 debugfs_remove_recursive(usb3->dentry); 2465 debugfs_remove_recursive(usb3->dentry);
2406 device_remove_file(&pdev->dev, &dev_attr_role); 2466 device_remove_file(&pdev->dev, &dev_attr_role);
2407 2467
2468 usb_role_switch_unregister(usb3->role_sw);
2469
2408 usb_del_gadget_udc(&usb3->gadget); 2470 usb_del_gadget_udc(&usb3->gadget);
2409 renesas_usb3_dma_free_prd(usb3, &pdev->dev); 2471 renesas_usb3_dma_free_prd(usb3, &pdev->dev);
2410 2472
@@ -2562,6 +2624,12 @@ static const unsigned int renesas_usb3_cable[] = {
2562 EXTCON_NONE, 2624 EXTCON_NONE,
2563}; 2625};
2564 2626
2627static const struct usb_role_switch_desc renesas_usb3_role_switch_desc = {
2628 .set = renesas_usb3_role_switch_set,
2629 .get = renesas_usb3_role_switch_get,
2630 .allow_userspace_control = true,
2631};
2632
2565static int renesas_usb3_probe(struct platform_device *pdev) 2633static int renesas_usb3_probe(struct platform_device *pdev)
2566{ 2634{
2567 struct renesas_usb3 *usb3; 2635 struct renesas_usb3 *usb3;
@@ -2647,6 +2715,20 @@ static int renesas_usb3_probe(struct platform_device *pdev)
2647 if (ret < 0) 2715 if (ret < 0)
2648 goto err_dev_create; 2716 goto err_dev_create;
2649 2717
2718 INIT_WORK(&usb3->role_work, renesas_usb3_role_work);
2719 usb3->role_sw = usb_role_switch_register(&pdev->dev,
2720 &renesas_usb3_role_switch_desc);
2721 if (!IS_ERR(usb3->role_sw)) {
2722 usb3->host_dev = usb_of_get_companion_dev(&pdev->dev);
2723 if (!usb3->host_dev) {
2724 /* If not found, this driver will not use a role sw */
2725 usb_role_switch_unregister(usb3->role_sw);
2726 usb3->role_sw = NULL;
2727 }
2728 } else {
2729 usb3->role_sw = NULL;
2730 }
2731
2650 usb3->workaround_for_vbus = priv->workaround_for_vbus; 2732 usb3->workaround_for_vbus = priv->workaround_for_vbus;
2651 2733
2652 renesas_usb3_debugfs_init(usb3, &pdev->dev); 2734 renesas_usb3_debugfs_init(usb3, &pdev->dev);
diff --git a/include/uapi/linux/usb/g_uvc.h b/include/uapi/linux/usb/g_uvc.h
new file mode 100644
index 000000000000..3c9ee3020cbb
--- /dev/null
+++ b/include/uapi/linux/usb/g_uvc.h
@@ -0,0 +1,39 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * g_uvc.h -- USB Video Class Gadget driver API
4 *
5 * Copyright (C) 2009-2010 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
6 */
7
8#ifndef __LINUX_USB_G_UVC_H
9#define __LINUX_USB_G_UVC_H
10
11#include <linux/ioctl.h>
12#include <linux/types.h>
13#include <linux/usb/ch9.h>
14
15#define UVC_EVENT_FIRST (V4L2_EVENT_PRIVATE_START + 0)
16#define UVC_EVENT_CONNECT (V4L2_EVENT_PRIVATE_START + 0)
17#define UVC_EVENT_DISCONNECT (V4L2_EVENT_PRIVATE_START + 1)
18#define UVC_EVENT_STREAMON (V4L2_EVENT_PRIVATE_START + 2)
19#define UVC_EVENT_STREAMOFF (V4L2_EVENT_PRIVATE_START + 3)
20#define UVC_EVENT_SETUP (V4L2_EVENT_PRIVATE_START + 4)
21#define UVC_EVENT_DATA (V4L2_EVENT_PRIVATE_START + 5)
22#define UVC_EVENT_LAST (V4L2_EVENT_PRIVATE_START + 5)
23
24struct uvc_request_data {
25 __s32 length;
26 __u8 data[60];
27};
28
29struct uvc_event {
30 union {
31 enum usb_device_speed speed;
32 struct usb_ctrlrequest req;
33 struct uvc_request_data data;
34 };
35};
36
37#define UVCIOC_SEND_RESPONSE _IOW('U', 1, struct uvc_request_data)
38
39#endif /* __LINUX_USB_G_UVC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 22:27:11 -0400