drm/i915/skl: Make the init clock gating function skylake specific

We'll gather cross-gen9 W/A in a separate function later.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 613827596aad..b162c5c288bb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -52,7 +52,7 @@
 #define INTEL_RC6p_ENABLE                       (1<<1)
 #define INTEL_RC6pp_ENABLE                      (1<<2)
 
-static void gen9_init_clock_gating(struct drm_device *dev)
+static void skl_init_clock_gating(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
 
@@ -6419,7 +6419,7 @@ void intel_init_pm(struct drm_device *dev)
         if (INTEL_INFO(dev)->gen >= 9) {
                 skl_setup_wm_latency(dev);
 
-                dev_priv->display.init_clock_gating = gen9_init_clock_gating;
+                dev_priv->display.init_clock_gating = skl_init_clock_gating;
                 dev_priv->display.update_wm = skl_update_wm;
                 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
         } else if (HAS_PCH_SPLIT(dev)) {