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authorArnd Bergmann <arnd@arndb.de>2014-03-18 11:19:44 -0400
committerArnd Bergmann <arnd@arndb.de>2014-03-18 11:19:50 -0400
commit4569f2b7be6f30f0edd2319d91ba718b8f26e232 (patch)
tree5469499bb5c6c7502731e28108ce28ae0ff71c81
parentcda88c8be59128da05d7cd58f9ce2754a1416516 (diff)
parente063735f9155826ee96a9bbc5407a1ead192f295 (diff)
Merge branch 'sti/dt' into next/drivers
This is apparently a dependency for the STi reset controller driver. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/reset/st,sti-powerdown.txt47
-rw-r--r--Documentation/devicetree/bindings/reset/st,sti-softreset.txt46
-rw-r--r--arch/arm/boot/dts/stih415-clock.dtsi14
-rw-r--r--arch/arm/boot/dts/stih415-pinctrl.dtsi204
-rw-r--r--arch/arm/boot/dts/stih415.dtsi70
-rw-r--r--arch/arm/boot/dts/stih416-clock.dtsi14
-rw-r--r--arch/arm/boot/dts/stih416-pinctrl.dtsi197
-rw-r--r--arch/arm/boot/dts/stih416.dtsi67
-rw-r--r--arch/arm/boot/dts/stih41x-b2000.dtsi22
-rw-r--r--arch/arm/boot/dts/stih41x-b2020.dtsi13
-rw-r--r--include/dt-bindings/reset-controller/stih415-resets.h26
-rw-r--r--include/dt-bindings/reset-controller/stih416-resets.h50
12 files changed, 770 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt b/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
new file mode 100644
index 000000000000..5ab26b7e9d35
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
@@ -0,0 +1,47 @@
1STMicroelectronics STi family Sysconfig Peripheral Powerdown Reset Controller
2=============================================================================
3
4This binding describes a reset controller device that is used to enable and
5disable on-chip peripheral controllers such as USB and SATA, using
6"powerdown" control bits found in the STi family SoC system configuration
7registers. These have been grouped together into a single reset controller
8device for convenience.
9
10The actual action taken when powerdown is asserted is hardware dependent.
11However, when asserted it may not be possible to access the hardware's
12registers and after an assert/deassert sequence the hardware's previous state
13may no longer be valid.
14
15Please refer to reset.txt in this directory for common reset
16controller binding usage.
17
18Required properties:
19- compatible: Should be "st,<chip>-powerdown"
20 ex: "st,stih415-powerdown", "st,stih416-powerdown"
21- #reset-cells: 1, see below
22
23example:
24
25 powerdown: powerdown-controller {
26 #reset-cells = <1>;
27 compatible = "st,stih415-powerdown";
28 };
29
30
31Specifying powerdown control of devices
32=======================================
33
34Device nodes should specify the reset channel required in their "resets"
35property, containing a phandle to the powerdown device node and an
36index specifying which channel to use, as described in reset.txt
37
38example:
39
40 usb1: usb@fe200000 {
41 resets = <&powerdown STIH41X_USB1_POWERDOWN>;
42 };
43
44Macro definitions for the supported reset channels can be found in:
45
46include/dt-bindings/reset-controller/stih415-resets.h
47include/dt-bindings/reset-controller/stih416-resets.h
diff --git a/Documentation/devicetree/bindings/reset/st,sti-softreset.txt b/Documentation/devicetree/bindings/reset/st,sti-softreset.txt
new file mode 100644
index 000000000000..a8d3d3c25ca2
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/st,sti-softreset.txt
@@ -0,0 +1,46 @@
1STMicroelectronics STi family Sysconfig Peripheral SoftReset Controller
2=============================================================================
3
4This binding describes a reset controller device that is used to enable and
5disable on-chip peripheral controllers such as USB and SATA, using
6"softreset" control bits found in the STi family SoC system configuration
7registers.
8
9The actual action taken when softreset is asserted is hardware dependent.
10However, when asserted it may not be possible to access the hardware's
11registers and after an assert/deassert sequence the hardware's previous state
12may no longer be valid.
13
14Please refer to reset.txt in this directory for common reset
15controller binding usage.
16
17Required properties:
18- compatible: Should be "st,<chip>-softreset" example:
19 "st,stih415-softreset" or "st,stih416-softreset";
20- #reset-cells: 1, see below
21
22example:
23
24 softreset: softreset-controller {
25 #reset-cells = <1>;
26 compatible = "st,stih415-softreset";
27 };
28
29
30Specifying softreset control of devices
31=======================================
32
33Device nodes should specify the reset channel required in their "resets"
34property, containing a phandle to the softreset device node and an
35index specifying which channel to use, as described in reset.txt
36
37example:
38
39 ethernet0{
40 resets = <&softreset STIH415_ETH0_SOFTRESET>;
41 };
42
43Macro definitions for the supported reset channels can be found in:
44
45include/dt-bindings/reset-controller/stih415-resets.h
46include/dt-bindings/reset-controller/stih416-resets.h
diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi
index 174c799df741..d047dbc28d61 100644
--- a/arch/arm/boot/dts/stih415-clock.dtsi
+++ b/arch/arm/boot/dts/stih415-clock.dtsi
@@ -34,5 +34,19 @@
34 compatible = "fixed-clock"; 34 compatible = "fixed-clock";
35 clock-frequency = <100000000>; 35 clock-frequency = <100000000>;
36 }; 36 };
37
38 CLKS_GMAC0_PHY: clockgenA1@7 {
39 #clock-cells = <0>;
40 compatible = "fixed-clock";
41 clock-frequency = <25000000>;
42 clock-output-names = "CLKS_GMAC0_PHY";
43 };
44
45 CLKS_ETH1_PHY: clockgenA0@7 {
46 #clock-cells = <0>;
47 compatible = "fixed-clock";
48 clock-frequency = <25000000>;
49 clock-output-names = "CLKS_ETH1_PHY";
50 };
37 }; 51 };
38}; 52};
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
index e56449d41481..f09fb10a3791 100644
--- a/arch/arm/boot/dts/stih415-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -7,6 +7,7 @@
7 * publishhed by the Free Software Foundation. 7 * publishhed by the Free Software Foundation.
8 */ 8 */
9#include "st-pincfg.h" 9#include "st-pincfg.h"
10#include <dt-bindings/interrupt-controller/arm-gic.h>
10/ { 11/ {
11 12
12 aliases { 13 aliases {
@@ -45,35 +46,49 @@
45 #size-cells = <1>; 46 #size-cells = <1>;
46 compatible = "st,stih415-sbc-pinctrl"; 47 compatible = "st,stih415-sbc-pinctrl";
47 st,syscfg = <&syscfg_sbc>; 48 st,syscfg = <&syscfg_sbc>;
49 reg = <0xfe61f080 0x4>;
50 reg-names = "irqmux";
51 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
52 interrupts-names = "irqmux";
48 ranges = <0 0xfe610000 0x5000>; 53 ranges = <0 0xfe610000 0x5000>;
49 54
50 PIO0: gpio@fe610000 { 55 PIO0: gpio@fe610000 {
51 gpio-controller; 56 gpio-controller;
52 #gpio-cells = <1>; 57 #gpio-cells = <1>;
58 interrupt-controller;
59 #interrupt-cells = <2>;
53 reg = <0 0x100>; 60 reg = <0 0x100>;
54 st,bank-name = "PIO0"; 61 st,bank-name = "PIO0";
55 }; 62 };
56 PIO1: gpio@fe611000 { 63 PIO1: gpio@fe611000 {
57 gpio-controller; 64 gpio-controller;
58 #gpio-cells = <1>; 65 #gpio-cells = <1>;
66 interrupt-controller;
67 #interrupt-cells = <2>;
59 reg = <0x1000 0x100>; 68 reg = <0x1000 0x100>;
60 st,bank-name = "PIO1"; 69 st,bank-name = "PIO1";
61 }; 70 };
62 PIO2: gpio@fe612000 { 71 PIO2: gpio@fe612000 {
63 gpio-controller; 72 gpio-controller;
64 #gpio-cells = <1>; 73 #gpio-cells = <1>;
74 interrupt-controller;
75 #interrupt-cells = <2>;
65 reg = <0x2000 0x100>; 76 reg = <0x2000 0x100>;
66 st,bank-name = "PIO2"; 77 st,bank-name = "PIO2";
67 }; 78 };
68 PIO3: gpio@fe613000 { 79 PIO3: gpio@fe613000 {
69 gpio-controller; 80 gpio-controller;
70 #gpio-cells = <1>; 81 #gpio-cells = <1>;
82 interrupt-controller;
83 #interrupt-cells = <2>;
71 reg = <0x3000 0x100>; 84 reg = <0x3000 0x100>;
72 st,bank-name = "PIO3"; 85 st,bank-name = "PIO3";
73 }; 86 };
74 PIO4: gpio@fe614000 { 87 PIO4: gpio@fe614000 {
75 gpio-controller; 88 gpio-controller;
76 #gpio-cells = <1>; 89 #gpio-cells = <1>;
90 interrupt-controller;
91 #interrupt-cells = <2>;
77 reg = <0x4000 0x100>; 92 reg = <0x4000 0x100>;
78 st,bank-name = "PIO4"; 93 st,bank-name = "PIO4";
79 }; 94 };
@@ -104,6 +119,64 @@
104 }; 119 };
105 }; 120 };
106 }; 121 };
122
123 rc{
124 pinctrl_ir: ir0 {
125 st,pins {
126 ir = <&PIO4 0 ALT2 IN>;
127 };
128 };
129 };
130
131 gmac1 {
132 pinctrl_mii1: mii1 {
133 st,pins {
134 txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
135 txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
136 txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
137 txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
138 txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
139 txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
140 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
141 col = <&PIO0 7 ALT1 IN BYPASS 1000>;
142 mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
143 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
144 crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
145 mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
146 rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
147 rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
148 rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
149 rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
150 rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
151 rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
152 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
153 phyclk = <&PIO2 3 ALT1 IN NICLK 1000 CLK_A>;
154 };
155 };
156
157 pinctrl_rgmii1: rgmii1-0 {
158 st,pins {
159 txd0 = <&PIO0 0 ALT1 OUT DE_IO 1000 CLK_A>;
160 txd1 = <&PIO0 1 ALT1 OUT DE_IO 1000 CLK_A>;
161 txd2 = <&PIO0 2 ALT1 OUT DE_IO 1000 CLK_A>;
162 txd3 = <&PIO0 3 ALT1 OUT DE_IO 1000 CLK_A>;
163 txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
164 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
165 mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
166 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
167 rxd0 = <&PIO1 4 ALT1 IN DE_IO 0 CLK_A>;
168 rxd1 = <&PIO1 5 ALT1 IN DE_IO 0 CLK_A>;
169 rxd2 = <&PIO1 6 ALT1 IN DE_IO 0 CLK_A>;
170 rxd3 = <&PIO1 7 ALT1 IN DE_IO 0 CLK_A>;
171
172 rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
173 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
174 phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
175
176 clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
177 };
178 };
179 };
107 }; 180 };
108 181
109 pin-controller-front { 182 pin-controller-front {
@@ -111,53 +184,73 @@
111 #size-cells = <1>; 184 #size-cells = <1>;
112 compatible = "st,stih415-front-pinctrl"; 185 compatible = "st,stih415-front-pinctrl";
113 st,syscfg = <&syscfg_front>; 186 st,syscfg = <&syscfg_front>;
187 reg = <0xfee0f080 0x4>;
188 reg-names = "irqmux";
189 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
190 interrupts-names = "irqmux";
114 ranges = <0 0xfee00000 0x8000>; 191 ranges = <0 0xfee00000 0x8000>;
115 192
116 PIO5: gpio@fee00000 { 193 PIO5: gpio@fee00000 {
117 gpio-controller; 194 gpio-controller;
118 #gpio-cells = <1>; 195 #gpio-cells = <1>;
196 interrupt-controller;
197 #interrupt-cells = <2>;
119 reg = <0 0x100>; 198 reg = <0 0x100>;
120 st,bank-name = "PIO5"; 199 st,bank-name = "PIO5";
121 }; 200 };
122 PIO6: gpio@fee01000 { 201 PIO6: gpio@fee01000 {
123 gpio-controller; 202 gpio-controller;
124 #gpio-cells = <1>; 203 #gpio-cells = <1>;
204 interrupt-controller;
205 #interrupt-cells = <2>;
125 reg = <0x1000 0x100>; 206 reg = <0x1000 0x100>;
126 st,bank-name = "PIO6"; 207 st,bank-name = "PIO6";
127 }; 208 };
128 PIO7: gpio@fee02000 { 209 PIO7: gpio@fee02000 {
129 gpio-controller; 210 gpio-controller;
130 #gpio-cells = <1>; 211 #gpio-cells = <1>;
212 interrupt-controller;
213 #interrupt-cells = <2>;
131 reg = <0x2000 0x100>; 214 reg = <0x2000 0x100>;
132 st,bank-name = "PIO7"; 215 st,bank-name = "PIO7";
133 }; 216 };
134 PIO8: gpio@fee03000 { 217 PIO8: gpio@fee03000 {
135 gpio-controller; 218 gpio-controller;
136 #gpio-cells = <1>; 219 #gpio-cells = <1>;
220 interrupt-controller;
221 #interrupt-cells = <2>;
137 reg = <0x3000 0x100>; 222 reg = <0x3000 0x100>;
138 st,bank-name = "PIO8"; 223 st,bank-name = "PIO8";
139 }; 224 };
140 PIO9: gpio@fee04000 { 225 PIO9: gpio@fee04000 {
141 gpio-controller; 226 gpio-controller;
142 #gpio-cells = <1>; 227 #gpio-cells = <1>;
228 interrupt-controller;
229 #interrupt-cells = <2>;
143 reg = <0x4000 0x100>; 230 reg = <0x4000 0x100>;
144 st,bank-name = "PIO9"; 231 st,bank-name = "PIO9";
145 }; 232 };
146 PIO10: gpio@fee05000 { 233 PIO10: gpio@fee05000 {
147 gpio-controller; 234 gpio-controller;
148 #gpio-cells = <1>; 235 #gpio-cells = <1>;
236 interrupt-controller;
237 #interrupt-cells = <2>;
149 reg = <0x5000 0x100>; 238 reg = <0x5000 0x100>;
150 st,bank-name = "PIO10"; 239 st,bank-name = "PIO10";
151 }; 240 };
152 PIO11: gpio@fee06000 { 241 PIO11: gpio@fee06000 {
153 gpio-controller; 242 gpio-controller;
154 #gpio-cells = <1>; 243 #gpio-cells = <1>;
244 interrupt-controller;
245 #interrupt-cells = <2>;
155 reg = <0x6000 0x100>; 246 reg = <0x6000 0x100>;
156 st,bank-name = "PIO11"; 247 st,bank-name = "PIO11";
157 }; 248 };
158 PIO12: gpio@fee07000 { 249 PIO12: gpio@fee07000 {
159 gpio-controller; 250 gpio-controller;
160 #gpio-cells = <1>; 251 #gpio-cells = <1>;
252 interrupt-controller;
253 #interrupt-cells = <2>;
161 reg = <0x7000 0x100>; 254 reg = <0x7000 0x100>;
162 st,bank-name = "PIO12"; 255 st,bank-name = "PIO12";
163 }; 256 };
@@ -186,41 +279,57 @@
186 #size-cells = <1>; 279 #size-cells = <1>;
187 compatible = "st,stih415-rear-pinctrl"; 280 compatible = "st,stih415-rear-pinctrl";
188 st,syscfg = <&syscfg_rear>; 281 st,syscfg = <&syscfg_rear>;
282 reg = <0xfe82f080 0x4>;
283 reg-names = "irqmux";
284 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
285 interrupts-names = "irqmux";
189 ranges = <0 0xfe820000 0x8000>; 286 ranges = <0 0xfe820000 0x8000>;
190 287
191 PIO13: gpio@fe820000 { 288 PIO13: gpio@fe820000 {
192 gpio-controller; 289 gpio-controller;
193 #gpio-cells = <1>; 290 #gpio-cells = <1>;
291 interrupt-controller;
292 #interrupt-cells = <2>;
194 reg = <0 0x100>; 293 reg = <0 0x100>;
195 st,bank-name = "PIO13"; 294 st,bank-name = "PIO13";
196 }; 295 };
197 PIO14: gpio@fe821000 { 296 PIO14: gpio@fe821000 {
198 gpio-controller; 297 gpio-controller;
199 #gpio-cells = <1>; 298 #gpio-cells = <1>;
299 interrupt-controller;
300 #interrupt-cells = <2>;
200 reg = <0x1000 0x100>; 301 reg = <0x1000 0x100>;
201 st,bank-name = "PIO14"; 302 st,bank-name = "PIO14";
202 }; 303 };
203 PIO15: gpio@fe822000 { 304 PIO15: gpio@fe822000 {
204 gpio-controller; 305 gpio-controller;
205 #gpio-cells = <1>; 306 #gpio-cells = <1>;
307 interrupt-controller;
308 #interrupt-cells = <2>;
206 reg = <0x2000 0x100>; 309 reg = <0x2000 0x100>;
207 st,bank-name = "PIO15"; 310 st,bank-name = "PIO15";
208 }; 311 };
209 PIO16: gpio@fe823000 { 312 PIO16: gpio@fe823000 {
210 gpio-controller; 313 gpio-controller;
211 #gpio-cells = <1>; 314 #gpio-cells = <1>;
315 interrupt-controller;
316 #interrupt-cells = <2>;
212 reg = <0x3000 0x100>; 317 reg = <0x3000 0x100>;
213 st,bank-name = "PIO16"; 318 st,bank-name = "PIO16";
214 }; 319 };
215 PIO17: gpio@fe824000 { 320 PIO17: gpio@fe824000 {
216 gpio-controller; 321 gpio-controller;
217 #gpio-cells = <1>; 322 #gpio-cells = <1>;
323 interrupt-controller;
324 #interrupt-cells = <2>;
218 reg = <0x4000 0x100>; 325 reg = <0x4000 0x100>;
219 st,bank-name = "PIO17"; 326 st,bank-name = "PIO17";
220 }; 327 };
221 PIO18: gpio@fe825000 { 328 PIO18: gpio@fe825000 {
222 gpio-controller; 329 gpio-controller;
223 #gpio-cells = <1>; 330 #gpio-cells = <1>;
331 interrupt-controller;
332 #interrupt-cells = <2>;
224 reg = <0x5000 0x100>; 333 reg = <0x5000 0x100>;
225 st,bank-name = "PIO18"; 334 st,bank-name = "PIO18";
226 }; 335 };
@@ -233,6 +342,77 @@
233 }; 342 };
234 }; 343 };
235 }; 344 };
345
346 gmac0{
347 pinctrl_mii0: mii0 {
348 st,pins {
349 mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
350 txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
351
352 txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
353 txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
354 txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
355 txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
356
357 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
358 txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
359 crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
360 col = <&PIO15 3 ALT2 IN BYPASS 1000>;
361 mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>;
362 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
363
364 rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
365 rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
366 rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
367 rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
368 rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
369 rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
370 rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
371 phyclk = <&PIO13 5 ALT2 OUT NICLK 1000 CLK_A>;
372
373 };
374 };
375
376 pinctrl_gmii0: gmii0 {
377 st,pins {
378 mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
379 mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>;
380 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
381 txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
382
383 txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
384 txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
385 txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
386 txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
387 txd4 = <&PIO14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
388 txd5 = <&PIO14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
389 txd6 = <&PIO14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
390 txd7 = <&PIO14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
391
392 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
393 txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
394 crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
395 col = <&PIO15 3 ALT2 IN BYPASS 1000>;
396 rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
397 rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
398
399 rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
400 rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
401 rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
402 rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
403 rxd4 = <&PIO16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
404 rxd5 = <&PIO16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
405 rxd6 = <&PIO16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
406 rxd7 = <&PIO16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
407
408 rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
409 clk125 = <&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
410 phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>;
411
412
413 };
414 };
415 };
236 }; 416 };
237 417
238 pin-controller-left { 418 pin-controller-left {
@@ -240,23 +420,33 @@
240 #size-cells = <1>; 420 #size-cells = <1>;
241 compatible = "st,stih415-left-pinctrl"; 421 compatible = "st,stih415-left-pinctrl";
242 st,syscfg = <&syscfg_left>; 422 st,syscfg = <&syscfg_left>;
423 reg = <0xfd6bf080 0x4>;
424 reg-names = "irqmux";
425 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
426 interrupts-names = "irqmux";
243 ranges = <0 0xfd6b0000 0x3000>; 427 ranges = <0 0xfd6b0000 0x3000>;
244 428
245 PIO100: gpio@fd6b0000 { 429 PIO100: gpio@fd6b0000 {
246 gpio-controller; 430 gpio-controller;
247 #gpio-cells = <1>; 431 #gpio-cells = <1>;
432 interrupt-controller;
433 #interrupt-cells = <2>;
248 reg = <0 0x100>; 434 reg = <0 0x100>;
249 st,bank-name = "PIO100"; 435 st,bank-name = "PIO100";
250 }; 436 };
251 PIO101: gpio@fd6b1000 { 437 PIO101: gpio@fd6b1000 {
252 gpio-controller; 438 gpio-controller;
253 #gpio-cells = <1>; 439 #gpio-cells = <1>;
440 interrupt-controller;
441 #interrupt-cells = <2>;
254 reg = <0x1000 0x100>; 442 reg = <0x1000 0x100>;
255 st,bank-name = "PIO101"; 443 st,bank-name = "PIO101";
256 }; 444 };
257 PIO102: gpio@fd6b2000 { 445 PIO102: gpio@fd6b2000 {
258 gpio-controller; 446 gpio-controller;
259 #gpio-cells = <1>; 447 #gpio-cells = <1>;
448 interrupt-controller;
449 #interrupt-cells = <2>;
260 reg = <0x2000 0x100>; 450 reg = <0x2000 0x100>;
261 st,bank-name = "PIO102"; 451 st,bank-name = "PIO102";
262 }; 452 };
@@ -267,35 +457,49 @@
267 #size-cells = <1>; 457 #size-cells = <1>;
268 compatible = "st,stih415-right-pinctrl"; 458 compatible = "st,stih415-right-pinctrl";
269 st,syscfg = <&syscfg_right>; 459 st,syscfg = <&syscfg_right>;
460 reg = <0xfd33f080 0x4>;
461 reg-names = "irqmux";
462 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
463 interrupts-names = "irqmux";
270 ranges = <0 0xfd330000 0x5000>; 464 ranges = <0 0xfd330000 0x5000>;
271 465
272 PIO103: gpio@fd330000 { 466 PIO103: gpio@fd330000 {
273 gpio-controller; 467 gpio-controller;
274 #gpio-cells = <1>; 468 #gpio-cells = <1>;
469 interrupt-controller;
470 #interrupt-cells = <2>;
275 reg = <0 0x100>; 471 reg = <0 0x100>;
276 st,bank-name = "PIO103"; 472 st,bank-name = "PIO103";
277 }; 473 };
278 PIO104: gpio@fd331000 { 474 PIO104: gpio@fd331000 {
279 gpio-controller; 475 gpio-controller;
280 #gpio-cells = <1>; 476 #gpio-cells = <1>;
477 interrupt-controller;
478 #interrupt-cells = <2>;
281 reg = <0x1000 0x100>; 479 reg = <0x1000 0x100>;
282 st,bank-name = "PIO104"; 480 st,bank-name = "PIO104";
283 }; 481 };
284 PIO105: gpio@fd332000 { 482 PIO105: gpio@fd332000 {
285 gpio-controller; 483 gpio-controller;
286 #gpio-cells = <1>; 484 #gpio-cells = <1>;
485 interrupt-controller;
486 #interrupt-cells = <2>;
287 reg = <0x2000 0x100>; 487 reg = <0x2000 0x100>;
288 st,bank-name = "PIO105"; 488 st,bank-name = "PIO105";
289 }; 489 };
290 PIO106: gpio@fd333000 { 490 PIO106: gpio@fd333000 {
291 gpio-controller; 491 gpio-controller;
292 #gpio-cells = <1>; 492 #gpio-cells = <1>;
493 interrupt-controller;
494 #interrupt-cells = <2>;
293 reg = <0x3000 0x100>; 495 reg = <0x3000 0x100>;
294 st,bank-name = "PIO106"; 496 st,bank-name = "PIO106";
295 }; 497 };
296 PIO107: gpio@fd334000 { 498 PIO107: gpio@fd334000 {
297 gpio-controller; 499 gpio-controller;
298 #gpio-cells = <1>; 500 #gpio-cells = <1>;
501 interrupt-controller;
502 #interrupt-cells = <2>;
299 reg = <0x4000 0x100>; 503 reg = <0x4000 0x100>;
300 st,bank-name = "PIO107"; 504 st,bank-name = "PIO107";
301 }; 505 };
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index d9c7dd1d95a4..d89064c20c8a 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -10,6 +10,7 @@
10#include "stih415-clock.dtsi" 10#include "stih415-clock.dtsi"
11#include "stih415-pinctrl.dtsi" 11#include "stih415-pinctrl.dtsi"
12#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/reset-controller/stih415-resets.h>
13/ { 14/ {
14 15
15 L2: cache-controller { 16 L2: cache-controller {
@@ -28,6 +29,16 @@
28 ranges; 29 ranges;
29 compatible = "simple-bus"; 30 compatible = "simple-bus";
30 31
32 powerdown: powerdown-controller {
33 #reset-cells = <1>;
34 compatible = "st,stih415-powerdown";
35 };
36
37 softreset: softreset-controller {
38 #reset-cells = <1>;
39 compatible = "st,stih415-softreset";
40 };
41
31 syscfg_sbc: sbc-syscfg@fe600000{ 42 syscfg_sbc: sbc-syscfg@fe600000{
32 compatible = "st,stih415-sbc-syscfg", "syscon"; 43 compatible = "st,stih415-sbc-syscfg", "syscon";
33 reg = <0xfe600000 0xb4>; 44 reg = <0xfe600000 0xb4>;
@@ -136,5 +147,64 @@
136 147
137 status = "disabled"; 148 status = "disabled";
138 }; 149 };
150
151 ethernet0: dwmac@fe810000 {
152 device_type = "network";
153 compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
154 status = "disabled";
155
156 reg = <0xfe810000 0x8000>, <0x148 0x4>;
157 reg-names = "stmmaceth", "sti-ethconf";
158
159 interrupts = <0 147 0>, <0 148 0>, <0 149 0>;
160 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
161 resets = <&softreset STIH415_ETH0_SOFTRESET>;
162 reset-names = "stmmaceth";
163
164 snps,pbl = <32>;
165 snps,mixed-burst;
166 snps,force_sf_dma_mode;
167
168 st,syscon = <&syscfg_rear>;
169
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_mii0>;
172 clock-names = "stmmaceth";
173 clocks = <&CLKS_GMAC0_PHY>;
174 };
175
176 ethernet1: dwmac@fef08000 {
177 device_type = "network";
178 compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
179 status = "disabled";
180 reg = <0xfef08000 0x8000>, <0x74 0x4>;
181 reg-names = "stmmaceth", "sti-ethconf";
182 interrupts = <0 150 0>, <0 151 0>, <0 152 0>;
183 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
184
185 snps,pbl = <32>;
186 snps,mixed-burst;
187 snps,force_sf_dma_mode;
188
189 st,syscon = <&syscfg_sbc>;
190
191 resets = <&softreset STIH415_ETH1_SOFTRESET>;
192 reset-names = "stmmaceth";
193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_mii1>;
195 clock-names = "stmmaceth";
196 clocks = <&CLKS_ETH1_PHY>;
197 };
198
199 rc: rc@fe518000 {
200 compatible = "st,comms-irb";
201 reg = <0xfe518000 0x234>;
202 interrupts = <0 203 0>;
203 clocks = <&CLK_SYSIN>;
204 rx-mode = "infrared";
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_ir>;
207 resets = <&softreset STIH415_IRB_SOFTRESET>;
208 };
139 }; 209 };
140}; 210};
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi
index 7026bf1158d8..a6942c75cbbb 100644
--- a/arch/arm/boot/dts/stih416-clock.dtsi
+++ b/arch/arm/boot/dts/stih416-clock.dtsi
@@ -37,5 +37,19 @@
37 clock-frequency = <100000000>; 37 clock-frequency = <100000000>;
38 clock-output-names = "CLK_S_ICN_REG_0"; 38 clock-output-names = "CLK_S_ICN_REG_0";
39 }; 39 };
40
41 CLK_S_GMAC0_PHY: clockgenA1@7 {
42 #clock-cells = <0>;
43 compatible = "fixed-clock";
44 clock-frequency = <25000000>;
45 clock-output-names = "CLK_S_GMAC0_PHY";
46 };
47
48 CLK_S_ETH1_PHY: clockgenA0@7 {
49 #clock-cells = <0>;
50 compatible = "fixed-clock";
51 clock-frequency = <25000000>;
52 clock-output-names = "CLK_S_ETH1_PHY";
53 };
40 }; 54 };
41}; 55};
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index b29ff4ba542c..e7f8b5f4460a 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -8,6 +8,7 @@
8 * publishhed by the Free Software Foundation. 8 * publishhed by the Free Software Foundation.
9 */ 9 */
10#include "st-pincfg.h" 10#include "st-pincfg.h"
11#include <dt-bindings/interrupt-controller/arm-gic.h>
11/ { 12/ {
12 13
13 aliases { 14 aliases {
@@ -49,46 +50,69 @@
49 #size-cells = <1>; 50 #size-cells = <1>;
50 compatible = "st,stih416-sbc-pinctrl"; 51 compatible = "st,stih416-sbc-pinctrl";
51 st,syscfg = <&syscfg_sbc>; 52 st,syscfg = <&syscfg_sbc>;
53 reg = <0xfe61f080 0x4>;
54 reg-names = "irqmux";
55 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
56 interrupts-names = "irqmux";
52 ranges = <0 0xfe610000 0x6000>; 57 ranges = <0 0xfe610000 0x6000>;
53 58
54 PIO0: gpio@fe610000 { 59 PIO0: gpio@fe610000 {
55 gpio-controller; 60 gpio-controller;
56 #gpio-cells = <1>; 61 #gpio-cells = <1>;
62 interrupt-controller;
63 #interrupt-cells = <2>;
57 reg = <0 0x100>; 64 reg = <0 0x100>;
58 st,bank-name = "PIO0"; 65 st,bank-name = "PIO0";
59 }; 66 };
60 PIO1: gpio@fe611000 { 67 PIO1: gpio@fe611000 {
61 gpio-controller; 68 gpio-controller;
62 #gpio-cells = <1>; 69 #gpio-cells = <1>;
70 interrupt-controller;
71 #interrupt-cells = <2>;
63 reg = <0x1000 0x100>; 72 reg = <0x1000 0x100>;
64 st,bank-name = "PIO1"; 73 st,bank-name = "PIO1";
65 }; 74 };
66 PIO2: gpio@fe612000 { 75 PIO2: gpio@fe612000 {
67 gpio-controller; 76 gpio-controller;
68 #gpio-cells = <1>; 77 #gpio-cells = <1>;
78 interrupt-controller;
79 #interrupt-cells = <2>;
69 reg = <0x2000 0x100>; 80 reg = <0x2000 0x100>;
70 st,bank-name = "PIO2"; 81 st,bank-name = "PIO2";
71 }; 82 };
72 PIO3: gpio@fe613000 { 83 PIO3: gpio@fe613000 {
73 gpio-controller; 84 gpio-controller;
74 #gpio-cells = <1>; 85 #gpio-cells = <1>;
86 interrupt-controller;
87 #interrupt-cells = <2>;
75 reg = <0x3000 0x100>; 88 reg = <0x3000 0x100>;
76 st,bank-name = "PIO3"; 89 st,bank-name = "PIO3";
77 }; 90 };
78 PIO4: gpio@fe614000 { 91 PIO4: gpio@fe614000 {
79 gpio-controller; 92 gpio-controller;
80 #gpio-cells = <1>; 93 #gpio-cells = <1>;
94 interrupt-controller;
95 #interrupt-cells = <2>;
81 reg = <0x4000 0x100>; 96 reg = <0x4000 0x100>;
82 st,bank-name = "PIO4"; 97 st,bank-name = "PIO4";
83 }; 98 };
84 PIO40: gpio@fe615000 { 99 PIO40: gpio@fe615000 {
85 gpio-controller; 100 gpio-controller;
86 #gpio-cells = <1>; 101 #gpio-cells = <1>;
102 interrupt-controller;
103 #interrupt-cells = <2>;
87 reg = <0x5000 0x100>; 104 reg = <0x5000 0x100>;
88 st,bank-name = "PIO40"; 105 st,bank-name = "PIO40";
89 st,retime-pin-mask = <0x7f>; 106 st,retime-pin-mask = <0x7f>;
90 }; 107 };
91 108
109 rc{
110 pinctrl_ir: ir0 {
111 st,pins {
112 ir = <&PIO4 0 ALT2 IN>;
113 };
114 };
115 };
92 sbc_serial1 { 116 sbc_serial1 {
93 pinctrl_sbc_serial1: sbc_serial1 { 117 pinctrl_sbc_serial1: sbc_serial1 {
94 st,pins { 118 st,pins {
@@ -115,6 +139,58 @@
115 }; 139 };
116 }; 140 };
117 }; 141 };
142
143 gmac1 {
144 pinctrl_mii1: mii1 {
145 st,pins {
146 txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
147 txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
148 txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
149 txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
150 txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
151 txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
152 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
153 col = <&PIO0 7 ALT1 IN BYPASS 1000>;
154
155 mdio = <&PIO1 0 ALT1 OUT BYPASS 1500>;
156 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
157 crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
158 mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
159 rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
160 rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
161 rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
162 rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
163
164 rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
165 rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
166 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
167 phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>;
168 };
169 };
170 pinctrl_rgmii1: rgmii1-0 {
171 st,pins {
172 txd0 = <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>;
173 txd1 = <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>;
174 txd2 = <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>;
175 txd3 = <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>;
176 txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
177 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
178
179 mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
180 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
181 rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>;
182 rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>;
183 rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>;
184 rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>;
185
186 rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
187 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
188 phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
189
190 clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
191 };
192 };
193 };
118 }; 194 };
119 195
120 pin-controller-front { 196 pin-controller-front {
@@ -122,65 +198,89 @@
122 #size-cells = <1>; 198 #size-cells = <1>;
123 compatible = "st,stih416-front-pinctrl"; 199 compatible = "st,stih416-front-pinctrl";
124 st,syscfg = <&syscfg_front>; 200 st,syscfg = <&syscfg_front>;
201 reg = <0xfee0f080 0x4>;
202 reg-names = "irqmux";
203 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
204 interrupts-names = "irqmux";
125 ranges = <0 0xfee00000 0x10000>; 205 ranges = <0 0xfee00000 0x10000>;
126 206
127 PIO5: gpio@fee00000 { 207 PIO5: gpio@fee00000 {
128 gpio-controller; 208 gpio-controller;
129 #gpio-cells = <1>; 209 #gpio-cells = <1>;
210 interrupt-controller;
211 #interrupt-cells = <2>;
130 reg = <0 0x100>; 212 reg = <0 0x100>;
131 st,bank-name = "PIO5"; 213 st,bank-name = "PIO5";
132 }; 214 };
133 PIO6: gpio@fee01000 { 215 PIO6: gpio@fee01000 {
134 gpio-controller; 216 gpio-controller;
135 #gpio-cells = <1>; 217 #gpio-cells = <1>;
218 interrupt-controller;
219 #interrupt-cells = <2>;
136 reg = <0x1000 0x100>; 220 reg = <0x1000 0x100>;
137 st,bank-name = "PIO6"; 221 st,bank-name = "PIO6";
138 }; 222 };
139 PIO7: gpio@fee02000 { 223 PIO7: gpio@fee02000 {
140 gpio-controller; 224 gpio-controller;
141 #gpio-cells = <1>; 225 #gpio-cells = <1>;
226 interrupt-controller;
227 #interrupt-cells = <2>;
142 reg = <0x2000 0x100>; 228 reg = <0x2000 0x100>;
143 st,bank-name = "PIO7"; 229 st,bank-name = "PIO7";
144 }; 230 };
145 PIO8: gpio@fee03000 { 231 PIO8: gpio@fee03000 {
146 gpio-controller; 232 gpio-controller;
147 #gpio-cells = <1>; 233 #gpio-cells = <1>;
234 interrupt-controller;
235 #interrupt-cells = <2>;
148 reg = <0x3000 0x100>; 236 reg = <0x3000 0x100>;
149 st,bank-name = "PIO8"; 237 st,bank-name = "PIO8";
150 }; 238 };
151 PIO9: gpio@fee04000 { 239 PIO9: gpio@fee04000 {
152 gpio-controller; 240 gpio-controller;
153 #gpio-cells = <1>; 241 #gpio-cells = <1>;
242 interrupt-controller;
243 #interrupt-cells = <2>;
154 reg = <0x4000 0x100>; 244 reg = <0x4000 0x100>;
155 st,bank-name = "PIO9"; 245 st,bank-name = "PIO9";
156 }; 246 };
157 PIO10: gpio@fee05000 { 247 PIO10: gpio@fee05000 {
158 gpio-controller; 248 gpio-controller;
159 #gpio-cells = <1>; 249 #gpio-cells = <1>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
160 reg = <0x5000 0x100>; 252 reg = <0x5000 0x100>;
161 st,bank-name = "PIO10"; 253 st,bank-name = "PIO10";
162 }; 254 };
163 PIO11: gpio@fee06000 { 255 PIO11: gpio@fee06000 {
164 gpio-controller; 256 gpio-controller;
165 #gpio-cells = <1>; 257 #gpio-cells = <1>;
258 interrupt-controller;
259 #interrupt-cells = <2>;
166 reg = <0x6000 0x100>; 260 reg = <0x6000 0x100>;
167 st,bank-name = "PIO11"; 261 st,bank-name = "PIO11";
168 }; 262 };
169 PIO12: gpio@fee07000 { 263 PIO12: gpio@fee07000 {
170 gpio-controller; 264 gpio-controller;
171 #gpio-cells = <1>; 265 #gpio-cells = <1>;
266 interrupt-controller;
267 #interrupt-cells = <2>;
172 reg = <0x7000 0x100>; 268 reg = <0x7000 0x100>;
173 st,bank-name = "PIO12"; 269 st,bank-name = "PIO12";
174 }; 270 };
175 PIO30: gpio@fee08000 { 271 PIO30: gpio@fee08000 {
176 gpio-controller; 272 gpio-controller;
177 #gpio-cells = <1>; 273 #gpio-cells = <1>;
274 interrupt-controller;
275 #interrupt-cells = <2>;
178 reg = <0x8000 0x100>; 276 reg = <0x8000 0x100>;
179 st,bank-name = "PIO30"; 277 st,bank-name = "PIO30";
180 }; 278 };
181 PIO31: gpio@fee09000 { 279 PIO31: gpio@fee09000 {
182 gpio-controller; 280 gpio-controller;
183 #gpio-cells = <1>; 281 #gpio-cells = <1>;
282 interrupt-controller;
283 #interrupt-cells = <2>;
184 reg = <0x9000 0x100>; 284 reg = <0x9000 0x100>;
185 st,bank-name = "PIO31"; 285 st,bank-name = "PIO31";
186 }; 286 };
@@ -217,41 +317,57 @@
217 #size-cells = <1>; 317 #size-cells = <1>;
218 compatible = "st,stih416-rear-pinctrl"; 318 compatible = "st,stih416-rear-pinctrl";
219 st,syscfg = <&syscfg_rear>; 319 st,syscfg = <&syscfg_rear>;
320 reg = <0xfe82f080 0x4>;
321 reg-names = "irqmux";
322 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
323 interrupts-names = "irqmux";
220 ranges = <0 0xfe820000 0x6000>; 324 ranges = <0 0xfe820000 0x6000>;
221 325
222 PIO13: gpio@fe820000 { 326 PIO13: gpio@fe820000 {
223 gpio-controller; 327 gpio-controller;
224 #gpio-cells = <1>; 328 #gpio-cells = <1>;
329 interrupt-controller;
330 #interrupt-cells = <2>;
225 reg = <0 0x100>; 331 reg = <0 0x100>;
226 st,bank-name = "PIO13"; 332 st,bank-name = "PIO13";
227 }; 333 };
228 PIO14: gpio@fe821000 { 334 PIO14: gpio@fe821000 {
229 gpio-controller; 335 gpio-controller;
230 #gpio-cells = <1>; 336 #gpio-cells = <1>;
337 interrupt-controller;
338 #interrupt-cells = <2>;
231 reg = <0x1000 0x100>; 339 reg = <0x1000 0x100>;
232 st,bank-name = "PIO14"; 340 st,bank-name = "PIO14";
233 }; 341 };
234 PIO15: gpio@fe822000 { 342 PIO15: gpio@fe822000 {
235 gpio-controller; 343 gpio-controller;
236 #gpio-cells = <1>; 344 #gpio-cells = <1>;
345 interrupt-controller;
346 #interrupt-cells = <2>;
237 reg = <0x2000 0x100>; 347 reg = <0x2000 0x100>;
238 st,bank-name = "PIO15"; 348 st,bank-name = "PIO15";
239 }; 349 };
240 PIO16: gpio@fe823000 { 350 PIO16: gpio@fe823000 {
241 gpio-controller; 351 gpio-controller;
242 #gpio-cells = <1>; 352 #gpio-cells = <1>;
353 interrupt-controller;
354 #interrupt-cells = <2>;
243 reg = <0x3000 0x100>; 355 reg = <0x3000 0x100>;
244 st,bank-name = "PIO16"; 356 st,bank-name = "PIO16";
245 }; 357 };
246 PIO17: gpio@fe824000 { 358 PIO17: gpio@fe824000 {
247 gpio-controller; 359 gpio-controller;
248 #gpio-cells = <1>; 360 #gpio-cells = <1>;
361 interrupt-controller;
362 #interrupt-cells = <2>;
249 reg = <0x4000 0x100>; 363 reg = <0x4000 0x100>;
250 st,bank-name = "PIO17"; 364 st,bank-name = "PIO17";
251 }; 365 };
252 PIO18: gpio@fe825000 { 366 PIO18: gpio@fe825000 {
253 gpio-controller; 367 gpio-controller;
254 #gpio-cells = <1>; 368 #gpio-cells = <1>;
369 interrupt-controller;
370 #interrupt-cells = <2>;
255 reg = <0x5000 0x100>; 371 reg = <0x5000 0x100>;
256 st,bank-name = "PIO18"; 372 st,bank-name = "PIO18";
257 st,retime-pin-mask = <0xf>; 373 st,retime-pin-mask = <0xf>;
@@ -265,6 +381,63 @@
265 }; 381 };
266 }; 382 };
267 }; 383 };
384
385 gmac0 {
386 pinctrl_mii0: mii0 {
387 st,pins {
388 mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
389 txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
390 txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
391 txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
392 txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
393 txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
394
395 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
396 txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
397 crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
398 col = <&PIO15 3 ALT2 IN BYPASS 1000>;
399 mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>;
400 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
401
402 rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
403 rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
404 rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
405 rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
406 rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
407 rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
408 rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
409 phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>;
410 };
411 };
412
413 pinctrl_gmii0: gmii0 {
414 st,pins {
415 };
416 };
417 pinctrl_rgmii0: rgmii0 {
418 st,pins {
419 phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>;
420 txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>;
421 txd0 = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>;
422 txd1 = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>;
423 txd2 = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>;
424 txd3 = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>;
425 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
426
427 mdio = <&PIO15 4 ALT2 OUT BYPASS 0>;
428 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
429
430 rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>;
431 rxd0 =<&PIO16 0 ALT2 IN DE_IO 500 CLK_A>;
432 rxd1 =<&PIO16 1 ALT2 IN DE_IO 500 CLK_A>;
433 rxd2 =<&PIO16 2 ALT2 IN DE_IO 500 CLK_A>;
434 rxd3 =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>;
435 rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
436
437 clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
438 };
439 };
440 };
268 }; 441 };
269 442
270 pin-controller-fvdp-fe { 443 pin-controller-fvdp-fe {
@@ -272,23 +445,33 @@
272 #size-cells = <1>; 445 #size-cells = <1>;
273 compatible = "st,stih416-fvdp-fe-pinctrl"; 446 compatible = "st,stih416-fvdp-fe-pinctrl";
274 st,syscfg = <&syscfg_fvdp_fe>; 447 st,syscfg = <&syscfg_fvdp_fe>;
448 reg = <0xfd6bf080 0x4>;
449 reg-names = "irqmux";
450 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
451 interrupts-names = "irqmux";
275 ranges = <0 0xfd6b0000 0x3000>; 452 ranges = <0 0xfd6b0000 0x3000>;
276 453
277 PIO100: gpio@fd6b0000 { 454 PIO100: gpio@fd6b0000 {
278 gpio-controller; 455 gpio-controller;
279 #gpio-cells = <1>; 456 #gpio-cells = <1>;
457 interrupt-controller;
458 #interrupt-cells = <2>;
280 reg = <0 0x100>; 459 reg = <0 0x100>;
281 st,bank-name = "PIO100"; 460 st,bank-name = "PIO100";
282 }; 461 };
283 PIO101: gpio@fd6b1000 { 462 PIO101: gpio@fd6b1000 {
284 gpio-controller; 463 gpio-controller;
285 #gpio-cells = <1>; 464 #gpio-cells = <1>;
465 interrupt-controller;
466 #interrupt-cells = <2>;
286 reg = <0x1000 0x100>; 467 reg = <0x1000 0x100>;
287 st,bank-name = "PIO101"; 468 st,bank-name = "PIO101";
288 }; 469 };
289 PIO102: gpio@fd6b2000 { 470 PIO102: gpio@fd6b2000 {
290 gpio-controller; 471 gpio-controller;
291 #gpio-cells = <1>; 472 #gpio-cells = <1>;
473 interrupt-controller;
474 #interrupt-cells = <2>;
292 reg = <0x2000 0x100>; 475 reg = <0x2000 0x100>;
293 st,bank-name = "PIO102"; 476 st,bank-name = "PIO102";
294 }; 477 };
@@ -299,29 +482,41 @@
299 #size-cells = <1>; 482 #size-cells = <1>;
300 compatible = "st,stih416-fvdp-lite-pinctrl"; 483 compatible = "st,stih416-fvdp-lite-pinctrl";
301 st,syscfg = <&syscfg_fvdp_lite>; 484 st,syscfg = <&syscfg_fvdp_lite>;
485 reg = <0xfd33f080 0x4>;
486 reg-names = "irqmux";
487 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
488 interrupts-names = "irqmux";
302 ranges = <0 0xfd330000 0x5000>; 489 ranges = <0 0xfd330000 0x5000>;
303 490
304 PIO103: gpio@fd330000 { 491 PIO103: gpio@fd330000 {
305 gpio-controller; 492 gpio-controller;
306 #gpio-cells = <1>; 493 #gpio-cells = <1>;
494 interrupt-controller;
495 #interrupt-cells = <2>;
307 reg = <0 0x100>; 496 reg = <0 0x100>;
308 st,bank-name = "PIO103"; 497 st,bank-name = "PIO103";
309 }; 498 };
310 PIO104: gpio@fd331000 { 499 PIO104: gpio@fd331000 {
311 gpio-controller; 500 gpio-controller;
312 #gpio-cells = <1>; 501 #gpio-cells = <1>;
502 interrupt-controller;
503 #interrupt-cells = <2>;
313 reg = <0x1000 0x100>; 504 reg = <0x1000 0x100>;
314 st,bank-name = "PIO104"; 505 st,bank-name = "PIO104";
315 }; 506 };
316 PIO105: gpio@fd332000 { 507 PIO105: gpio@fd332000 {
317 gpio-controller; 508 gpio-controller;
318 #gpio-cells = <1>; 509 #gpio-cells = <1>;
510 interrupt-controller;
511 #interrupt-cells = <2>;
319 reg = <0x2000 0x100>; 512 reg = <0x2000 0x100>;
320 st,bank-name = "PIO105"; 513 st,bank-name = "PIO105";
321 }; 514 };
322 PIO106: gpio@fd333000 { 515 PIO106: gpio@fd333000 {
323 gpio-controller; 516 gpio-controller;
324 #gpio-cells = <1>; 517 #gpio-cells = <1>;
518 interrupt-controller;
519 #interrupt-cells = <2>;
325 reg = <0x3000 0x100>; 520 reg = <0x3000 0x100>;
326 st,bank-name = "PIO106"; 521 st,bank-name = "PIO106";
327 }; 522 };
@@ -329,6 +524,8 @@
329 PIO107: gpio@fd334000 { 524 PIO107: gpio@fd334000 {
330 gpio-controller; 525 gpio-controller;
331 #gpio-cells = <1>; 526 #gpio-cells = <1>;
527 interrupt-controller;
528 #interrupt-cells = <2>;
332 reg = <0x4000 0x100>; 529 reg = <0x4000 0x100>;
333 st,bank-name = "PIO107"; 530 st,bank-name = "PIO107";
334 st,retime-pin-mask = <0xf>; 531 st,retime-pin-mask = <0xf>;
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index b7ab47b95816..8299a7b8fee8 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -10,6 +10,7 @@
10#include "stih416-clock.dtsi" 10#include "stih416-clock.dtsi"
11#include "stih416-pinctrl.dtsi" 11#include "stih416-pinctrl.dtsi"
12#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/reset-controller/stih416-resets.h>
13/ { 14/ {
14 L2: cache-controller { 15 L2: cache-controller {
15 compatible = "arm,pl310-cache"; 16 compatible = "arm,pl310-cache";
@@ -27,6 +28,16 @@
27 ranges; 28 ranges;
28 compatible = "simple-bus"; 29 compatible = "simple-bus";
29 30
31 powerdown: powerdown-controller {
32 #reset-cells = <1>;
33 compatible = "st,stih416-powerdown";
34 };
35
36 softreset: softreset-controller {
37 #reset-cells = <1>;
38 compatible = "st,stih416-softreset";
39 };
40
30 syscfg_sbc:sbc-syscfg@fe600000{ 41 syscfg_sbc:sbc-syscfg@fe600000{
31 compatible = "st,stih416-sbc-syscfg", "syscon"; 42 compatible = "st,stih416-sbc-syscfg", "syscon";
32 reg = <0xfe600000 0x1000>; 43 reg = <0xfe600000 0x1000>;
@@ -145,5 +156,61 @@
145 156
146 status = "disabled"; 157 status = "disabled";
147 }; 158 };
159
160 ethernet0: dwmac@fe810000 {
161 device_type = "network";
162 compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
163 status = "disabled";
164 reg = <0xfe810000 0x8000>, <0x8bc 0x4>;
165 reg-names = "stmmaceth", "sti-ethconf";
166
167 interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
168 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
169
170 snps,pbl = <32>;
171 snps,mixed-burst;
172
173 st,syscon = <&syscfg_rear>;
174 resets = <&softreset STIH416_ETH0_SOFTRESET>;
175 reset-names = "stmmaceth";
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_mii0>;
178 clock-names = "stmmaceth";
179 clocks = <&CLK_S_GMAC0_PHY>;
180 };
181
182 ethernet1: dwmac@fef08000 {
183 device_type = "network";
184 compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
185 status = "disabled";
186 reg = <0xfef08000 0x8000>, <0x7f0 0x4>;
187 reg-names = "stmmaceth", "sti-ethconf";
188 interrupts = <0 136 0>, <0 137 0>, <0 138 0>;
189 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
190
191 snps,pbl = <32>;
192 snps,mixed-burst;
193
194 st,syscon = <&syscfg_sbc>;
195
196 resets = <&softreset STIH416_ETH1_SOFTRESET>;
197 reset-names = "stmmaceth";
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_mii1>;
200 clock-names = "stmmaceth";
201 clocks = <&CLK_S_ETH1_PHY>;
202 };
203
204 rc: rc@fe518000 {
205 compatible = "st,comms-irb";
206 reg = <0xfe518000 0x234>;
207 interrupts = <0 203 0>;
208 rx-mode = "infrared";
209 clocks = <&CLK_SYSIN>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_ir>;
212 resets = <&softreset STIH416_IRB_SOFTRESET>;
213 };
214
148 }; 215 };
149}; 216};
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
index 1e6aa92772f5..bf65c49095af 100644
--- a/arch/arm/boot/dts/stih41x-b2000.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -20,6 +20,8 @@
20 20
21 aliases { 21 aliases {
22 ttyAS0 = &serial2; 22 ttyAS0 = &serial2;
23 ethernet0 = &ethernet0;
24 ethernet1 = &ethernet1;
23 }; 25 };
24 26
25 soc { 27 soc {
@@ -46,5 +48,25 @@
46 48
47 status = "okay"; 49 status = "okay";
48 }; 50 };
51
52 ethernet0: dwmac@fe810000 {
53 status = "okay";
54 phy-mode = "mii";
55 pinctrl-0 = <&pinctrl_mii0>;
56
57 snps,reset-gpio = <&PIO106 2>;
58 snps,reset-active-low;
59 snps,reset-delays-us = <0 10000 10000>;
60 };
61
62 ethernet1: dwmac@fef08000 {
63 status = "disabled";
64 phy-mode = "mii";
65 st,tx-retime-src = "txclk";
66
67 snps,reset-gpio = <&PIO4 7>;
68 snps,reset-active-low;
69 snps,reset-delays-us = <0 10000 10000>;
70 };
49 }; 71 };
50}; 72};
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
index 0ef0a69df8ea..3dc74c25a57b 100644
--- a/arch/arm/boot/dts/stih41x-b2020.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -19,6 +19,7 @@
19 19
20 aliases { 20 aliases {
21 ttyAS0 = &sbc_serial1; 21 ttyAS0 = &sbc_serial1;
22 ethernet1 = &ethernet1;
22 }; 23 };
23 soc { 24 soc {
24 sbc_serial1: serial@fe531000 { 25 sbc_serial1: serial@fe531000 {
@@ -60,5 +61,17 @@
60 i2c@fe541000 { 61 i2c@fe541000 {
61 status = "okay"; 62 status = "okay";
62 }; 63 };
64
65 ethernet1: dwmac@fef08000 {
66 status = "okay";
67 phy-mode = "rgmii-id";
68 max-speed = <1000>;
69 st,tx-retime-src = "clk_125";
70 snps,reset-gpio = <&PIO3 0>;
71 snps,reset-active-low;
72 snps,reset-delays-us = <0 10000 10000>;
73
74 pinctrl-0 = <&pinctrl_rgmii1>;
75 };
63 }; 76 };
64}; 77};
diff --git a/include/dt-bindings/reset-controller/stih415-resets.h b/include/dt-bindings/reset-controller/stih415-resets.h
new file mode 100644
index 000000000000..c2f8a66913c5
--- /dev/null
+++ b/include/dt-bindings/reset-controller/stih415-resets.h
@@ -0,0 +1,26 @@
1/*
2 * This header provides constants for the reset controller
3 * based peripheral powerdown requests on the STMicroelectronics
4 * STiH415 SoC.
5 */
6#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH415
7#define _DT_BINDINGS_RESET_CONTROLLER_STIH415
8
9#define STIH415_EMISS_POWERDOWN 0
10#define STIH415_NAND_POWERDOWN 1
11#define STIH415_KEYSCAN_POWERDOWN 2
12#define STIH415_USB0_POWERDOWN 3
13#define STIH415_USB1_POWERDOWN 4
14#define STIH415_USB2_POWERDOWN 5
15#define STIH415_SATA0_POWERDOWN 6
16#define STIH415_SATA1_POWERDOWN 7
17#define STIH415_PCIE_POWERDOWN 8
18
19#define STIH415_ETH0_SOFTRESET 0
20#define STIH415_ETH1_SOFTRESET 1
21#define STIH415_IRB_SOFTRESET 2
22#define STIH415_USB0_SOFTRESET 3
23#define STIH415_USB1_SOFTRESET 4
24#define STIH415_USB2_SOFTRESET 5
25
26#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH415 */
diff --git a/include/dt-bindings/reset-controller/stih416-resets.h b/include/dt-bindings/reset-controller/stih416-resets.h
new file mode 100644
index 000000000000..2127743f23e3
--- /dev/null
+++ b/include/dt-bindings/reset-controller/stih416-resets.h
@@ -0,0 +1,50 @@
1/*
2 * This header provides constants for the reset controller
3 * based peripheral powerdown requests on the STMicroelectronics
4 * STiH416 SoC.
5 */
6#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH416
7#define _DT_BINDINGS_RESET_CONTROLLER_STIH416
8
9#define STIH416_EMISS_POWERDOWN 0
10#define STIH416_NAND_POWERDOWN 1
11#define STIH416_KEYSCAN_POWERDOWN 2
12#define STIH416_USB0_POWERDOWN 3
13#define STIH416_USB1_POWERDOWN 4
14#define STIH416_USB2_POWERDOWN 5
15#define STIH416_USB3_POWERDOWN 6
16#define STIH416_SATA0_POWERDOWN 7
17#define STIH416_SATA1_POWERDOWN 8
18#define STIH416_PCIE0_POWERDOWN 9
19#define STIH416_PCIE1_POWERDOWN 10
20
21#define STIH416_ETH0_SOFTRESET 0
22#define STIH416_ETH1_SOFTRESET 1
23#define STIH416_IRB_SOFTRESET 2
24#define STIH416_USB0_SOFTRESET 3
25#define STIH416_USB1_SOFTRESET 4
26#define STIH416_USB2_SOFTRESET 5
27#define STIH416_USB3_SOFTRESET 6
28#define STIH416_SATA0_SOFTRESET 7
29#define STIH416_SATA1_SOFTRESET 8
30#define STIH416_PCIE0_SOFTRESET 9
31#define STIH416_PCIE1_SOFTRESET 10
32#define STIH416_AUD_DAC_SOFTRESET 11
33#define STIH416_HDTVOUT_SOFTRESET 12
34#define STIH416_VTAC_M_RX_SOFTRESET 13
35#define STIH416_VTAC_A_RX_SOFTRESET 14
36#define STIH416_SYNC_HD_SOFTRESET 15
37#define STIH416_SYNC_SD_SOFTRESET 16
38#define STIH416_BLITTER_SOFTRESET 17
39#define STIH416_GPU_SOFTRESET 18
40#define STIH416_VTAC_M_TX_SOFTRESET 19
41#define STIH416_VTAC_A_TX_SOFTRESET 20
42#define STIH416_VTG_AUX_SOFTRESET 21
43#define STIH416_JPEG_DEC_SOFTRESET 22
44#define STIH416_HVA_SOFTRESET 23
45#define STIH416_COMPO_M_SOFTRESET 24
46#define STIH416_COMPO_A_SOFTRESET 25
47#define STIH416_VP8_DEC_SOFTRESET 26
48#define STIH416_VTG_MAIN_SOFTRESET 27
49
50#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH416 */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 00:33:00 -0400