aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorHisashi Nakamura <hisashi.nakamura.ak@renesas.com>2015-06-05 18:34:48 -0400
committerLinus Walleij <linus.walleij@linaro.org>2015-06-16 04:53:20 -0400
commit43c4436e2f1890a7b28dc0f0d901866cda99a08c (patch)
tree99565380a43103de95967f605fc2371e31f50f60
parent323de9efdf3e75d1dfb48003a52e59d6d9d4c7a5 (diff)
pinctrl: sh-pfc: add R8A7794 PFC support
Add PFC support for the R8A7794 SoC including pin groups for some on-chip devices such as ETH, I2C, INTC, MSIOF, QSPI, [H]SCIF... Sergei: squashed together several patches, fixed the MLB_CLK typo, added IRQ4.. IRQ9 pin groups, fixed IRQn comments, added ETH B pin group names, removed stray new line and fixed typos in the comments in the pinmux_config_regs[] initializer, removed the platform device ID, took into account limited number of signals in the GPIO1/5/6 controllers, added reasonable and removed unreasonable copyrights, modified the bindings document, renamed, added changelog. Changes in version 5: - resolved rejects, refreshed the patch; - added Laurent Pinchart's ACK. Changes in version 4: - reused the PORT_GP_26() macro to #define PORT_GP_28(). Changes in version 3: - removed the platform device ID; - added PORT_GP_26() and PORT_GP_28() macros, used them for GPIO1/5/6 in the CPU_ALL_PORT() macro. Changes in version 2: - rebased the patch. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt1
-rw-r--r--drivers/pinctrl/sh-pfc/Kconfig5
-rw-r--r--drivers/pinctrl/sh-pfc/Makefile1
-rw-r--r--drivers/pinctrl/sh-pfc/core.c6
-rw-r--r--drivers/pinctrl/sh-pfc/core.h1
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7794.c4008
6 files changed, 4022 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
index 6bcf851b6779..51cee44fc140 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -18,6 +18,7 @@ Required Properties:
18 - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. 18 - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
19 - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller. 19 - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
20 - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller. 20 - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.
21 - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
21 - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. 22 - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
22 23
23 - reg: Base address and length of each memory resource used by the pin 24 - reg: Base address and length of each memory resource used by the pin
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index 5d570fdf6065..8e024c9c9115 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -60,6 +60,11 @@ config PINCTRL_PFC_R8A7793
60 depends on ARCH_R8A7793 60 depends on ARCH_R8A7793
61 select PINCTRL_SH_PFC 61 select PINCTRL_SH_PFC
62 62
63config PINCTRL_PFC_R8A7794
64 def_bool y
65 depends on ARCH_R8A7794
66 select PINCTRL_SH_PFC
67
63config PINCTRL_PFC_SH7203 68config PINCTRL_PFC_SH7203
64 def_bool y 69 def_bool y
65 depends on CPU_SUBTYPE_SH7203 70 depends on CPU_SUBTYPE_SH7203
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 11eefcb71ec9..ea2a60ef122a 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o
11obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o 11obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
12obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o 12obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
13obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o 13obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o
14obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
14obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o 15obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
15obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o 16obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
16obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o 17obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 96556362b28f..865d235612c5 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -487,6 +487,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
487 .data = &r8a7793_pinmux_info, 487 .data = &r8a7793_pinmux_info,
488 }, 488 },
489#endif 489#endif
490#ifdef CONFIG_PINCTRL_PFC_R8A7794
491 {
492 .compatible = "renesas,pfc-r8a7794",
493 .data = &r8a7794_pinmux_info,
494 },
495#endif
490#ifdef CONFIG_PINCTRL_PFC_SH73A0 496#ifdef CONFIG_PINCTRL_PFC_SH73A0
491 { 497 {
492 .compatible = "renesas,pfc-sh73a0", 498 .compatible = "renesas,pfc-sh73a0",
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index b151b771e876..4c3c37bf7161 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -72,6 +72,7 @@ extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
72extern const struct sh_pfc_soc_info r8a7790_pinmux_info; 72extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
73extern const struct sh_pfc_soc_info r8a7791_pinmux_info; 73extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
74extern const struct sh_pfc_soc_info r8a7793_pinmux_info; 74extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
75extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
75extern const struct sh_pfc_soc_info sh7203_pinmux_info; 76extern const struct sh_pfc_soc_info sh7203_pinmux_info;
76extern const struct sh_pfc_soc_info sh7264_pinmux_info; 77extern const struct sh_pfc_soc_info sh7264_pinmux_info;
77extern const struct sh_pfc_soc_info sh7269_pinmux_info; 78extern const struct sh_pfc_soc_info sh7269_pinmux_info;
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
new file mode 100644
index 000000000000..0e2686a2093c
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
@@ -0,0 +1,4008 @@
1/*
2 * r8a7794 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2015 Renesas Solutions Corp.
6 * Copyright (C) 2015 Cogent Embedded, Inc., <source@cogentembedded.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2
10 * as published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/platform_data/gpio-rcar.h>
15
16#include "core.h"
17#include "sh_pfc.h"
18
19#define PORT_GP_26(bank, fn, sfx) \
20 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
21 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
22 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
23 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
24 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
25 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
26 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
27 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
28 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
29 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
30 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
31 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
32 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx)
33
34#define PORT_GP_28(bank, fn, sfx) \
35 PORT_GP_26(bank, fn, sfx), \
36 PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx)
37
38#define CPU_ALL_PORT(fn, sfx) \
39 PORT_GP_32(0, fn, sfx), \
40 PORT_GP_26(1, fn, sfx), \
41 PORT_GP_32(2, fn, sfx), \
42 PORT_GP_32(3, fn, sfx), \
43 PORT_GP_32(4, fn, sfx), \
44 PORT_GP_28(5, fn, sfx), \
45 PORT_GP_26(6, fn, sfx)
46
47enum {
48 PINMUX_RESERVED = 0,
49
50 PINMUX_DATA_BEGIN,
51 GP_ALL(DATA),
52 PINMUX_DATA_END,
53
54 PINMUX_FUNCTION_BEGIN,
55 GP_ALL(FN),
56
57 /* GPSR0 */
58 FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
59 FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
60 FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
61 FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
62 FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
63 FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
64 FN_IP2_17_16,
65
66 /* GPSR1 */
67 FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
68 FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
69 FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
70 FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
71 FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
72
73 /* GPSR2 */
74 FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
75 FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
76 FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
77 FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
78 FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
79 FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
80 FN_IP6_5_4, FN_IP6_7_6,
81
82 /* GPSR3 */
83 FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
84 FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
85 FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
86 FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
87 FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
88 FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
89 FN_IP8_22_20,
90
91 /* GPSR4 */
92 FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
93 FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
94 FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
95 FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
96 FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
97 FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
98 FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
99
100 /* GPSR5 */
101 FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
102 FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
103 FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
104 FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
105 FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
106 FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
107
108 /* GPSR6 */
109 FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
110 FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
111 FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
112 FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
113 FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
114
115 /* IPSR0 */
116 FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
117 FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
118 FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
119 FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
120 FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
121 FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
122 FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
123 FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
124
125 /* IPSR1 */
126 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, FN_D7, FN_IRQ3, FN_TCLK1,
127 FN_PWM6_B, FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, FN_D9, FN_HSCIF2_HTX,
128 FN_I2C1_SDA_B, FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6,
129 FN_PWM5_C, FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
130 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, FN_D13,
131 FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B, FN_D14, FN_SCIFA1_RXD,
132 FN_IIC0_SCL_B, FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, FN_A0,
133 FN_SCIFB1_SCK, FN_PWM3_B, FN_A1, FN_SCIFB1_TXD, FN_A3, FN_SCIFB0_SCK,
134 FN_A4, FN_SCIFB0_TXD, FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
135 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
136
137 /* IPSR2 */
138 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, FN_A8, FN_MSIOF1_RXD,
139 FN_SCIFA0_RXD_B, FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, FN_A10,
140 FN_MSIOF1_SCK, FN_IIC1_SCL_B, FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B,
141 FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, FN_A13, FN_MSIOF1_SS2,
142 FN_SCIFA5_TXD_B, FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
143 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, FN_A16,
144 FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_VSP, FN_CAN_CLK_C,
145 FN_TPUTO2_B, FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
146 FN_AVB_AVTP_CAPTURE_B, FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E,
147 FN_CAN1_TX_B, FN_AVB_AVTP_MATCH_B, FN_A19, FN_MSIOF2_SS2, FN_PWM4,
148 FN_TPUTO2, FN_MOUT0, FN_A20, FN_SPCLK, FN_MOUT1,
149
150 /* IPSR3 */
151 FN_A21, FN_MOSI_IO0, FN_MOUT2, FN_A22, FN_MISO_IO1, FN_MOUT5,
152 FN_ATADIR1_N, FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N, FN_A24, FN_IO3,
153 FN_EX_WAIT2, FN_A25, FN_SSL, FN_ATARD1_N, FN_CS0_N, FN_VI1_DATA8,
154 FN_CS1_N_A26, FN_VI1_DATA9, FN_EX_CS0_N, FN_VI1_DATA10, FN_EX_CS1_N,
155 FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, FN_EX_CS2_N, FN_PWM0,
156 FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD,
157 FN_SDATA_B, FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
158 FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B, FN_EX_CS4_N,
159 FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_RIF0_D0, FN_FMCLK,
160 FN_SCIFB2_CTS_N, FN_SCKZ_B, FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E,
161 FN_TS_SPSYNC_B, FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B,
162 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, FN_MTS_N_B,
163 FN_RD_N, FN_ATACS11_N, FN_RD_WR_N, FN_ATAG1_N,
164
165 /* IPSR4 */
166 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, FN_DU0_DR0,
167 FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, FN_CC50_STATE0,
168 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, FN_CC50_STATE1,
169 FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, FN_DU0_DR3, FN_LCDOUT19,
170 FN_CC50_STATE3, FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, FN_DU0_DR5,
171 FN_LCDOUT21, FN_CC50_STATE5, FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6,
172 FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, FN_DU0_DG0, FN_LCDOUT8,
173 FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, FN_CC50_STATE8, FN_DU0_DG1, FN_LCDOUT9,
174 FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, FN_CC50_STATE9, FN_DU0_DG2, FN_LCDOUT10,
175 FN_CC50_STATE10, FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, FN_DU0_DG4,
176 FN_LCDOUT12, FN_CC50_STATE12,
177
178 /* IPSR5 */
179 FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, FN_DU0_DG6, FN_LCDOUT14,
180 FN_CC50_STATE14, FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, FN_DU0_DB0,
181 FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
182 FN_CC50_STATE16, FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
183 FN_CAN0_TX_C, FN_CC50_STATE17, FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18,
184 FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, FN_DU0_DB4, FN_LCDOUT4,
185 FN_CC50_STATE20, FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, FN_DU0_DB6,
186 FN_LCDOUT6, FN_CC50_STATE22, FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23,
187 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, FN_DU0_DOTCLKOUT0,
188 FN_QCLK, FN_CC50_STATE25, FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
189 FN_CC50_STATE26, FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27,
190
191 /* IPSR6 */
192 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28,
193 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
194 FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB,
195 FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0,
196 FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2,
197 FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4,
198 FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6,
199 FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB,
200 FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD,
201 FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N,
202 FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N,
203 FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN,
204 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK,
205 FN_ADIDATA, FN_AD_DI,
206
207 /* IPSR7 */
208 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0,
209 FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B,
210 FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3,
211 FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N,
212 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
213 FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
214 FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C,
215 FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C,
216 FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0,
217 FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B,
218 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
219 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
220 FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD,
221
222 /* IPSR8 */
223 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
224 FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C,
225 FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX,
226 FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B,
227 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
228 FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7,
229 FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
230 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
231 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
232 FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0,
233 FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD,
234 FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B,
235 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B,
236 FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C,
237 FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
238
239 /* IPSR9 */
240 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_RIF1_D1_B,
241 FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, FN_MSIOF0_SCK, FN_IRQ0,
242 FN_TS_SDATA, FN_DU1_DR4, FN_RIF1_SYNC, FN_TPUTO1_C, FN_MSIOF0_SYNC,
243 FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_RIF1_CLK, FN_BPFCLK_B, FN_MSIOF0_SS1,
244 FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_RIF1_D0, FN_FMCLK_B,
245 FN_RDS_CLK_B, FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
246 FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, FN_HSCIF1_HRX, FN_I2C4_SCL,
247 FN_PWM6, FN_DU1_DG0, FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
248 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B,
249 FN_SPEEDIN_B, FN_VSP_B, FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK,
250 FN_DU1_DG3, FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32,
251 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B,
252 FN_CAN_STEP0, FN_CC50_STATE33, FN_SCIF1_SCK, FN_PWM3, FN_TCLK2,
253 FN_DU1_DG5, FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34,
254
255 /* IPSR10 */
256 FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, FN_CAN_DEBUGOUT0,
257 FN_CC50_STATE35, FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
258 FN_CAN_DEBUGOUT1, FN_CC50_STATE36, FN_SCIF2_RXD, FN_IIC1_SCL,
259 FN_DU1_DB0, FN_SSI_SDATA2_B, FN_USB0_EXTLP, FN_CAN_DEBUGOUT2,
260 FN_CC50_STATE37, FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
261 FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, FN_SCIF2_SCK, FN_IRQ1,
262 FN_DU1_DB2, FN_SSI_WS9_B, FN_USB0_IDIN, FN_CAN_DEBUGOUT4,
263 FN_CC50_STATE39, FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
264 FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT,
265 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C,
266 FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C, FN_SCIF3_TXD,
267 FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B,
268 FN_CAN_DEBUGOUT7, FN_RDS_DATA_C, FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6,
269 FN_AUDIO_CLKC_C, FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, FN_I2C2_SDA,
270 FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, FN_CAN_DEBUGOUT9,
271 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10,
272
273 /* IPSR11 */
274 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
275 FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C,
276 FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B,
277 FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6,
278 FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
279 FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
280 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78,
281 FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78,
282 FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7,
283 FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N,
284 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
285 FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D,
286 FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B,
287 FN_ADICLK_B, FN_AD_CLK_B,
288
289 /* IPSR12 */
290 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
291 FN_AD_NCS_N_B, FN_DREQ1_N_B, FN_SSI_WS34, FN_MSIOF1_SS1_B,
292 FN_SCIFA1_RXD_C, FN_ADICHS1_B, FN_CAN1_RX_C, FN_DACK1_B, FN_SSI_SDATA3,
293 FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, FN_CAN1_TX_C,
294 FN_DREQ2_N, FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX, FN_SSI_WS4,
295 FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX, FN_SSI_SDATA4, FN_MLB_DAT,
296 FN_IERX_B, FN_IRD_SCK, FN_SSI_SDATA8, FN_SCIF1_SCK_B,
297 FN_PWM1_B, FN_IRQ9, FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, FN_SSI_SCK1,
298 FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
299 FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, FN_SSI_WS1, FN_SCIF1_TXD_B,
300 FN_IIC1_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH,
301 FN_ETH_RX_ER_B, FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA, FN_VI1_DATA1,
302 FN_ATAG0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2,
303 FN_MDATA, FN_ATAWR0_N, FN_ETH_RXD1_B,
304
305 /* IPSR13 */
306 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, FN_SCKZ,
307 FN_ATACS00_N, FN_ETH_LINK_B, FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B,
308 FN_SCIFA0_TXD_D, FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B,
309 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_MTS_N,
310 FN_EX_WAIT1, FN_ETH_TXD1_B, FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E,
311 FN_VI1_DATA6, FN_ATARD0_N, FN_ETH_TX_EN_B, FN_SSI_SDATA9,
312 FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, FN_ATADIR0_N,
313 FN_ETH_MAGIC_B, FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D,
314 FN_VI1_CLKENB, FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B,
315 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
316 FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B, FN_AUDIO_CLKC,
317 FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, FN_TS_SDEN_C,
318 FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D, FN_AUDIO_CLKOUT, FN_I2C4_SDA_B,
319 FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, FN_TS_SPSYNC_C, FN_RIF0_D1_B,
320 FN_FMIN_E, FN_RDS_DATA_D,
321
322 /* MOD_SEL */
323 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
324 FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1,
325 FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1,
326 FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0,
327 FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1,
328 FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0,
329 FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2,
330 FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1,
331 FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0,
332 FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4,
333 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
334 FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2,
335 FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1,
336 FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1,
337
338 /* MOD_SEL2 */
339 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0,
340 FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0,
341 FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0,
342 FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0,
343 FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0,
344 FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0,
345 FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
346 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1,
347 FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1,
348 FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1,
349 FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1,
350 FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1,
351 FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1,
352 FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
353 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1,
354 FN_SEL_RDS_2, FN_SEL_RDS_3,
355
356 /* MOD_SEL3 */
357 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
358 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
359 FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
360 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
361 FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
362 FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
363 FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
364 FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
365 FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
366 FN_SEL_SSI9_1,
367 PINMUX_FUNCTION_END,
368
369 PINMUX_MARK_BEGIN,
370 A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
371
372 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
373
374 SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
375 SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
376
377 SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
378 SD1_DATA2_MARK, SD1_DATA3_MARK,
379
380 /* IPSR0 */
381 SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
382 MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
383 SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
384 SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
385 MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
386 CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
387 CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
388 SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
389 SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
390 SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
391
392 /* IPSR1 */
393 D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK, D7_MARK, IRQ3_MARK,
394 TCLK1_MARK, PWM6_B_MARK, D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK,
395 D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK, D10_MARK,
396 HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
397 D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK,
398 D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK,
399 D13_MARK, SCIFA1_SCK_MARK, TANS1_MARK, PWM2_C_MARK, TCLK2_B_MARK,
400 D14_MARK, SCIFA1_RXD_MARK, IIC0_SCL_B_MARK, D15_MARK, SCIFA1_TXD_MARK,
401 IIC0_SDA_B_MARK, A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK, A1_MARK,
402 SCIFB1_TXD_MARK, A3_MARK, SCIFB0_SCK_MARK, A4_MARK, SCIFB0_TXD_MARK,
403 A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK, A6_MARK,
404 SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK,
405
406 /* IPSR2 */
407 A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK, A8_MARK, MSIOF1_RXD_MARK,
408 SCIFA0_RXD_B_MARK, A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK,
409 A10_MARK, MSIOF1_SCK_MARK, IIC1_SCL_B_MARK, A11_MARK, MSIOF1_SYNC_MARK,
410 IIC1_SDA_B_MARK, A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK,
411 A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK, A14_MARK, MSIOF2_RXD_MARK,
412 HSCIF0_HRX_B_MARK, DREQ1_N_MARK, A15_MARK, MSIOF2_TXD_MARK,
413 HSCIF0_HTX_B_MARK, DACK1_MARK, A16_MARK, MSIOF2_SCK_MARK,
414 HSCIF0_HSCK_B_MARK, SPEEDIN_MARK, VSP_MARK, CAN_CLK_C_MARK,
415 TPUTO2_B_MARK, A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK,
416 CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_B_MARK, A18_MARK, MSIOF2_SS1_MARK,
417 SCIF4_TXD_E_MARK, CAN1_TX_B_MARK, AVB_AVTP_MATCH_B_MARK, A19_MARK,
418 MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK, MOUT0_MARK, A20_MARK,
419 SPCLK_MARK, MOUT1_MARK,
420
421 /* IPSR3 */
422 A21_MARK, MOSI_IO0_MARK, MOUT2_MARK, A22_MARK, MISO_IO1_MARK,
423 MOUT5_MARK, ATADIR1_N_MARK, A23_MARK, IO2_MARK, MOUT6_MARK,
424 ATAWR1_N_MARK, A24_MARK, IO3_MARK, EX_WAIT2_MARK, A25_MARK, SSL_MARK,
425 ATARD1_N_MARK, CS0_N_MARK, VI1_DATA8_MARK, CS1_N_A26_MARK,
426 VI1_DATA9_MARK, EX_CS0_N_MARK, VI1_DATA10_MARK, EX_CS1_N_MARK,
427 TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK, EX_CS2_N_MARK,
428 PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK, RIF0_SYNC_MARK,
429 TPUTO3_MARK, SCIFB2_TXD_MARK, SDATA_B_MARK, EX_CS3_N_MARK,
430 SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK, RIF0_CLK_MARK,
431 BPFCLK_MARK, SCIFB2_SCK_MARK, MDATA_B_MARK, EX_CS4_N_MARK,
432 SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK, RIF0_D0_MARK,
433 FMCLK_MARK, SCIFB2_CTS_N_MARK, SCKZ_B_MARK, EX_CS5_N_MARK,
434 SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK, RIF0_D1_MARK,
435 FMIN_MARK, SCIFB2_RTS_N_MARK, STM_N_B_MARK, BS_N_MARK, DRACK0_MARK,
436 PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK, MTS_N_B_MARK, RD_N_MARK,
437 ATACS11_N_MARK, RD_WR_N_MARK, ATAG1_N_MARK,
438
439 /* IPSR4 */
440 EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK, PWMFSW0_MARK,
441 DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK,
442 CC50_STATE0_MARK, DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK,
443 I2C2_SDA_D_MARK, CC50_STATE1_MARK, DU0_DR2_MARK, LCDOUT18_MARK,
444 CC50_STATE2_MARK, DU0_DR3_MARK, LCDOUT19_MARK, CC50_STATE3_MARK,
445 DU0_DR4_MARK, LCDOUT20_MARK, CC50_STATE4_MARK, DU0_DR5_MARK,
446 LCDOUT21_MARK, CC50_STATE5_MARK, DU0_DR6_MARK, LCDOUT22_MARK,
447 CC50_STATE6_MARK, DU0_DR7_MARK, LCDOUT23_MARK, CC50_STATE7_MARK,
448 DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK,
449 CC50_STATE8_MARK, DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK,
450 I2C3_SDA_D_MARK, CC50_STATE9_MARK, DU0_DG2_MARK, LCDOUT10_MARK,
451 CC50_STATE10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, CC50_STATE11_MARK,
452 DU0_DG4_MARK, LCDOUT12_MARK, CC50_STATE12_MARK,
453
454 /* IPSR5 */
455 DU0_DG5_MARK, LCDOUT13_MARK, CC50_STATE13_MARK, DU0_DG6_MARK,
456 LCDOUT14_MARK, CC50_STATE14_MARK, DU0_DG7_MARK, LCDOUT15_MARK,
457 CC50_STATE15_MARK, DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK,
458 I2C4_SCL_D_MARK, CAN0_RX_C_MARK, CC50_STATE16_MARK, DU0_DB1_MARK,
459 LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK, CAN0_TX_C_MARK,
460 CC50_STATE17_MARK, DU0_DB2_MARK, LCDOUT2_MARK, CC50_STATE18_MARK,
461 DU0_DB3_MARK, LCDOUT3_MARK, CC50_STATE19_MARK, DU0_DB4_MARK,
462 LCDOUT4_MARK, CC50_STATE20_MARK, DU0_DB5_MARK, LCDOUT5_MARK,
463 CC50_STATE21_MARK, DU0_DB6_MARK, LCDOUT6_MARK, CC50_STATE22_MARK,
464 DU0_DB7_MARK, LCDOUT7_MARK, CC50_STATE23_MARK, DU0_DOTCLKIN_MARK,
465 QSTVA_QVS_MARK, CC50_STATE24_MARK, DU0_DOTCLKOUT0_MARK,
466 QCLK_MARK, CC50_STATE25_MARK, DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
467 CC50_STATE26_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
468 CC50_STATE27_MARK,
469
470 /* IPSR6 */
471 DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK,
472 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK,
473 DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK,
474 CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK,
475 AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
476 VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK,
477 AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
478 VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK,
479 AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK,
480 I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK,
481 VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
482 AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK,
483 IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK,
484 I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK,
485 VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK,
486 ADIDATA_MARK, AD_DI_MARK,
487
488 /* IPSR7 */
489 ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK,
490 AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK,
491 MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK,
492 AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK,
493 CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK,
494 ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
495 AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK,
496 MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK,
497 ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
498 SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK,
499 IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK,
500 VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK,
501 SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK,
502 AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK,
503 SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
504 DREQ0_N_MARK, SCIFB1_RXD_MARK,
505
506 /* IPSR8 */
507 ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
508 AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
509 I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
510 HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
511 AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
512 SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
513 HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
514 AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
515 HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
516 I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
517 AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
518 SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
519 CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK,
520 DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK,
521 I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK,
522 TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK,
523 I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK,
524 FMCLK_C_MARK, RDS_CLK_MARK,
525
526 /* IPSR9 */
527 MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK,
528 RIF1_D1_B_MARK, TS_SPSYNC_D_MARK, FMIN_C_MARK, RDS_DATA_MARK,
529 MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, RIF1_SYNC_MARK,
530 TPUTO1_C_MARK, MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK,
531 RIF1_CLK_MARK, BPFCLK_B_MARK, MSIOF0_SS1_MARK, SCIFA0_RXD_MARK,
532 TS_SDEN_MARK, DU1_DR6_MARK, RIF1_D0_MARK, FMCLK_B_MARK, RDS_CLK_B_MARK,
533 MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK,
534 RIF1_D1_MARK, FMIN_B_MARK, RDS_DATA_B_MARK, HSCIF1_HRX_MARK,
535 I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK, HSCIF1_HTX_MARK,
536 I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK, HSCIF1_HSCK_MARK,
537 PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK, SPEEDIN_B_MARK,
538 VSP_B_MARK, HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK,
539 DU1_DG3_MARK, SSI_SCK1_B_MARK, CAN_DEBUG_HW_TRIGGER_MARK,
540 CC50_STATE32_MARK, HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK,
541 DU1_DG4_MARK, SSI_WS1_B_MARK, CAN_STEP0_MARK, CC50_STATE33_MARK,
542 SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK,
543 CAN_TXCLK_MARK, CC50_STATE34_MARK,
544
545 /* IPSR10 */
546 SCIF1_RXD_MARK, IIC0_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
547 CAN_DEBUGOUT0_MARK, CC50_STATE35_MARK, SCIF1_TXD_MARK, IIC0_SDA_MARK,
548 DU1_DG7_MARK, SSI_WS2_B_MARK, CAN_DEBUGOUT1_MARK, CC50_STATE36_MARK,
549 SCIF2_RXD_MARK, IIC1_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
550 USB0_EXTLP_MARK, CAN_DEBUGOUT2_MARK, CC50_STATE37_MARK, SCIF2_TXD_MARK,
551 IIC1_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK, USB0_OVC1_MARK,
552 CAN_DEBUGOUT3_MARK, CC50_STATE38_MARK, SCIF2_SCK_MARK, IRQ1_MARK,
553 DU1_DB2_MARK, SSI_WS9_B_MARK, USB0_IDIN_MARK, CAN_DEBUGOUT4_MARK,
554 CC50_STATE39_MARK, SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK,
555 DU1_DB3_MARK, SSI_SDATA9_B_MARK, TANS2_MARK, CAN_DEBUGOUT5_MARK,
556 CC50_OSCOUT_MARK, SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK,
557 DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK, CAN_DEBUGOUT6_MARK,
558 RDS_CLK_C_MARK, SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK,
559 DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK, CAN_DEBUGOUT7_MARK,
560 RDS_DATA_C_MARK, I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK,
561 AUDIO_CLKC_C_MARK, SSI_SDATA4_B_MARK, CAN_DEBUGOUT8_MARK, I2C2_SDA_MARK,
562 SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK, CAN_DEBUGOUT9_MARK,
563 SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK, CAN_DEBUGOUT10_MARK,
564
565 /* IPSR11 */
566 SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
567 CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK,
568 DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK,
569 SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK,
570 SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
571 DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK,
572 SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
573 CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK,
574 DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK,
575 DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK,
576 AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK,
577 MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK,
578 PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK,
579 ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK,
580 PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK,
581
582 /* IPSR12 */
583 SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK,
584 AD_NCS_N_B_MARK, DREQ1_N_B_MARK, SSI_WS34_MARK, MSIOF1_SS1_B_MARK,
585 SCIFA1_RXD_C_MARK, ADICHS1_B_MARK, CAN1_RX_C_MARK, DACK1_B_MARK,
586 SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK,
587 CAN1_TX_C_MARK, DREQ2_N_MARK, SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
588 IRD_TX_MARK, SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK, IRD_RX_MARK,
589 SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK, IRD_SCK_MARK,
590 SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
591 DACK2_MARK, ETH_MDIO_B_MARK, SSI_SCK1_MARK, SCIF1_RXD_B_MARK,
592 IIC1_SCL_C_MARK, VI1_CLK_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_MARK,
593 ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC1_SDA_C_MARK,
594 VI1_DATA0_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK, ETH_RX_ER_B_MARK,
595 SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, SDATA_MARK,
596 ATAG0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK,
597 VI1_DATA2_MARK, MDATA_MARK, ATAWR0_N_MARK, ETH_RXD1_B_MARK,
598
599 /* IPSR13 */
600 SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
601 SCKZ_MARK, ATACS00_N_MARK, ETH_LINK_B_MARK, SSI_SDATA2_MARK,
602 HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK, VI1_DATA4_MARK, STM_N_MARK,
603 ATACS10_N_MARK, ETH_REFCLK_B_MARK, SSI_SCK9_MARK, SCIF2_SCK_B_MARK,
604 PWM2_B_MARK, VI1_DATA5_MARK, MTS_N_MARK, EX_WAIT1_MARK,
605 ETH_TXD1_B_MARK, SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK,
606 VI1_DATA6_MARK, ATARD0_N_MARK, ETH_TX_EN_B_MARK, SSI_SDATA9_MARK,
607 SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK, ATADIR0_N_MARK,
608 ETH_MAGIC_B_MARK, AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK,
609 VI1_CLKENB_MARK, TS_SDATA_C_MARK, RIF0_SYNC_B_MARK, ETH_TXD0_B_MARK,
610 AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK,
611 TS_SCK_C_MARK, RIF0_CLK_B_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
612 AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK,
613 TS_SDEN_C_MARK, RIF0_D0_B_MARK, FMCLK_E_MARK, RDS_CLK_D_MARK,
614 AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK,
615 TS_SPSYNC_C_MARK, RIF0_D1_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK,
616 PINMUX_MARK_END,
617};
618
619static const u16 pinmux_data[] = {
620 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
621
622 PINMUX_DATA(A2_MARK, FN_A2),
623 PINMUX_DATA(WE0_N_MARK, FN_WE0_N),
624 PINMUX_DATA(WE1_N_MARK, FN_WE1_N),
625 PINMUX_DATA(DACK0_MARK, FN_DACK0),
626 PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
627 PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
628 PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
629 PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
630 PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK),
631 PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD),
632 PINMUX_DATA(SD0_DATA0_MARK, FN_SD0_DATA0),
633 PINMUX_DATA(SD0_DATA1_MARK, FN_SD0_DATA1),
634 PINMUX_DATA(SD0_DATA2_MARK, FN_SD0_DATA2),
635 PINMUX_DATA(SD0_DATA3_MARK, FN_SD0_DATA3),
636 PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD),
637 PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP),
638 PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK),
639 PINMUX_DATA(SD1_CMD_MARK, FN_SD1_CMD),
640 PINMUX_DATA(SD1_DATA0_MARK, FN_SD1_DATA0),
641 PINMUX_DATA(SD1_DATA1_MARK, FN_SD1_DATA1),
642 PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2),
643 PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3),
644
645 /* IPSR0 */
646 PINMUX_IPSR_DATA(IP0_0, SD1_CD),
647 PINMUX_IPSR_MODSEL_DATA(IP0_0, CAN0_RX, SEL_CAN0_0),
648 PINMUX_IPSR_DATA(IP0_9_8, SD1_WP),
649 PINMUX_IPSR_DATA(IP0_9_8, IRQ7),
650 PINMUX_IPSR_MODSEL_DATA(IP0_9_8, CAN0_TX, SEL_CAN0_0),
651 PINMUX_IPSR_DATA(IP0_10, MMC_CLK),
652 PINMUX_IPSR_DATA(IP0_10, SD2_CLK),
653 PINMUX_IPSR_DATA(IP0_11, MMC_CMD),
654 PINMUX_IPSR_DATA(IP0_11, SD2_CMD),
655 PINMUX_IPSR_DATA(IP0_12, MMC_D0),
656 PINMUX_IPSR_DATA(IP0_12, SD2_DATA0),
657 PINMUX_IPSR_DATA(IP0_13, MMC_D1),
658 PINMUX_IPSR_DATA(IP0_13, SD2_DATA1),
659 PINMUX_IPSR_DATA(IP0_14, MMC_D2),
660 PINMUX_IPSR_DATA(IP0_14, SD2_DATA2),
661 PINMUX_IPSR_DATA(IP0_15, MMC_D3),
662 PINMUX_IPSR_DATA(IP0_15, SD2_DATA3),
663 PINMUX_IPSR_DATA(IP0_16, MMC_D4),
664 PINMUX_IPSR_DATA(IP0_16, SD2_CD),
665 PINMUX_IPSR_DATA(IP0_17, MMC_D5),
666 PINMUX_IPSR_DATA(IP0_17, SD2_WP),
667 PINMUX_IPSR_DATA(IP0_19_18, MMC_D6),
668 PINMUX_IPSR_MODSEL_DATA(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
669 PINMUX_IPSR_MODSEL_DATA(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
670 PINMUX_IPSR_MODSEL_DATA(IP0_19_18, CAN1_RX, SEL_CAN1_0),
671 PINMUX_IPSR_DATA(IP0_21_20, MMC_D7),
672 PINMUX_IPSR_MODSEL_DATA(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
673 PINMUX_IPSR_MODSEL_DATA(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
674 PINMUX_IPSR_MODSEL_DATA(IP0_21_20, CAN1_TX, SEL_CAN1_0),
675 PINMUX_IPSR_DATA(IP0_23_22, D0),
676 PINMUX_IPSR_MODSEL_DATA(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
677 PINMUX_IPSR_DATA(IP0_23_22, IRQ4),
678 PINMUX_IPSR_DATA(IP0_24, D1),
679 PINMUX_IPSR_MODSEL_DATA(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
680 PINMUX_IPSR_DATA(IP0_25, D2),
681 PINMUX_IPSR_MODSEL_DATA(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
682 PINMUX_IPSR_DATA(IP0_27_26, D3),
683 PINMUX_IPSR_MODSEL_DATA(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
684 PINMUX_IPSR_MODSEL_DATA(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
685 PINMUX_IPSR_DATA(IP0_29_28, D4),
686 PINMUX_IPSR_MODSEL_DATA(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
687 PINMUX_IPSR_MODSEL_DATA(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
688 PINMUX_IPSR_DATA(IP0_31_30, D5),
689 PINMUX_IPSR_MODSEL_DATA(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
690 PINMUX_IPSR_MODSEL_DATA(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
691
692 /* IPSR1 */
693 PINMUX_IPSR_DATA(IP1_1_0, D6),
694 PINMUX_IPSR_MODSEL_DATA(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1),
695 PINMUX_IPSR_MODSEL_DATA(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3),
696 PINMUX_IPSR_DATA(IP1_3_2, D7),
697 PINMUX_IPSR_DATA(IP1_3_2, IRQ3),
698 PINMUX_IPSR_MODSEL_DATA(IP1_3_2, TCLK1, SEL_TMU_0),
699 PINMUX_IPSR_DATA(IP1_3_2, PWM6_B),
700 PINMUX_IPSR_DATA(IP1_5_4, D8),
701 PINMUX_IPSR_DATA(IP1_5_4, HSCIF2_HRX),
702 PINMUX_IPSR_MODSEL_DATA(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1),
703 PINMUX_IPSR_DATA(IP1_7_6, D9),
704 PINMUX_IPSR_DATA(IP1_7_6, HSCIF2_HTX),
705 PINMUX_IPSR_MODSEL_DATA(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1),
706 PINMUX_IPSR_DATA(IP1_10_8, D10),
707 PINMUX_IPSR_DATA(IP1_10_8, HSCIF2_HSCK),
708 PINMUX_IPSR_MODSEL_DATA(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2),
709 PINMUX_IPSR_DATA(IP1_10_8, IRQ6),
710 PINMUX_IPSR_DATA(IP1_10_8, PWM5_C),
711 PINMUX_IPSR_DATA(IP1_12_11, D11),
712 PINMUX_IPSR_DATA(IP1_12_11, HSCIF2_HCTS_N),
713 PINMUX_IPSR_MODSEL_DATA(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2),
714 PINMUX_IPSR_MODSEL_DATA(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3),
715 PINMUX_IPSR_DATA(IP1_14_13, D12),
716 PINMUX_IPSR_DATA(IP1_14_13, HSCIF2_HRTS_N),
717 PINMUX_IPSR_MODSEL_DATA(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2),
718 PINMUX_IPSR_MODSEL_DATA(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
719 PINMUX_IPSR_DATA(IP1_17_15, D13),
720 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
721 PINMUX_IPSR_DATA(IP1_17_15, TANS1),
722 PINMUX_IPSR_DATA(IP1_17_15, PWM2_C),
723 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, TCLK2_B, SEL_TMU_1),
724 PINMUX_IPSR_DATA(IP1_19_18, D14),
725 PINMUX_IPSR_MODSEL_DATA(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0),
726 PINMUX_IPSR_MODSEL_DATA(IP1_19_18, IIC0_SCL_B, SEL_IIC00_1),
727 PINMUX_IPSR_DATA(IP1_21_20, D15),
728 PINMUX_IPSR_MODSEL_DATA(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0),
729 PINMUX_IPSR_MODSEL_DATA(IP1_21_20, IIC0_SDA_B, SEL_IIC00_1),
730 PINMUX_IPSR_DATA(IP1_23_22, A0),
731 PINMUX_IPSR_DATA(IP1_23_22, SCIFB1_SCK),
732 PINMUX_IPSR_DATA(IP1_23_22, PWM3_B),
733 PINMUX_IPSR_DATA(IP1_24, A1),
734 PINMUX_IPSR_DATA(IP1_24, SCIFB1_TXD),
735 PINMUX_IPSR_DATA(IP1_26, A3),
736 PINMUX_IPSR_DATA(IP1_26, SCIFB0_SCK),
737 PINMUX_IPSR_DATA(IP1_27, A4),
738 PINMUX_IPSR_DATA(IP1_27, SCIFB0_TXD),
739 PINMUX_IPSR_DATA(IP1_29_28, A5),
740 PINMUX_IPSR_DATA(IP1_29_28, SCIFB0_RXD),
741 PINMUX_IPSR_DATA(IP1_29_28, PWM4_B),
742 PINMUX_IPSR_DATA(IP1_29_28, TPUTO3_C),
743 PINMUX_IPSR_DATA(IP1_31_30, A6),
744 PINMUX_IPSR_DATA(IP1_31_30, SCIFB0_CTS_N),
745 PINMUX_IPSR_MODSEL_DATA(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1),
746 PINMUX_IPSR_DATA(IP1_31_30, TPUTO2_C),
747
748 /* IPSR2 */
749 PINMUX_IPSR_DATA(IP2_1_0, A7),
750 PINMUX_IPSR_DATA(IP2_1_0, SCIFB0_RTS_N),
751 PINMUX_IPSR_MODSEL_DATA(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1),
752 PINMUX_IPSR_DATA(IP2_3_2, A8),
753 PINMUX_IPSR_MODSEL_DATA(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0),
754 PINMUX_IPSR_MODSEL_DATA(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1),
755 PINMUX_IPSR_DATA(IP2_5_4, A9),
756 PINMUX_IPSR_MODSEL_DATA(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0),
757 PINMUX_IPSR_MODSEL_DATA(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1),
758 PINMUX_IPSR_DATA(IP2_7_6, A10),
759 PINMUX_IPSR_MODSEL_DATA(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0),
760 PINMUX_IPSR_MODSEL_DATA(IP2_7_6, IIC1_SCL_B, SEL_IIC01_1),
761 PINMUX_IPSR_DATA(IP2_9_8, A11),
762 PINMUX_IPSR_MODSEL_DATA(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0),
763 PINMUX_IPSR_MODSEL_DATA(IP2_9_8, IIC1_SDA_B, SEL_IIC01_1),
764 PINMUX_IPSR_DATA(IP2_11_10, A12),
765 PINMUX_IPSR_MODSEL_DATA(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0),
766 PINMUX_IPSR_MODSEL_DATA(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1),
767 PINMUX_IPSR_DATA(IP2_13_12, A13),
768 PINMUX_IPSR_MODSEL_DATA(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0),
769 PINMUX_IPSR_MODSEL_DATA(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1),
770 PINMUX_IPSR_DATA(IP2_15_14, A14),
771 PINMUX_IPSR_MODSEL_DATA(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0),
772 PINMUX_IPSR_MODSEL_DATA(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1),
773 PINMUX_IPSR_MODSEL_DATA(IP2_15_14, DREQ1_N, SEL_LBS_0),
774 PINMUX_IPSR_DATA(IP2_17_16, A15),
775 PINMUX_IPSR_MODSEL_DATA(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0),
776 PINMUX_IPSR_MODSEL_DATA(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1),
777 PINMUX_IPSR_MODSEL_DATA(IP2_17_16, DACK1, SEL_LBS_0),
778 PINMUX_IPSR_DATA(IP2_20_18, A16),
779 PINMUX_IPSR_MODSEL_DATA(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
780 PINMUX_IPSR_MODSEL_DATA(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
781 PINMUX_IPSR_MODSEL_DATA(IP2_20_18, SPEEDIN, SEL_RSP_0),
782 PINMUX_IPSR_MODSEL_DATA(IP2_20_18, VSP, SEL_SPDM_0),
783 PINMUX_IPSR_MODSEL_DATA(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
784 PINMUX_IPSR_DATA(IP2_20_18, TPUTO2_B),
785 PINMUX_IPSR_DATA(IP2_23_21, A17),
786 PINMUX_IPSR_MODSEL_DATA(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
787 PINMUX_IPSR_MODSEL_DATA(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
788 PINMUX_IPSR_MODSEL_DATA(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
789 PINMUX_IPSR_MODSEL_DATA(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1),
790 PINMUX_IPSR_DATA(IP2_26_24, A18),
791 PINMUX_IPSR_MODSEL_DATA(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
792 PINMUX_IPSR_MODSEL_DATA(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
793 PINMUX_IPSR_MODSEL_DATA(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
794 PINMUX_IPSR_MODSEL_DATA(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1),
795 PINMUX_IPSR_DATA(IP2_29_27, A19),
796 PINMUX_IPSR_MODSEL_DATA(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
797 PINMUX_IPSR_DATA(IP2_29_27, PWM4),
798 PINMUX_IPSR_DATA(IP2_29_27, TPUTO2),
799 PINMUX_IPSR_DATA(IP2_29_27, MOUT0),
800 PINMUX_IPSR_DATA(IP2_31_30, A20),
801 PINMUX_IPSR_DATA(IP2_31_30, SPCLK),
802 PINMUX_IPSR_DATA(IP2_29_27, MOUT1),
803
804 /* IPSR3 */
805 PINMUX_IPSR_DATA(IP3_1_0, A21),
806 PINMUX_IPSR_DATA(IP3_1_0, MOSI_IO0),
807 PINMUX_IPSR_DATA(IP3_1_0, MOUT2),
808 PINMUX_IPSR_DATA(IP3_3_2, A22),
809 PINMUX_IPSR_DATA(IP3_3_2, MISO_IO1),
810 PINMUX_IPSR_DATA(IP3_3_2, MOUT5),
811 PINMUX_IPSR_DATA(IP3_3_2, ATADIR1_N),
812 PINMUX_IPSR_DATA(IP3_5_4, A23),
813 PINMUX_IPSR_DATA(IP3_5_4, IO2),
814 PINMUX_IPSR_DATA(IP3_5_4, MOUT6),
815 PINMUX_IPSR_DATA(IP3_5_4, ATAWR1_N),
816 PINMUX_IPSR_DATA(IP3_7_6, A24),
817 PINMUX_IPSR_DATA(IP3_7_6, IO3),
818 PINMUX_IPSR_DATA(IP3_7_6, EX_WAIT2),
819 PINMUX_IPSR_DATA(IP3_9_8, A25),
820 PINMUX_IPSR_DATA(IP3_9_8, SSL),
821 PINMUX_IPSR_DATA(IP3_9_8, ATARD1_N),
822 PINMUX_IPSR_DATA(IP3_10, CS0_N),
823 PINMUX_IPSR_DATA(IP3_10, VI1_DATA8),
824 PINMUX_IPSR_DATA(IP3_11, CS1_N_A26),
825 PINMUX_IPSR_DATA(IP3_11, VI1_DATA9),
826 PINMUX_IPSR_DATA(IP3_12, EX_CS0_N),
827 PINMUX_IPSR_DATA(IP3_12, VI1_DATA10),
828 PINMUX_IPSR_DATA(IP3_14_13, EX_CS1_N),
829 PINMUX_IPSR_DATA(IP3_14_13, TPUTO3_B),
830 PINMUX_IPSR_DATA(IP3_14_13, SCIFB2_RXD),
831 PINMUX_IPSR_DATA(IP3_14_13, VI1_DATA11),
832 PINMUX_IPSR_DATA(IP3_17_15, EX_CS2_N),
833 PINMUX_IPSR_DATA(IP3_17_15, PWM0),
834 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
835 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
836 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, RIF0_SYNC, SEL_DR0_0),
837 PINMUX_IPSR_DATA(IP3_17_15, TPUTO3),
838 PINMUX_IPSR_DATA(IP3_17_15, SCIFB2_TXD),
839 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SDATA_B, SEL_FSN_1),
840 PINMUX_IPSR_DATA(IP3_20_18, EX_CS3_N),
841 PINMUX_IPSR_MODSEL_DATA(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
842 PINMUX_IPSR_MODSEL_DATA(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
843 PINMUX_IPSR_MODSEL_DATA(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
844 PINMUX_IPSR_MODSEL_DATA(IP3_20_18, RIF0_CLK, SEL_DR0_0),
845 PINMUX_IPSR_MODSEL_DATA(IP3_20_18, BPFCLK, SEL_DARC_0),
846 PINMUX_IPSR_DATA(IP3_20_18, SCIFB2_SCK),
847 PINMUX_IPSR_MODSEL_DATA(IP3_20_18, MDATA_B, SEL_FSN_1),
848 PINMUX_IPSR_DATA(IP3_23_21, EX_CS4_N),
849 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
850 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
851 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
852 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, RIF0_D0, SEL_DR0_0),
853 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, FMCLK, SEL_DARC_0),
854 PINMUX_IPSR_DATA(IP3_23_21, SCIFB2_CTS_N),
855 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, SCKZ_B, SEL_FSN_1),
856 PINMUX_IPSR_DATA(IP3_26_24, EX_CS5_N),
857 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
858 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
859 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
860 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RIF0_D1, SEL_DR1_0),
861 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, FMIN, SEL_DARC_0),
862 PINMUX_IPSR_DATA(IP3_26_24, SCIFB2_RTS_N),
863 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, STM_N_B, SEL_FSN_1),
864 PINMUX_IPSR_DATA(IP3_29_27, BS_N),
865 PINMUX_IPSR_DATA(IP3_29_27, DRACK0),
866 PINMUX_IPSR_DATA(IP3_29_27, PWM1_C),
867 PINMUX_IPSR_DATA(IP3_29_27, TPUTO0_C),
868 PINMUX_IPSR_DATA(IP3_29_27, ATACS01_N),
869 PINMUX_IPSR_MODSEL_DATA(IP3_29_27, MTS_N_B, SEL_FSN_1),
870 PINMUX_IPSR_DATA(IP3_30, RD_N),
871 PINMUX_IPSR_DATA(IP3_30, ATACS11_N),
872 PINMUX_IPSR_DATA(IP3_31, RD_WR_N),
873 PINMUX_IPSR_DATA(IP3_31, ATAG1_N),
874
875 /* IPSR4 */
876 PINMUX_IPSR_DATA(IP4_1_0, EX_WAIT0),
877 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
878 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
879 PINMUX_IPSR_DATA(IP4_1_0, PWMFSW0),
880 PINMUX_IPSR_DATA(IP4_4_2, DU0_DR0),
881 PINMUX_IPSR_DATA(IP4_4_2, LCDOUT16),
882 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
883 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
884 PINMUX_IPSR_DATA(IP4_4_2, CC50_STATE0),
885 PINMUX_IPSR_DATA(IP4_7_5, DU0_DR1),
886 PINMUX_IPSR_DATA(IP4_7_5, LCDOUT17),
887 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
888 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
889 PINMUX_IPSR_DATA(IP4_9_8, CC50_STATE1),
890 PINMUX_IPSR_DATA(IP4_9_8, DU0_DR2),
891 PINMUX_IPSR_DATA(IP4_9_8, LCDOUT18),
892 PINMUX_IPSR_DATA(IP4_9_8, CC50_STATE2),
893 PINMUX_IPSR_DATA(IP4_11_10, DU0_DR3),
894 PINMUX_IPSR_DATA(IP4_11_10, LCDOUT19),
895 PINMUX_IPSR_DATA(IP4_11_10, CC50_STATE3),
896 PINMUX_IPSR_DATA(IP4_13_12, DU0_DR4),
897 PINMUX_IPSR_DATA(IP4_13_12, LCDOUT20),
898 PINMUX_IPSR_DATA(IP4_13_12, CC50_STATE4),
899 PINMUX_IPSR_DATA(IP4_15_14, DU0_DR5),
900 PINMUX_IPSR_DATA(IP4_15_14, LCDOUT21),
901 PINMUX_IPSR_DATA(IP4_15_14, CC50_STATE5),
902 PINMUX_IPSR_DATA(IP4_17_16, DU0_DR6),
903 PINMUX_IPSR_DATA(IP4_17_16, LCDOUT22),
904 PINMUX_IPSR_DATA(IP4_17_16, CC50_STATE6),
905 PINMUX_IPSR_DATA(IP4_19_18, DU0_DR7),
906 PINMUX_IPSR_DATA(IP4_19_18, LCDOUT23),
907 PINMUX_IPSR_DATA(IP4_19_18, CC50_STATE7),
908 PINMUX_IPSR_DATA(IP4_22_20, DU0_DG0),
909 PINMUX_IPSR_DATA(IP4_22_20, LCDOUT8),
910 PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
911 PINMUX_IPSR_MODSEL_DATA(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
912 PINMUX_IPSR_DATA(IP4_22_20, CC50_STATE8),
913 PINMUX_IPSR_DATA(IP4_25_23, DU0_DG1),
914 PINMUX_IPSR_DATA(IP4_25_23, LCDOUT9),
915 PINMUX_IPSR_MODSEL_DATA(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
916 PINMUX_IPSR_MODSEL_DATA(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
917 PINMUX_IPSR_DATA(IP4_25_23, CC50_STATE9),
918 PINMUX_IPSR_DATA(IP4_27_26, DU0_DG2),
919 PINMUX_IPSR_DATA(IP4_27_26, LCDOUT10),
920 PINMUX_IPSR_DATA(IP4_27_26, CC50_STATE10),
921 PINMUX_IPSR_DATA(IP4_29_28, DU0_DG3),
922 PINMUX_IPSR_DATA(IP4_29_28, LCDOUT11),
923 PINMUX_IPSR_DATA(IP4_29_28, CC50_STATE11),
924 PINMUX_IPSR_DATA(IP4_31_30, DU0_DG4),
925 PINMUX_IPSR_DATA(IP4_31_30, LCDOUT12),
926 PINMUX_IPSR_DATA(IP4_31_30, CC50_STATE12),
927
928 /* IPSR5 */
929 PINMUX_IPSR_DATA(IP5_1_0, DU0_DG5),
930 PINMUX_IPSR_DATA(IP5_1_0, LCDOUT13),
931 PINMUX_IPSR_DATA(IP5_1_0, CC50_STATE13),
932 PINMUX_IPSR_DATA(IP5_3_2, DU0_DG6),
933 PINMUX_IPSR_DATA(IP5_3_2, LCDOUT14),
934 PINMUX_IPSR_DATA(IP5_3_2, CC50_STATE14),
935 PINMUX_IPSR_DATA(IP5_5_4, DU0_DG7),
936 PINMUX_IPSR_DATA(IP5_5_4, LCDOUT15),
937 PINMUX_IPSR_DATA(IP5_5_4, CC50_STATE15),
938 PINMUX_IPSR_DATA(IP5_8_6, DU0_DB0),
939 PINMUX_IPSR_DATA(IP5_8_6, LCDOUT0),
940 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
941 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
942 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
943 PINMUX_IPSR_DATA(IP5_8_6, CC50_STATE16),
944 PINMUX_IPSR_DATA(IP5_11_9, DU0_DB1),
945 PINMUX_IPSR_DATA(IP5_11_9, LCDOUT1),
946 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
947 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
948 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
949 PINMUX_IPSR_DATA(IP5_11_9, CC50_STATE17),
950 PINMUX_IPSR_DATA(IP5_13_12, DU0_DB2),
951 PINMUX_IPSR_DATA(IP5_13_12, LCDOUT2),
952 PINMUX_IPSR_DATA(IP5_13_12, CC50_STATE18),
953 PINMUX_IPSR_DATA(IP5_15_14, DU0_DB3),
954 PINMUX_IPSR_DATA(IP5_15_14, LCDOUT3),
955 PINMUX_IPSR_DATA(IP5_15_14, CC50_STATE19),
956 PINMUX_IPSR_DATA(IP5_17_16, DU0_DB4),
957 PINMUX_IPSR_DATA(IP5_17_16, LCDOUT4),
958 PINMUX_IPSR_DATA(IP5_17_16, CC50_STATE20),
959 PINMUX_IPSR_DATA(IP5_19_18, DU0_DB5),
960 PINMUX_IPSR_DATA(IP5_19_18, LCDOUT5),
961 PINMUX_IPSR_DATA(IP5_19_18, CC50_STATE21),
962 PINMUX_IPSR_DATA(IP5_21_20, DU0_DB6),
963 PINMUX_IPSR_DATA(IP5_21_20, LCDOUT6),
964 PINMUX_IPSR_DATA(IP5_21_20, CC50_STATE22),
965 PINMUX_IPSR_DATA(IP5_23_22, DU0_DB7),
966 PINMUX_IPSR_DATA(IP5_23_22, LCDOUT7),
967 PINMUX_IPSR_DATA(IP5_23_22, CC50_STATE23),
968 PINMUX_IPSR_DATA(IP5_25_24, DU0_DOTCLKIN),
969 PINMUX_IPSR_DATA(IP5_25_24, QSTVA_QVS),
970 PINMUX_IPSR_DATA(IP5_25_24, CC50_STATE24),
971 PINMUX_IPSR_DATA(IP5_27_26, DU0_DOTCLKOUT0),
972 PINMUX_IPSR_DATA(IP5_27_26, QCLK),
973 PINMUX_IPSR_DATA(IP5_27_26, CC50_STATE25),
974 PINMUX_IPSR_DATA(IP5_29_28, DU0_DOTCLKOUT1),
975 PINMUX_IPSR_DATA(IP5_29_28, QSTVB_QVE),
976 PINMUX_IPSR_DATA(IP5_29_28, CC50_STATE26),
977 PINMUX_IPSR_DATA(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
978 PINMUX_IPSR_DATA(IP5_31_30, QSTH_QHS),
979 PINMUX_IPSR_DATA(IP5_31_30, CC50_STATE27),
980
981 /* IPSR6 */
982 PINMUX_IPSR_DATA(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
983 PINMUX_IPSR_DATA(IP6_1_0, QSTB_QHE),
984 PINMUX_IPSR_DATA(IP6_1_0, CC50_STATE28),
985 PINMUX_IPSR_DATA(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
986 PINMUX_IPSR_DATA(IP6_3_2, QCPV_QDE),
987 PINMUX_IPSR_DATA(IP6_3_2, CC50_STATE29),
988 PINMUX_IPSR_DATA(IP6_5_4, DU0_DISP),
989 PINMUX_IPSR_DATA(IP6_5_4, QPOLA),
990 PINMUX_IPSR_DATA(IP6_5_4, CC50_STATE30),
991 PINMUX_IPSR_DATA(IP6_7_6, DU0_CDE),
992 PINMUX_IPSR_DATA(IP6_7_6, QPOLB),
993 PINMUX_IPSR_DATA(IP6_7_6, CC50_STATE31),
994 PINMUX_IPSR_DATA(IP6_8, VI0_CLK),
995 PINMUX_IPSR_DATA(IP6_8, AVB_RX_CLK),
996 PINMUX_IPSR_DATA(IP6_9, VI0_DATA0_VI0_B0),
997 PINMUX_IPSR_DATA(IP6_9, AVB_RX_DV),
998 PINMUX_IPSR_DATA(IP6_10, VI0_DATA1_VI0_B1),
999 PINMUX_IPSR_DATA(IP6_10, AVB_RXD0),
1000 PINMUX_IPSR_DATA(IP6_11, VI0_DATA2_VI0_B2),
1001 PINMUX_IPSR_DATA(IP6_11, AVB_RXD1),
1002 PINMUX_IPSR_DATA(IP6_12, VI0_DATA3_VI0_B3),
1003 PINMUX_IPSR_DATA(IP6_12, AVB_RXD2),
1004 PINMUX_IPSR_DATA(IP6_13, VI0_DATA4_VI0_B4),
1005 PINMUX_IPSR_DATA(IP6_13, AVB_RXD3),
1006 PINMUX_IPSR_DATA(IP6_14, VI0_DATA5_VI0_B5),
1007 PINMUX_IPSR_DATA(IP6_14, AVB_RXD4),
1008 PINMUX_IPSR_DATA(IP6_15, VI0_DATA6_VI0_B6),
1009 PINMUX_IPSR_DATA(IP6_15, AVB_RXD5),
1010 PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7),
1011 PINMUX_IPSR_DATA(IP6_16, AVB_RXD6),
1012 PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB),
1013 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
1014 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
1015 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IETX_C, SEL_IEB_2),
1016 PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7),
1017 PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD),
1018 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
1019 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
1020 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, IECLK_C, SEL_IEB_2),
1021 PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER),
1022 PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N),
1023 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
1024 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
1025 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, IERX_C, SEL_IEB_2),
1026 PINMUX_IPSR_DATA(IP6_25_23, AVB_COL),
1027 PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N),
1028 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
1029 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
1030 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
1031 PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN),
1032 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ETH_MDIO, SEL_ETH_0),
1033 PINMUX_IPSR_DATA(IP6_31_29, VI0_G0),
1034 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
1035 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3),
1036 PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK),
1037 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ADIDATA, SEL_RAD_0),
1038 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, AD_DI, SEL_ADI_0),
1039
1040 /* IPSR7 */
1041 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
1042 PINMUX_IPSR_DATA(IP7_2_0, VI0_G1),
1043 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
1044 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3),
1045 PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0),
1046 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
1047 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, AD_DO, SEL_ADI_0),
1048 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
1049 PINMUX_IPSR_DATA(IP7_5_3, VI0_G2),
1050 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
1051 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
1052 PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1),
1053 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ADICLK, SEL_RAD_0),
1054 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, AD_CLK, SEL_ADI_0),
1055 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ETH_RXD0, SEL_ETH_0),
1056 PINMUX_IPSR_DATA(IP7_8_6, VI0_G3),
1057 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
1058 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
1059 PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2),
1060 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ADICHS0, SEL_RAD_0),
1061 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, AD_NCS_N, SEL_ADI_0),
1062 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ETH_RXD1, SEL_ETH_0),
1063 PINMUX_IPSR_DATA(IP7_11_9, VI0_G4),
1064 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
1065 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
1066 PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3),
1067 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ADICHS1, SEL_RAD_0),
1068 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ETH_LINK, SEL_ETH_0),
1069 PINMUX_IPSR_DATA(IP7_14_12, VI0_G5),
1070 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
1071 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
1072 PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4),
1073 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ADICHS2, SEL_RAD_0),
1074 PINMUX_IPSR_MODSEL_DATA(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
1075 PINMUX_IPSR_DATA(IP7_17_15, VI0_G6),
1076 PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
1077 PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5),
1078 PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
1079 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, ETH_TXD1, SEL_ETH_0),
1080 PINMUX_IPSR_DATA(IP7_20_18, VI0_G7),
1081 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
1082 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3),
1083 PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6),
1084 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
1085 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
1086 PINMUX_IPSR_DATA(IP7_23_21, VI0_R0),
1087 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
1088 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3),
1089 PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7),
1090 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
1091 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
1092 PINMUX_IPSR_DATA(IP7_26_24, VI0_R1),
1093 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
1094 PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER),
1095 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
1096 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, ETH_TXD0, SEL_ETH_0),
1097 PINMUX_IPSR_DATA(IP7_29_27, VI0_R2),
1098 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
1099 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
1100 PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK),
1101 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
1102 PINMUX_IPSR_DATA(IP7_31, DREQ0_N),
1103 PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD),
1104
1105 /* IPSR8 */
1106 PINMUX_IPSR_MODSEL_DATA(IP8_2_0, ETH_MDC, SEL_ETH_0),
1107 PINMUX_IPSR_DATA(IP8_2_0, VI0_R3),
1108 PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
1109 PINMUX_IPSR_MODSEL_DATA(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
1110 PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC),
1111 PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
1112 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
1113 PINMUX_IPSR_DATA(IP8_5_3, VI0_R4),
1114 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
1115 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
1116 PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO),
1117 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
1118 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
1119 PINMUX_IPSR_DATA(IP8_8_6, VI0_R5),
1120 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
1121 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1122 PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK),
1123 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
1124 PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N),
1125 PINMUX_IPSR_DATA(IP8_11_9, VI0_R6),
1126 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
1127 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
1128 PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC),
1129 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
1130 PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N),
1131 PINMUX_IPSR_DATA(IP8_14_12, VI0_R7),
1132 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
1133 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
1134 PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT),
1135 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
1136 PINMUX_IPSR_MODSEL_DATA(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
1137 PINMUX_IPSR_MODSEL_DATA(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
1138 PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS),
1139 PINMUX_IPSR_MODSEL_DATA(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
1140 PINMUX_IPSR_MODSEL_DATA(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
1141 PINMUX_IPSR_MODSEL_DATA(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
1142 PINMUX_IPSR_DATA(IP8_19_17, PWM5),
1143 PINMUX_IPSR_MODSEL_DATA(IP8_19_17, TCLK1_B, SEL_TMU_1),
1144 PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK),
1145 PINMUX_IPSR_MODSEL_DATA(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
1146 PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B),
1147 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
1148 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
1149 PINMUX_IPSR_DATA(IP8_22_20, TPUTO0),
1150 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN_CLK, SEL_CAN_0),
1151 PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE),
1152 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
1153 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
1154 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
1155 PINMUX_IPSR_DATA(IP8_25_23, PWM5_B),
1156 PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0),
1157 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1),
1158 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
1159 PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B),
1160 PINMUX_IPSR_MODSEL_DATA(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
1161 PINMUX_IPSR_MODSEL_DATA(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
1162 PINMUX_IPSR_DATA(IP8_28_26, IRQ5),
1163 PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1),
1164 PINMUX_IPSR_MODSEL_DATA(IP8_28_26, RIF1_CLK_B, SEL_DR2_1),
1165 PINMUX_IPSR_MODSEL_DATA(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
1166 PINMUX_IPSR_MODSEL_DATA(IP8_28_26, BPFCLK_C, SEL_DARC_2),
1167 PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD),
1168 PINMUX_IPSR_MODSEL_DATA(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
1169 PINMUX_IPSR_MODSEL_DATA(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
1170 PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2),
1171 PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RIF1_D0_B, SEL_DR2_1),
1172 PINMUX_IPSR_MODSEL_DATA(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
1173 PINMUX_IPSR_MODSEL_DATA(IP8_31_29, FMCLK_C, SEL_DARC_2),
1174 PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RDS_CLK, SEL_RDS_0),
1175
1176 /* IPSR9 */
1177 PINMUX_IPSR_DATA(IP9_2_0, MSIOF0_TXD),
1178 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
1179 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
1180 PINMUX_IPSR_DATA(IP9_2_0, DU1_DR3),
1181 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RIF1_D1_B, SEL_DR3_1),
1182 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
1183 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, FMIN_C, SEL_DARC_2),
1184 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RDS_DATA, SEL_RDS_0),
1185 PINMUX_IPSR_DATA(IP9_5_3, MSIOF0_SCK),
1186 PINMUX_IPSR_DATA(IP9_5_3, IRQ0),
1187 PINMUX_IPSR_MODSEL_DATA(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
1188 PINMUX_IPSR_DATA(IP9_5_3, DU1_DR4),
1189 PINMUX_IPSR_MODSEL_DATA(IP9_5_3, RIF1_SYNC, SEL_DR2_0),
1190 PINMUX_IPSR_DATA(IP9_5_3, TPUTO1_C),
1191 PINMUX_IPSR_DATA(IP9_8_6, MSIOF0_SYNC),
1192 PINMUX_IPSR_DATA(IP9_8_6, PWM1),
1193 PINMUX_IPSR_MODSEL_DATA(IP9_8_6, TS_SCK, SEL_TSIF0_0),
1194 PINMUX_IPSR_DATA(IP9_8_6, DU1_DR5),
1195 PINMUX_IPSR_MODSEL_DATA(IP9_8_6, RIF1_CLK, SEL_DR2_0),
1196 PINMUX_IPSR_MODSEL_DATA(IP9_8_6, BPFCLK_B, SEL_DARC_1),
1197 PINMUX_IPSR_DATA(IP9_11_9, MSIOF0_SS1),
1198 PINMUX_IPSR_MODSEL_DATA(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
1199 PINMUX_IPSR_MODSEL_DATA(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
1200 PINMUX_IPSR_DATA(IP9_11_9, DU1_DR6),
1201 PINMUX_IPSR_MODSEL_DATA(IP9_11_9, RIF1_D0, SEL_DR2_0),
1202 PINMUX_IPSR_MODSEL_DATA(IP9_11_9, FMCLK_B, SEL_DARC_1),
1203 PINMUX_IPSR_MODSEL_DATA(IP9_11_9, RDS_CLK_B, SEL_RDS_1),
1204 PINMUX_IPSR_DATA(IP9_14_12, MSIOF0_SS2),
1205 PINMUX_IPSR_MODSEL_DATA(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
1206 PINMUX_IPSR_MODSEL_DATA(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
1207 PINMUX_IPSR_DATA(IP9_14_12, DU1_DR7),
1208 PINMUX_IPSR_MODSEL_DATA(IP9_14_12, RIF1_D1, SEL_DR3_0),
1209 PINMUX_IPSR_MODSEL_DATA(IP9_14_12, FMIN_B, SEL_DARC_1),
1210 PINMUX_IPSR_MODSEL_DATA(IP9_14_12, RDS_DATA_B, SEL_RDS_1),
1211 PINMUX_IPSR_MODSEL_DATA(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
1212 PINMUX_IPSR_MODSEL_DATA(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
1213 PINMUX_IPSR_DATA(IP9_16_15, PWM6),
1214 PINMUX_IPSR_DATA(IP9_16_15, DU1_DG0),
1215 PINMUX_IPSR_MODSEL_DATA(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0),
1216 PINMUX_IPSR_MODSEL_DATA(IP9_18_17, I2C4_SDA, SEL_I2C04_0),
1217 PINMUX_IPSR_DATA(IP9_18_17, TPUTO1),
1218 PINMUX_IPSR_DATA(IP9_18_17, DU1_DG1),
1219 PINMUX_IPSR_DATA(IP9_21_19, HSCIF1_HSCK),
1220 PINMUX_IPSR_DATA(IP9_21_19, PWM2),
1221 PINMUX_IPSR_MODSEL_DATA(IP9_21_19, IETX, SEL_IEB_0),
1222 PINMUX_IPSR_DATA(IP9_21_19, DU1_DG2),
1223 PINMUX_IPSR_MODSEL_DATA(IP9_21_19, REMOCON_B, SEL_RCN_1),
1224 PINMUX_IPSR_MODSEL_DATA(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
1225 PINMUX_IPSR_MODSEL_DATA(IP9_21_19, VSP_B, SEL_SPDM_1),
1226 PINMUX_IPSR_MODSEL_DATA(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
1227 PINMUX_IPSR_MODSEL_DATA(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
1228 PINMUX_IPSR_MODSEL_DATA(IP9_24_22, IECLK, SEL_IEB_0),
1229 PINMUX_IPSR_DATA(IP9_24_22, DU1_DG3),
1230 PINMUX_IPSR_MODSEL_DATA(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
1231 PINMUX_IPSR_DATA(IP9_24_22, CAN_DEBUG_HW_TRIGGER),
1232 PINMUX_IPSR_DATA(IP9_24_22, CC50_STATE32),
1233 PINMUX_IPSR_MODSEL_DATA(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
1234 PINMUX_IPSR_MODSEL_DATA(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
1235 PINMUX_IPSR_MODSEL_DATA(IP9_27_25, IERX, SEL_IEB_0),
1236 PINMUX_IPSR_DATA(IP9_27_25, DU1_DG4),
1237 PINMUX_IPSR_MODSEL_DATA(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
1238 PINMUX_IPSR_DATA(IP9_27_25, CAN_STEP0),
1239 PINMUX_IPSR_DATA(IP9_27_25, CC50_STATE33),
1240 PINMUX_IPSR_MODSEL_DATA(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
1241 PINMUX_IPSR_DATA(IP9_30_28, PWM3),
1242 PINMUX_IPSR_MODSEL_DATA(IP9_30_28, TCLK2, SEL_TMU_0),
1243 PINMUX_IPSR_DATA(IP9_30_28, DU1_DG5),
1244 PINMUX_IPSR_MODSEL_DATA(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
1245 PINMUX_IPSR_DATA(IP9_30_28, CAN_TXCLK),
1246 PINMUX_IPSR_DATA(IP9_30_28, CC50_STATE34),
1247
1248 /* IPSR10 */
1249 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
1250 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, IIC0_SCL, SEL_IIC00_0),
1251 PINMUX_IPSR_DATA(IP10_2_0, DU1_DG6),
1252 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
1253 PINMUX_IPSR_DATA(IP10_2_0, CAN_DEBUGOUT0),
1254 PINMUX_IPSR_DATA(IP10_2_0, CC50_STATE35),
1255 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
1256 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, IIC0_SDA, SEL_IIC00_0),
1257 PINMUX_IPSR_DATA(IP10_5_3, DU1_DG7),
1258 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
1259 PINMUX_IPSR_DATA(IP10_5_3, CAN_DEBUGOUT1),
1260 PINMUX_IPSR_DATA(IP10_5_3, CC50_STATE36),
1261 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
1262 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IIC1_SCL, SEL_IIC01_0),
1263 PINMUX_IPSR_DATA(IP10_8_6, DU1_DB0),
1264 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
1265 PINMUX_IPSR_DATA(IP10_8_6, USB0_EXTLP),
1266 PINMUX_IPSR_DATA(IP10_8_6, CAN_DEBUGOUT2),
1267 PINMUX_IPSR_DATA(IP10_8_6, CC50_STATE37),
1268 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
1269 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IIC1_SDA, SEL_IIC01_0),
1270 PINMUX_IPSR_DATA(IP10_11_9, DU1_DB1),
1271 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
1272 PINMUX_IPSR_DATA(IP10_11_9, USB0_OVC1),
1273 PINMUX_IPSR_DATA(IP10_11_9, CAN_DEBUGOUT3),
1274 PINMUX_IPSR_DATA(IP10_11_9, CC50_STATE38),
1275 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
1276 PINMUX_IPSR_DATA(IP10_14_12, IRQ1),
1277 PINMUX_IPSR_DATA(IP10_14_12, DU1_DB2),
1278 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
1279 PINMUX_IPSR_DATA(IP10_14_12, USB0_IDIN),
1280 PINMUX_IPSR_DATA(IP10_14_12, CAN_DEBUGOUT4),
1281 PINMUX_IPSR_DATA(IP10_14_12, CC50_STATE39),
1282 PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
1283 PINMUX_IPSR_DATA(IP10_17_15, IRQ2),
1284 PINMUX_IPSR_MODSEL_DATA(IP10_17_15, BPFCLK_D, SEL_DARC_3),
1285 PINMUX_IPSR_DATA(IP10_17_15, DU1_DB3),
1286 PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
1287 PINMUX_IPSR_DATA(IP10_17_15, TANS2),
1288 PINMUX_IPSR_DATA(IP10_17_15, CAN_DEBUGOUT5),
1289 PINMUX_IPSR_DATA(IP10_17_15, CC50_OSCOUT),
1290 PINMUX_IPSR_MODSEL_DATA(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
1291 PINMUX_IPSR_MODSEL_DATA(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
1292 PINMUX_IPSR_MODSEL_DATA(IP10_20_18, FMCLK_D, SEL_DARC_3),
1293 PINMUX_IPSR_DATA(IP10_20_18, DU1_DB4),
1294 PINMUX_IPSR_MODSEL_DATA(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
1295 PINMUX_IPSR_MODSEL_DATA(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
1296 PINMUX_IPSR_DATA(IP10_20_18, CAN_DEBUGOUT6),
1297 PINMUX_IPSR_MODSEL_DATA(IP10_20_18, RDS_CLK_C, SEL_RDS_2),
1298 PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
1299 PINMUX_IPSR_MODSEL_DATA(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
1300 PINMUX_IPSR_MODSEL_DATA(IP10_23_21, FMIN_D, SEL_DARC_3),
1301 PINMUX_IPSR_DATA(IP10_23_21, DU1_DB5),
1302 PINMUX_IPSR_MODSEL_DATA(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
1303 PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
1304 PINMUX_IPSR_DATA(IP10_23_21, CAN_DEBUGOUT7),
1305 PINMUX_IPSR_MODSEL_DATA(IP10_23_21, RDS_DATA_C, SEL_RDS_2),
1306 PINMUX_IPSR_MODSEL_DATA(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
1307 PINMUX_IPSR_MODSEL_DATA(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
1308 PINMUX_IPSR_DATA(IP10_26_24, DU1_DB6),
1309 PINMUX_IPSR_MODSEL_DATA(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
1310 PINMUX_IPSR_MODSEL_DATA(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
1311 PINMUX_IPSR_DATA(IP10_26_24, CAN_DEBUGOUT8),
1312 PINMUX_IPSR_MODSEL_DATA(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
1313 PINMUX_IPSR_MODSEL_DATA(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
1314 PINMUX_IPSR_DATA(IP10_29_27, DU1_DB7),
1315 PINMUX_IPSR_MODSEL_DATA(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
1316 PINMUX_IPSR_DATA(IP10_29_27, CAN_DEBUGOUT9),
1317 PINMUX_IPSR_MODSEL_DATA(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
1318 PINMUX_IPSR_MODSEL_DATA(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
1319 PINMUX_IPSR_DATA(IP10_31_30, DU1_DOTCLKIN),
1320 PINMUX_IPSR_DATA(IP10_31_30, CAN_DEBUGOUT10),
1321
1322 /* IPSR11 */
1323 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SSI_WS5, SEL_SSI5_0),
1324 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1325 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
1326 PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0),
1327 PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11),
1328 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
1329 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
1330 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
1331 PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1),
1332 PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12),
1333 PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
1334 PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
1335 PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
1336 PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13),
1337 PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SSI_WS6, SEL_SSI6_0),
1338 PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
1339 PINMUX_IPSR_MODSEL_DATA(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
1340 PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
1341 PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14),
1342 PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
1343 PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
1344 PINMUX_IPSR_MODSEL_DATA(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
1345 PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1346 PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15),
1347 PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
1348 PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
1349 PINMUX_IPSR_MODSEL_DATA(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2),
1350 PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP),
1351 PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SSI_WS78, SEL_SSI7_0),
1352 PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
1353 PINMUX_IPSR_MODSEL_DATA(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2),
1354 PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE),
1355 PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
1356 PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
1357 PINMUX_IPSR_DATA(IP11_20_18, IRQ8),
1358 PINMUX_IPSR_MODSEL_DATA(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
1359 PINMUX_IPSR_MODSEL_DATA(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
1360 PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N),
1361 PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129),
1362 PINMUX_IPSR_MODSEL_DATA(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
1363 PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
1364 PINMUX_IPSR_MODSEL_DATA(IP11_23_21, ADIDATA_B, SEL_RAD_1),
1365 PINMUX_IPSR_MODSEL_DATA(IP11_23_21, AD_DI_B, SEL_ADI_1),
1366 PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N),
1367 PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129),
1368 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
1369 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
1370 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
1371 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, AD_DO_B, SEL_ADI_1),
1372 PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0),
1373 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
1374 PINMUX_IPSR_DATA(IP11_29_27, PWM0_B),
1375 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, ADICLK_B, SEL_RAD_1),
1376 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, AD_CLK_B, SEL_ADI_1),
1377
1378 /* IPSR12 */
1379 PINMUX_IPSR_DATA(IP12_2_0, SSI_SCK34),
1380 PINMUX_IPSR_MODSEL_DATA(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
1381 PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
1382 PINMUX_IPSR_MODSEL_DATA(IP12_2_0, ADICHS0_B, SEL_RAD_1),
1383 PINMUX_IPSR_MODSEL_DATA(IP12_2_0, AD_NCS_N_B, SEL_ADI_1),
1384 PINMUX_IPSR_MODSEL_DATA(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
1385 PINMUX_IPSR_DATA(IP12_5_3, SSI_WS34),
1386 PINMUX_IPSR_MODSEL_DATA(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
1387 PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
1388 PINMUX_IPSR_MODSEL_DATA(IP12_5_3, ADICHS1_B, SEL_RAD_1),
1389 PINMUX_IPSR_MODSEL_DATA(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
1390 PINMUX_IPSR_MODSEL_DATA(IP12_5_3, DACK1_B, SEL_LBS_1),
1391 PINMUX_IPSR_DATA(IP12_8_6, SSI_SDATA3),
1392 PINMUX_IPSR_MODSEL_DATA(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
1393 PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
1394 PINMUX_IPSR_MODSEL_DATA(IP12_8_6, ADICHS2_B, SEL_RAD_1),
1395 PINMUX_IPSR_MODSEL_DATA(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
1396 PINMUX_IPSR_DATA(IP12_8_6, DREQ2_N),
1397 PINMUX_IPSR_MODSEL_DATA(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
1398 PINMUX_IPSR_DATA(IP12_10_9, MLB_CLK),
1399 PINMUX_IPSR_MODSEL_DATA(IP12_10_9, IETX_B, SEL_IEB_1),
1400 PINMUX_IPSR_DATA(IP12_10_9, IRD_TX),
1401 PINMUX_IPSR_MODSEL_DATA(IP12_12_11, SSI_WS4, SEL_SSI4_0),
1402 PINMUX_IPSR_DATA(IP12_12_11, MLB_SIG),
1403 PINMUX_IPSR_MODSEL_DATA(IP12_12_11, IECLK_B, SEL_IEB_1),
1404 PINMUX_IPSR_DATA(IP12_12_11, IRD_RX),
1405 PINMUX_IPSR_MODSEL_DATA(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
1406 PINMUX_IPSR_DATA(IP12_14_13, MLB_DAT),
1407 PINMUX_IPSR_MODSEL_DATA(IP12_14_13, IERX_B, SEL_IEB_1),
1408 PINMUX_IPSR_DATA(IP12_14_13, IRD_SCK),
1409 PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
1410 PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
1411 PINMUX_IPSR_DATA(IP12_17_15, PWM1_B),
1412 PINMUX_IPSR_DATA(IP12_17_15, IRQ9),
1413 PINMUX_IPSR_MODSEL_DATA(IP12_17_15, REMOCON, SEL_RCN_0),
1414 PINMUX_IPSR_DATA(IP12_17_15, DACK2),
1415 PINMUX_IPSR_MODSEL_DATA(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
1416 PINMUX_IPSR_MODSEL_DATA(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
1417 PINMUX_IPSR_MODSEL_DATA(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1),
1418 PINMUX_IPSR_MODSEL_DATA(IP12_20_18, IIC1_SCL_C, SEL_IIC01_2),
1419 PINMUX_IPSR_DATA(IP12_20_18, VI1_CLK),
1420 PINMUX_IPSR_MODSEL_DATA(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
1421 PINMUX_IPSR_MODSEL_DATA(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0),
1422 PINMUX_IPSR_MODSEL_DATA(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
1423 PINMUX_IPSR_MODSEL_DATA(IP12_23_21, SSI_WS1, SEL_SSI1_0),
1424 PINMUX_IPSR_MODSEL_DATA(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
1425 PINMUX_IPSR_MODSEL_DATA(IP12_23_21, IIC1_SDA_C, SEL_IIC01_2),
1426 PINMUX_IPSR_DATA(IP12_23_21, VI1_DATA0),
1427 PINMUX_IPSR_MODSEL_DATA(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
1428 PINMUX_IPSR_MODSEL_DATA(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0),
1429 PINMUX_IPSR_MODSEL_DATA(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
1430 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
1431 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
1432 PINMUX_IPSR_DATA(IP12_26_24, VI1_DATA1),
1433 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SDATA, SEL_FSN_0),
1434 PINMUX_IPSR_DATA(IP12_26_24, ATAG0_N),
1435 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
1436 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
1437 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
1438 PINMUX_IPSR_DATA(IP12_29_27, VI1_DATA2),
1439 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MDATA, SEL_FSN_0),
1440 PINMUX_IPSR_DATA(IP12_29_27, ATAWR0_N),
1441 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
1442
1443 /* IPSR13 */
1444 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_WS2, SEL_SSI2_0),
1445 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
1446 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
1447 PINMUX_IPSR_DATA(IP13_2_0, VI1_DATA3),
1448 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCKZ, SEL_FSN_0),
1449 PINMUX_IPSR_DATA(IP13_2_0, ATACS00_N),
1450 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
1451 PINMUX_IPSR_MODSEL_DATA(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
1452 PINMUX_IPSR_MODSEL_DATA(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
1453 PINMUX_IPSR_MODSEL_DATA(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
1454 PINMUX_IPSR_DATA(IP13_5_3, VI1_DATA4),
1455 PINMUX_IPSR_MODSEL_DATA(IP13_5_3, STM_N, SEL_FSN_0),
1456 PINMUX_IPSR_DATA(IP13_5_3, ATACS10_N),
1457 PINMUX_IPSR_MODSEL_DATA(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
1458 PINMUX_IPSR_MODSEL_DATA(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
1459 PINMUX_IPSR_MODSEL_DATA(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
1460 PINMUX_IPSR_DATA(IP13_8_6, PWM2_B),
1461 PINMUX_IPSR_DATA(IP13_8_6, VI1_DATA5),
1462 PINMUX_IPSR_MODSEL_DATA(IP13_8_6, MTS_N, SEL_FSN_0),
1463 PINMUX_IPSR_DATA(IP13_8_6, EX_WAIT1),
1464 PINMUX_IPSR_MODSEL_DATA(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
1465 PINMUX_IPSR_MODSEL_DATA(IP13_11_9, SSI_WS9, SEL_SSI9_0),
1466 PINMUX_IPSR_MODSEL_DATA(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1),
1467 PINMUX_IPSR_MODSEL_DATA(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4),
1468 PINMUX_IPSR_DATA(IP13_11_9, VI1_DATA6),
1469 PINMUX_IPSR_DATA(IP13_11_9, ATARD0_N),
1470 PINMUX_IPSR_MODSEL_DATA(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1),
1471 PINMUX_IPSR_MODSEL_DATA(IP13_14_12, SSI_SDATA9, SEL_SSI9_0),
1472 PINMUX_IPSR_MODSEL_DATA(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1),
1473 PINMUX_IPSR_MODSEL_DATA(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4),
1474 PINMUX_IPSR_DATA(IP13_14_12, VI1_DATA7),
1475 PINMUX_IPSR_DATA(IP13_14_12, ATADIR0_N),
1476 PINMUX_IPSR_MODSEL_DATA(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1),
1477 PINMUX_IPSR_MODSEL_DATA(IP13_17_15, AUDIO_CLKA, SEL_ADG_0),
1478 PINMUX_IPSR_MODSEL_DATA(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
1479 PINMUX_IPSR_MODSEL_DATA(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
1480 PINMUX_IPSR_DATA(IP13_17_15, VI1_CLKENB),
1481 PINMUX_IPSR_MODSEL_DATA(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
1482 PINMUX_IPSR_MODSEL_DATA(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1),
1483 PINMUX_IPSR_MODSEL_DATA(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
1484 PINMUX_IPSR_MODSEL_DATA(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
1485 PINMUX_IPSR_MODSEL_DATA(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
1486 PINMUX_IPSR_MODSEL_DATA(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
1487 PINMUX_IPSR_DATA(IP13_20_18, VI1_FIELD),
1488 PINMUX_IPSR_MODSEL_DATA(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
1489 PINMUX_IPSR_MODSEL_DATA(IP13_20_18, RIF0_CLK_B, SEL_DR0_1),
1490 PINMUX_IPSR_MODSEL_DATA(IP13_20_18, BPFCLK_E, SEL_DARC_4),
1491 PINMUX_IPSR_MODSEL_DATA(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
1492 PINMUX_IPSR_MODSEL_DATA(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
1493 PINMUX_IPSR_MODSEL_DATA(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
1494 PINMUX_IPSR_MODSEL_DATA(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
1495 PINMUX_IPSR_DATA(IP13_23_21, VI1_HSYNC_N),
1496 PINMUX_IPSR_MODSEL_DATA(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
1497 PINMUX_IPSR_MODSEL_DATA(IP13_23_21, RIF0_D0_B, SEL_DR0_1),
1498 PINMUX_IPSR_MODSEL_DATA(IP13_23_21, FMCLK_E, SEL_DARC_4),
1499 PINMUX_IPSR_MODSEL_DATA(IP13_23_21, RDS_CLK_D, SEL_RDS_3),
1500 PINMUX_IPSR_MODSEL_DATA(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
1501 PINMUX_IPSR_MODSEL_DATA(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
1502 PINMUX_IPSR_MODSEL_DATA(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
1503 PINMUX_IPSR_DATA(IP13_26_24, VI1_VSYNC_N),
1504 PINMUX_IPSR_MODSEL_DATA(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
1505 PINMUX_IPSR_MODSEL_DATA(IP13_26_24, RIF0_D1_B, SEL_DR1_1),
1506 PINMUX_IPSR_MODSEL_DATA(IP13_26_24, FMIN_E, SEL_DARC_4),
1507 PINMUX_IPSR_MODSEL_DATA(IP13_26_24, RDS_DATA_D, SEL_RDS_3),
1508};
1509
1510static const struct sh_pfc_pin pinmux_pins[] = {
1511 PINMUX_GPIO_GP_ALL(),
1512};
1513
1514/* - ETH -------------------------------------------------------------------- */
1515static const unsigned int eth_link_pins[] = {
1516 /* LINK */
1517 RCAR_GP_PIN(3, 18),
1518};
1519static const unsigned int eth_link_mux[] = {
1520 ETH_LINK_MARK,
1521};
1522static const unsigned int eth_magic_pins[] = {
1523 /* MAGIC */
1524 RCAR_GP_PIN(3, 22),
1525};
1526static const unsigned int eth_magic_mux[] = {
1527 ETH_MAGIC_MARK,
1528};
1529static const unsigned int eth_mdio_pins[] = {
1530 /* MDC, MDIO */
1531 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13),
1532};
1533static const unsigned int eth_mdio_mux[] = {
1534 ETH_MDC_MARK, ETH_MDIO_MARK,
1535};
1536static const unsigned int eth_rmii_pins[] = {
1537 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1538 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15),
1539 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20),
1540 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19),
1541};
1542static const unsigned int eth_rmii_mux[] = {
1543 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1544 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1545};
1546static const unsigned int eth_link_b_pins[] = {
1547 /* LINK */
1548 RCAR_GP_PIN(5, 15),
1549};
1550static const unsigned int eth_link_b_mux[] = {
1551 ETH_LINK_B_MARK,
1552};
1553static const unsigned int eth_magic_b_pins[] = {
1554 /* MAGIC */
1555 RCAR_GP_PIN(5, 19),
1556};
1557static const unsigned int eth_magic_b_mux[] = {
1558 ETH_MAGIC_B_MARK,
1559};
1560static const unsigned int eth_mdio_b_pins[] = {
1561 /* MDC, MDIO */
1562 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10),
1563};
1564static const unsigned int eth_mdio_b_mux[] = {
1565 ETH_MDC_B_MARK, ETH_MDIO_B_MARK,
1566};
1567static const unsigned int eth_rmii_b_pins[] = {
1568 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1569 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12),
1570 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17),
1571 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16),
1572};
1573static const unsigned int eth_rmii_b_mux[] = {
1574 ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK,
1575 ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK,
1576};
1577/* - HSCIF0 ----------------------------------------------------------------- */
1578static const unsigned int hscif0_data_pins[] = {
1579 /* RX, TX */
1580 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1581};
1582static const unsigned int hscif0_data_mux[] = {
1583 HSCIF0_HRX_MARK, HSCIF0_HTX_MARK,
1584};
1585static const unsigned int hscif0_clk_pins[] = {
1586 /* SCK */
1587 RCAR_GP_PIN(3, 29),
1588};
1589static const unsigned int hscif0_clk_mux[] = {
1590 HSCIF0_HSCK_MARK,
1591};
1592static const unsigned int hscif0_ctrl_pins[] = {
1593 /* RTS, CTS */
1594 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1595};
1596static const unsigned int hscif0_ctrl_mux[] = {
1597 HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK,
1598};
1599static const unsigned int hscif0_data_b_pins[] = {
1600 /* RX, TX */
1601 RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31),
1602};
1603static const unsigned int hscif0_data_b_mux[] = {
1604 HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK,
1605};
1606static const unsigned int hscif0_clk_b_pins[] = {
1607 /* SCK */
1608 RCAR_GP_PIN(1, 0),
1609};
1610static const unsigned int hscif0_clk_b_mux[] = {
1611 HSCIF0_HSCK_B_MARK,
1612};
1613/* - HSCIF1 ----------------------------------------------------------------- */
1614static const unsigned int hscif1_data_pins[] = {
1615 /* RX, TX */
1616 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1617};
1618static const unsigned int hscif1_data_mux[] = {
1619 HSCIF1_HRX_MARK, HSCIF1_HTX_MARK,
1620};
1621static const unsigned int hscif1_clk_pins[] = {
1622 /* SCK */
1623 RCAR_GP_PIN(4, 10),
1624};
1625static const unsigned int hscif1_clk_mux[] = {
1626 HSCIF1_HSCK_MARK,
1627};
1628static const unsigned int hscif1_ctrl_pins[] = {
1629 /* RTS, CTS */
1630 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
1631};
1632static const unsigned int hscif1_ctrl_mux[] = {
1633 HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK,
1634};
1635static const unsigned int hscif1_data_b_pins[] = {
1636 /* RX, TX */
1637 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1638};
1639static const unsigned int hscif1_data_b_mux[] = {
1640 HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK,
1641};
1642static const unsigned int hscif1_ctrl_b_pins[] = {
1643 /* RTS, CTS */
1644 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
1645};
1646static const unsigned int hscif1_ctrl_b_mux[] = {
1647 HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK,
1648};
1649/* - HSCIF2 ----------------------------------------------------------------- */
1650static const unsigned int hscif2_data_pins[] = {
1651 /* RX, TX */
1652 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
1653};
1654static const unsigned int hscif2_data_mux[] = {
1655 HSCIF2_HRX_MARK, HSCIF2_HTX_MARK,
1656};
1657static const unsigned int hscif2_clk_pins[] = {
1658 /* SCK */
1659 RCAR_GP_PIN(0, 10),
1660};
1661static const unsigned int hscif2_clk_mux[] = {
1662 HSCIF2_HSCK_MARK,
1663};
1664static const unsigned int hscif2_ctrl_pins[] = {
1665 /* RTS, CTS */
1666 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
1667};
1668static const unsigned int hscif2_ctrl_mux[] = {
1669 HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK,
1670};
1671/* - I2C0 ------------------------------------------------------------------- */
1672static const unsigned int i2c0_pins[] = {
1673 /* SCL, SDA */
1674 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
1675};
1676static const unsigned int i2c0_mux[] = {
1677 I2C0_SCL_MARK, I2C0_SDA_MARK,
1678};
1679static const unsigned int i2c0_b_pins[] = {
1680 /* SCL, SDA */
1681 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
1682};
1683static const unsigned int i2c0_b_mux[] = {
1684 I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
1685};
1686static const unsigned int i2c0_c_pins[] = {
1687 /* SCL, SDA */
1688 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1689};
1690static const unsigned int i2c0_c_mux[] = {
1691 I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
1692};
1693static const unsigned int i2c0_d_pins[] = {
1694 /* SCL, SDA */
1695 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
1696};
1697static const unsigned int i2c0_d_mux[] = {
1698 I2C0_SCL_D_MARK, I2C0_SDA_D_MARK,
1699};
1700static const unsigned int i2c0_e_pins[] = {
1701 /* SCL, SDA */
1702 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
1703};
1704static const unsigned int i2c0_e_mux[] = {
1705 I2C0_SCL_E_MARK, I2C0_SDA_E_MARK,
1706};
1707/* - I2C1 ------------------------------------------------------------------- */
1708static const unsigned int i2c1_pins[] = {
1709 /* SCL, SDA */
1710 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1711};
1712static const unsigned int i2c1_mux[] = {
1713 I2C1_SCL_MARK, I2C1_SDA_MARK,
1714};
1715static const unsigned int i2c1_b_pins[] = {
1716 /* SCL, SDA */
1717 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
1718};
1719static const unsigned int i2c1_b_mux[] = {
1720 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
1721};
1722static const unsigned int i2c1_c_pins[] = {
1723 /* SCL, SDA */
1724 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1725};
1726static const unsigned int i2c1_c_mux[] = {
1727 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
1728};
1729static const unsigned int i2c1_d_pins[] = {
1730 /* SCL, SDA */
1731 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
1732};
1733static const unsigned int i2c1_d_mux[] = {
1734 I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
1735};
1736static const unsigned int i2c1_e_pins[] = {
1737 /* SCL, SDA */
1738 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
1739};
1740static const unsigned int i2c1_e_mux[] = {
1741 I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
1742};
1743/* - I2C2 ------------------------------------------------------------------- */
1744static const unsigned int i2c2_pins[] = {
1745 /* SCL, SDA */
1746 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
1747};
1748static const unsigned int i2c2_mux[] = {
1749 I2C2_SCL_MARK, I2C2_SDA_MARK,
1750};
1751static const unsigned int i2c2_b_pins[] = {
1752 /* SCL, SDA */
1753 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1754};
1755static const unsigned int i2c2_b_mux[] = {
1756 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
1757};
1758static const unsigned int i2c2_c_pins[] = {
1759 /* SCL, SDA */
1760 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1761};
1762static const unsigned int i2c2_c_mux[] = {
1763 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
1764};
1765static const unsigned int i2c2_d_pins[] = {
1766 /* SCL, SDA */
1767 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1768};
1769static const unsigned int i2c2_d_mux[] = {
1770 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
1771};
1772static const unsigned int i2c2_e_pins[] = {
1773 /* SCL, SDA */
1774 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
1775};
1776static const unsigned int i2c2_e_mux[] = {
1777 I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
1778};
1779/* - I2C3 ------------------------------------------------------------------- */
1780static const unsigned int i2c3_pins[] = {
1781 /* SCL, SDA */
1782 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1783};
1784static const unsigned int i2c3_mux[] = {
1785 I2C3_SCL_MARK, I2C3_SDA_MARK,
1786};
1787static const unsigned int i2c3_b_pins[] = {
1788 /* SCL, SDA */
1789 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
1790};
1791static const unsigned int i2c3_b_mux[] = {
1792 I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
1793};
1794static const unsigned int i2c3_c_pins[] = {
1795 /* SCL, SDA */
1796 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
1797};
1798static const unsigned int i2c3_c_mux[] = {
1799 I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
1800};
1801static const unsigned int i2c3_d_pins[] = {
1802 /* SCL, SDA */
1803 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1804};
1805static const unsigned int i2c3_d_mux[] = {
1806 I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
1807};
1808static const unsigned int i2c3_e_pins[] = {
1809 /* SCL, SDA */
1810 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
1811};
1812static const unsigned int i2c3_e_mux[] = {
1813 I2C3_SCL_E_MARK, I2C3_SDA_E_MARK,
1814};
1815/* - I2C4 ------------------------------------------------------------------- */
1816static const unsigned int i2c4_pins[] = {
1817 /* SCL, SDA */
1818 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1819};
1820static const unsigned int i2c4_mux[] = {
1821 I2C4_SCL_MARK, I2C4_SDA_MARK,
1822};
1823static const unsigned int i2c4_b_pins[] = {
1824 /* SCL, SDA */
1825 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
1826};
1827static const unsigned int i2c4_b_mux[] = {
1828 I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
1829};
1830static const unsigned int i2c4_c_pins[] = {
1831 /* SCL, SDA */
1832 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
1833};
1834static const unsigned int i2c4_c_mux[] = {
1835 I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
1836};
1837static const unsigned int i2c4_d_pins[] = {
1838 /* SCL, SDA */
1839 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1840};
1841static const unsigned int i2c4_d_mux[] = {
1842 I2C4_SCL_D_MARK, I2C4_SDA_D_MARK,
1843};
1844static const unsigned int i2c4_e_pins[] = {
1845 /* SCL, SDA */
1846 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
1847};
1848static const unsigned int i2c4_e_mux[] = {
1849 I2C4_SCL_E_MARK, I2C4_SDA_E_MARK,
1850};
1851/* - INTC ------------------------------------------------------------------- */
1852static const unsigned int intc_irq0_pins[] = {
1853 /* IRQ0 */
1854 RCAR_GP_PIN(4, 4),
1855};
1856static const unsigned int intc_irq0_mux[] = {
1857 IRQ0_MARK,
1858};
1859static const unsigned int intc_irq1_pins[] = {
1860 /* IRQ1 */
1861 RCAR_GP_PIN(4, 18),
1862};
1863static const unsigned int intc_irq1_mux[] = {
1864 IRQ1_MARK,
1865};
1866static const unsigned int intc_irq2_pins[] = {
1867 /* IRQ2 */
1868 RCAR_GP_PIN(4, 19),
1869};
1870static const unsigned int intc_irq2_mux[] = {
1871 IRQ2_MARK,
1872};
1873static const unsigned int intc_irq3_pins[] = {
1874 /* IRQ3 */
1875 RCAR_GP_PIN(0, 7),
1876};
1877static const unsigned int intc_irq3_mux[] = {
1878 IRQ3_MARK,
1879};
1880static const unsigned int intc_irq4_pins[] = {
1881 /* IRQ4 */
1882 RCAR_GP_PIN(0, 0),
1883};
1884static const unsigned int intc_irq4_mux[] = {
1885 IRQ4_MARK,
1886};
1887static const unsigned int intc_irq5_pins[] = {
1888 /* IRQ5 */
1889 RCAR_GP_PIN(4, 1),
1890};
1891static const unsigned int intc_irq5_mux[] = {
1892 IRQ5_MARK,
1893};
1894static const unsigned int intc_irq6_pins[] = {
1895 /* IRQ6 */
1896 RCAR_GP_PIN(0, 10),
1897};
1898static const unsigned int intc_irq6_mux[] = {
1899 IRQ6_MARK,
1900};
1901static const unsigned int intc_irq7_pins[] = {
1902 /* IRQ7 */
1903 RCAR_GP_PIN(6, 15),
1904};
1905static const unsigned int intc_irq7_mux[] = {
1906 IRQ7_MARK,
1907};
1908static const unsigned int intc_irq8_pins[] = {
1909 /* IRQ8 */
1910 RCAR_GP_PIN(5, 0),
1911};
1912static const unsigned int intc_irq8_mux[] = {
1913 IRQ8_MARK,
1914};
1915static const unsigned int intc_irq9_pins[] = {
1916 /* IRQ9 */
1917 RCAR_GP_PIN(5, 10),
1918};
1919static const unsigned int intc_irq9_mux[] = {
1920 IRQ9_MARK,
1921};
1922/* - MSIOF0 ----------------------------------------------------------------- */
1923static const unsigned int msiof0_clk_pins[] = {
1924 /* SCK */
1925 RCAR_GP_PIN(4, 4),
1926};
1927static const unsigned int msiof0_clk_mux[] = {
1928 MSIOF0_SCK_MARK,
1929};
1930static const unsigned int msiof0_sync_pins[] = {
1931 /* SYNC */
1932 RCAR_GP_PIN(4, 5),
1933};
1934static const unsigned int msiof0_sync_mux[] = {
1935 MSIOF0_SYNC_MARK,
1936};
1937static const unsigned int msiof0_ss1_pins[] = {
1938 /* SS1 */
1939 RCAR_GP_PIN(4, 6),
1940};
1941static const unsigned int msiof0_ss1_mux[] = {
1942 MSIOF0_SS1_MARK,
1943};
1944static const unsigned int msiof0_ss2_pins[] = {
1945 /* SS2 */
1946 RCAR_GP_PIN(4, 7),
1947};
1948static const unsigned int msiof0_ss2_mux[] = {
1949 MSIOF0_SS2_MARK,
1950};
1951static const unsigned int msiof0_rx_pins[] = {
1952 /* RXD */
1953 RCAR_GP_PIN(4, 2),
1954};
1955static const unsigned int msiof0_rx_mux[] = {
1956 MSIOF0_RXD_MARK,
1957};
1958static const unsigned int msiof0_tx_pins[] = {
1959 /* TXD */
1960 RCAR_GP_PIN(4, 3),
1961};
1962static const unsigned int msiof0_tx_mux[] = {
1963 MSIOF0_TXD_MARK,
1964};
1965/* - MSIOF1 ----------------------------------------------------------------- */
1966static const unsigned int msiof1_clk_pins[] = {
1967 /* SCK */
1968 RCAR_GP_PIN(0, 26),
1969};
1970static const unsigned int msiof1_clk_mux[] = {
1971 MSIOF1_SCK_MARK,
1972};
1973static const unsigned int msiof1_sync_pins[] = {
1974 /* SYNC */
1975 RCAR_GP_PIN(0, 27),
1976};
1977static const unsigned int msiof1_sync_mux[] = {
1978 MSIOF1_SYNC_MARK,
1979};
1980static const unsigned int msiof1_ss1_pins[] = {
1981 /* SS1 */
1982 RCAR_GP_PIN(0, 28),
1983};
1984static const unsigned int msiof1_ss1_mux[] = {
1985 MSIOF1_SS1_MARK,
1986};
1987static const unsigned int msiof1_ss2_pins[] = {
1988 /* SS2 */
1989 RCAR_GP_PIN(0, 29),
1990};
1991static const unsigned int msiof1_ss2_mux[] = {
1992 MSIOF1_SS2_MARK,
1993};
1994static const unsigned int msiof1_rx_pins[] = {
1995 /* RXD */
1996 RCAR_GP_PIN(0, 24),
1997};
1998static const unsigned int msiof1_rx_mux[] = {
1999 MSIOF1_RXD_MARK,
2000};
2001static const unsigned int msiof1_tx_pins[] = {
2002 /* TXD */
2003 RCAR_GP_PIN(0, 25),
2004};
2005static const unsigned int msiof1_tx_mux[] = {
2006 MSIOF1_TXD_MARK,
2007};
2008static const unsigned int msiof1_clk_b_pins[] = {
2009 /* SCK */
2010 RCAR_GP_PIN(5, 3),
2011};
2012static const unsigned int msiof1_clk_b_mux[] = {
2013 MSIOF1_SCK_B_MARK,
2014};
2015static const unsigned int msiof1_sync_b_pins[] = {
2016 /* SYNC */
2017 RCAR_GP_PIN(5, 4),
2018};
2019static const unsigned int msiof1_sync_b_mux[] = {
2020 MSIOF1_SYNC_B_MARK,
2021};
2022static const unsigned int msiof1_ss1_b_pins[] = {
2023 /* SS1 */
2024 RCAR_GP_PIN(5, 5),
2025};
2026static const unsigned int msiof1_ss1_b_mux[] = {
2027 MSIOF1_SS1_B_MARK,
2028};
2029static const unsigned int msiof1_ss2_b_pins[] = {
2030 /* SS2 */
2031 RCAR_GP_PIN(5, 6),
2032};
2033static const unsigned int msiof1_ss2_b_mux[] = {
2034 MSIOF1_SS2_B_MARK,
2035};
2036static const unsigned int msiof1_rx_b_pins[] = {
2037 /* RXD */
2038 RCAR_GP_PIN(5, 1),
2039};
2040static const unsigned int msiof1_rx_b_mux[] = {
2041 MSIOF1_RXD_B_MARK,
2042};
2043static const unsigned int msiof1_tx_b_pins[] = {
2044 /* TXD */
2045 RCAR_GP_PIN(5, 2),
2046};
2047static const unsigned int msiof1_tx_b_mux[] = {
2048 MSIOF1_TXD_B_MARK,
2049};
2050/* - MSIOF2 ----------------------------------------------------------------- */
2051static const unsigned int msiof2_clk_pins[] = {
2052 /* SCK */
2053 RCAR_GP_PIN(1, 0),
2054};
2055static const unsigned int msiof2_clk_mux[] = {
2056 MSIOF2_SCK_MARK,
2057};
2058static const unsigned int msiof2_sync_pins[] = {
2059 /* SYNC */
2060 RCAR_GP_PIN(1, 1),
2061};
2062static const unsigned int msiof2_sync_mux[] = {
2063 MSIOF2_SYNC_MARK,
2064};
2065static const unsigned int msiof2_ss1_pins[] = {
2066 /* SS1 */
2067 RCAR_GP_PIN(1, 2),
2068};
2069static const unsigned int msiof2_ss1_mux[] = {
2070 MSIOF2_SS1_MARK,
2071};
2072static const unsigned int msiof2_ss2_pins[] = {
2073 /* SS2 */
2074 RCAR_GP_PIN(1, 3),
2075};
2076static const unsigned int msiof2_ss2_mux[] = {
2077 MSIOF2_SS2_MARK,
2078};
2079static const unsigned int msiof2_rx_pins[] = {
2080 /* RXD */
2081 RCAR_GP_PIN(0, 30),
2082};
2083static const unsigned int msiof2_rx_mux[] = {
2084 MSIOF2_RXD_MARK,
2085};
2086static const unsigned int msiof2_tx_pins[] = {
2087 /* TXD */
2088 RCAR_GP_PIN(0, 31),
2089};
2090static const unsigned int msiof2_tx_mux[] = {
2091 MSIOF2_TXD_MARK,
2092};
2093static const unsigned int msiof2_clk_b_pins[] = {
2094 /* SCK */
2095 RCAR_GP_PIN(3, 15),
2096};
2097static const unsigned int msiof2_clk_b_mux[] = {
2098 MSIOF2_SCK_B_MARK,
2099};
2100static const unsigned int msiof2_sync_b_pins[] = {
2101 /* SYNC */
2102 RCAR_GP_PIN(3, 16),
2103};
2104static const unsigned int msiof2_sync_b_mux[] = {
2105 MSIOF2_SYNC_B_MARK,
2106};
2107static const unsigned int msiof2_ss1_b_pins[] = {
2108 /* SS1 */
2109 RCAR_GP_PIN(3, 17),
2110};
2111static const unsigned int msiof2_ss1_b_mux[] = {
2112 MSIOF2_SS1_B_MARK,
2113};
2114static const unsigned int msiof2_ss2_b_pins[] = {
2115 /* SS2 */
2116 RCAR_GP_PIN(3, 18),
2117};
2118static const unsigned int msiof2_ss2_b_mux[] = {
2119 MSIOF2_SS2_B_MARK,
2120};
2121static const unsigned int msiof2_rx_b_pins[] = {
2122 /* RXD */
2123 RCAR_GP_PIN(3, 13),
2124};
2125static const unsigned int msiof2_rx_b_mux[] = {
2126 MSIOF2_RXD_B_MARK,
2127};
2128static const unsigned int msiof2_tx_b_pins[] = {
2129 /* TXD */
2130 RCAR_GP_PIN(3, 14),
2131};
2132static const unsigned int msiof2_tx_b_mux[] = {
2133 MSIOF2_TXD_B_MARK,
2134};
2135/* - QSPI ------------------------------------------------------------------- */
2136static const unsigned int qspi_ctrl_pins[] = {
2137 /* SPCLK, SSL */
2138 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2139};
2140static const unsigned int qspi_ctrl_mux[] = {
2141 SPCLK_MARK, SSL_MARK,
2142};
2143static const unsigned int qspi_data2_pins[] = {
2144 /* MOSI_IO0, MISO_IO1 */
2145 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2146};
2147static const unsigned int qspi_data2_mux[] = {
2148 MOSI_IO0_MARK, MISO_IO1_MARK,
2149};
2150static const unsigned int qspi_data4_pins[] = {
2151 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2152 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2153 RCAR_GP_PIN(1, 8),
2154};
2155static const unsigned int qspi_data4_mux[] = {
2156 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2157};
2158/* - SCIF0 ------------------------------------------------------------------ */
2159static const unsigned int scif0_data_pins[] = {
2160 /* RX, TX */
2161 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2162};
2163static const unsigned int scif0_data_mux[] = {
2164 SCIF0_RXD_MARK, SCIF0_TXD_MARK,
2165};
2166static const unsigned int scif0_clk_pins[] = {
2167 /* SCK */
2168 RCAR_GP_PIN(1, 23),
2169};
2170static const unsigned int scif0_clk_mux[] = {
2171 SCIF_CLK_MARK,
2172};
2173static const unsigned int scif0_data_b_pins[] = {
2174 /* RX, TX */
2175 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
2176};
2177static const unsigned int scif0_data_b_mux[] = {
2178 SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK,
2179};
2180static const unsigned int scif0_clk_b_pins[] = {
2181 /* SCK */
2182 RCAR_GP_PIN(3, 29),
2183};
2184static const unsigned int scif0_clk_b_mux[] = {
2185 SCIF_CLK_B_MARK,
2186};
2187static const unsigned int scif0_data_c_pins[] = {
2188 /* RX, TX */
2189 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2190};
2191static const unsigned int scif0_data_c_mux[] = {
2192 SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK,
2193};
2194static const unsigned int scif0_data_d_pins[] = {
2195 /* RX, TX */
2196 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
2197};
2198static const unsigned int scif0_data_d_mux[] = {
2199 SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK,
2200};
2201/* - SCIF1 ------------------------------------------------------------------ */
2202static const unsigned int scif1_data_pins[] = {
2203 /* RX, TX */
2204 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
2205};
2206static const unsigned int scif1_data_mux[] = {
2207 SCIF1_RXD_MARK, SCIF1_TXD_MARK,
2208};
2209static const unsigned int scif1_clk_pins[] = {
2210 /* SCK */
2211 RCAR_GP_PIN(4, 13),
2212};
2213static const unsigned int scif1_clk_mux[] = {
2214 SCIF1_SCK_MARK,
2215};
2216static const unsigned int scif1_data_b_pins[] = {
2217 /* RX, TX */
2218 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
2219};
2220static const unsigned int scif1_data_b_mux[] = {
2221 SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK,
2222};
2223static const unsigned int scif1_clk_b_pins[] = {
2224 /* SCK */
2225 RCAR_GP_PIN(5, 10),
2226};
2227static const unsigned int scif1_clk_b_mux[] = {
2228 SCIF1_SCK_B_MARK,
2229};
2230static const unsigned int scif1_data_c_pins[] = {
2231 /* RX, TX */
2232 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
2233};
2234static const unsigned int scif1_data_c_mux[] = {
2235 SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK,
2236};
2237static const unsigned int scif1_clk_c_pins[] = {
2238 /* SCK */
2239 RCAR_GP_PIN(0, 10),
2240};
2241static const unsigned int scif1_clk_c_mux[] = {
2242 SCIF1_SCK_C_MARK,
2243};
2244/* - SCIF2 ------------------------------------------------------------------ */
2245static const unsigned int scif2_data_pins[] = {
2246 /* RX, TX */
2247 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2248};
2249static const unsigned int scif2_data_mux[] = {
2250 SCIF2_RXD_MARK, SCIF2_TXD_MARK,
2251};
2252static const unsigned int scif2_clk_pins[] = {
2253 /* SCK */
2254 RCAR_GP_PIN(4, 18),
2255};
2256static const unsigned int scif2_clk_mux[] = {
2257 SCIF2_SCK_MARK,
2258};
2259static const unsigned int scif2_data_b_pins[] = {
2260 /* RX, TX */
2261 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2262};
2263static const unsigned int scif2_data_b_mux[] = {
2264 SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK,
2265};
2266static const unsigned int scif2_clk_b_pins[] = {
2267 /* SCK */
2268 RCAR_GP_PIN(5, 17),
2269};
2270static const unsigned int scif2_clk_b_mux[] = {
2271 SCIF2_SCK_B_MARK,
2272};
2273static const unsigned int scif2_data_c_pins[] = {
2274 /* RX, TX */
2275 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2276};
2277static const unsigned int scif2_data_c_mux[] = {
2278 SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK,
2279};
2280static const unsigned int scif2_clk_c_pins[] = {
2281 /* SCK */
2282 RCAR_GP_PIN(3, 19),
2283};
2284static const unsigned int scif2_clk_c_mux[] = {
2285 SCIF2_SCK_C_MARK,
2286};
2287/* - SCIF3 ------------------------------------------------------------------ */
2288static const unsigned int scif3_data_pins[] = {
2289 /* RX, TX */
2290 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
2291};
2292static const unsigned int scif3_data_mux[] = {
2293 SCIF3_RXD_MARK, SCIF3_TXD_MARK,
2294};
2295static const unsigned int scif3_clk_pins[] = {
2296 /* SCK */
2297 RCAR_GP_PIN(4, 19),
2298};
2299static const unsigned int scif3_clk_mux[] = {
2300 SCIF3_SCK_MARK,
2301};
2302static const unsigned int scif3_data_b_pins[] = {
2303 /* RX, TX */
2304 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2305};
2306static const unsigned int scif3_data_b_mux[] = {
2307 SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK,
2308};
2309static const unsigned int scif3_clk_b_pins[] = {
2310 /* SCK */
2311 RCAR_GP_PIN(3, 22),
2312};
2313static const unsigned int scif3_clk_b_mux[] = {
2314 SCIF3_SCK_B_MARK,
2315};
2316/* - SCIF4 ------------------------------------------------------------------ */
2317static const unsigned int scif4_data_pins[] = {
2318 /* RX, TX */
2319 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2320};
2321static const unsigned int scif4_data_mux[] = {
2322 SCIF4_RXD_MARK, SCIF4_TXD_MARK,
2323};
2324static const unsigned int scif4_data_b_pins[] = {
2325 /* RX, TX */
2326 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2327};
2328static const unsigned int scif4_data_b_mux[] = {
2329 SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK,
2330};
2331static const unsigned int scif4_data_c_pins[] = {
2332 /* RX, TX */
2333 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
2334};
2335static const unsigned int scif4_data_c_mux[] = {
2336 SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK,
2337};
2338static const unsigned int scif4_data_d_pins[] = {
2339 /* RX, TX */
2340 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
2341};
2342static const unsigned int scif4_data_d_mux[] = {
2343 SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK,
2344};
2345static const unsigned int scif4_data_e_pins[] = {
2346 /* RX, TX */
2347 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
2348};
2349static const unsigned int scif4_data_e_mux[] = {
2350 SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK,
2351};
2352/* - SCIF5 ------------------------------------------------------------------ */
2353static const unsigned int scif5_data_pins[] = {
2354 /* RX, TX */
2355 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2356};
2357static const unsigned int scif5_data_mux[] = {
2358 SCIF5_RXD_MARK, SCIF5_TXD_MARK,
2359};
2360static const unsigned int scif5_data_b_pins[] = {
2361 /* RX, TX */
2362 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2363};
2364static const unsigned int scif5_data_b_mux[] = {
2365 SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK,
2366};
2367static const unsigned int scif5_data_c_pins[] = {
2368 /* RX, TX */
2369 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11),
2370};
2371static const unsigned int scif5_data_c_mux[] = {
2372 SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK,
2373};
2374static const unsigned int scif5_data_d_pins[] = {
2375 /* RX, TX */
2376 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2377};
2378static const unsigned int scif5_data_d_mux[] = {
2379 SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK,
2380};
2381/* - SCIFA0 ----------------------------------------------------------------- */
2382static const unsigned int scifa0_data_pins[] = {
2383 /* RXD, TXD */
2384 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
2385};
2386static const unsigned int scifa0_data_mux[] = {
2387 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2388};
2389static const unsigned int scifa0_data_b_pins[] = {
2390 /* RXD, TXD */
2391 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2392};
2393static const unsigned int scifa0_data_b_mux[] = {
2394 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2395};
2396static const unsigned int scifa0_data_c_pins[] = {
2397 /* RXD, TXD */
2398 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2399};
2400static const unsigned int scifa0_data_c_mux[] = {
2401 SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK
2402};
2403static const unsigned int scifa0_data_d_pins[] = {
2404 /* RXD, TXD */
2405 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2406};
2407static const unsigned int scifa0_data_d_mux[] = {
2408 SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK
2409};
2410/* - SCIFA1 ----------------------------------------------------------------- */
2411static const unsigned int scifa1_data_pins[] = {
2412 /* RXD, TXD */
2413 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2414};
2415static const unsigned int scifa1_data_mux[] = {
2416 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2417};
2418static const unsigned int scifa1_clk_pins[] = {
2419 /* SCK */
2420 RCAR_GP_PIN(0, 13),
2421};
2422static const unsigned int scifa1_clk_mux[] = {
2423 SCIFA1_SCK_MARK,
2424};
2425static const unsigned int scifa1_data_b_pins[] = {
2426 /* RXD, TXD */
2427 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2428};
2429static const unsigned int scifa1_data_b_mux[] = {
2430 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2431};
2432static const unsigned int scifa1_clk_b_pins[] = {
2433 /* SCK */
2434 RCAR_GP_PIN(4, 27),
2435};
2436static const unsigned int scifa1_clk_b_mux[] = {
2437 SCIFA1_SCK_B_MARK,
2438};
2439static const unsigned int scifa1_data_c_pins[] = {
2440 /* RXD, TXD */
2441 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2442};
2443static const unsigned int scifa1_data_c_mux[] = {
2444 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2445};
2446static const unsigned int scifa1_clk_c_pins[] = {
2447 /* SCK */
2448 RCAR_GP_PIN(5, 4),
2449};
2450static const unsigned int scifa1_clk_c_mux[] = {
2451 SCIFA1_SCK_C_MARK,
2452};
2453/* - SCIFA2 ----------------------------------------------------------------- */
2454static const unsigned int scifa2_data_pins[] = {
2455 /* RXD, TXD */
2456 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2457};
2458static const unsigned int scifa2_data_mux[] = {
2459 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2460};
2461static const unsigned int scifa2_clk_pins[] = {
2462 /* SCK */
2463 RCAR_GP_PIN(1, 15),
2464};
2465static const unsigned int scifa2_clk_mux[] = {
2466 SCIFA2_SCK_MARK,
2467};
2468static const unsigned int scifa2_data_b_pins[] = {
2469 /* RXD, TXD */
2470 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0),
2471};
2472static const unsigned int scifa2_data_b_mux[] = {
2473 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
2474};
2475static const unsigned int scifa2_clk_b_pins[] = {
2476 /* SCK */
2477 RCAR_GP_PIN(4, 30),
2478};
2479static const unsigned int scifa2_clk_b_mux[] = {
2480 SCIFA2_SCK_B_MARK,
2481};
2482/* - SCIFA3 ----------------------------------------------------------------- */
2483static const unsigned int scifa3_data_pins[] = {
2484 /* RXD, TXD */
2485 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2486};
2487static const unsigned int scifa3_data_mux[] = {
2488 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2489};
2490static const unsigned int scifa3_clk_pins[] = {
2491 /* SCK */
2492 RCAR_GP_PIN(4, 24),
2493};
2494static const unsigned int scifa3_clk_mux[] = {
2495 SCIFA3_SCK_MARK,
2496};
2497static const unsigned int scifa3_data_b_pins[] = {
2498 /* RXD, TXD */
2499 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
2500};
2501static const unsigned int scifa3_data_b_mux[] = {
2502 SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
2503};
2504static const unsigned int scifa3_clk_b_pins[] = {
2505 /* SCK */
2506 RCAR_GP_PIN(0, 0),
2507};
2508static const unsigned int scifa3_clk_b_mux[] = {
2509 SCIFA3_SCK_B_MARK,
2510};
2511/* - SCIFA4 ----------------------------------------------------------------- */
2512static const unsigned int scifa4_data_pins[] = {
2513 /* RXD, TXD */
2514 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12),
2515};
2516static const unsigned int scifa4_data_mux[] = {
2517 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2518};
2519static const unsigned int scifa4_data_b_pins[] = {
2520 /* RXD, TXD */
2521 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23),
2522};
2523static const unsigned int scifa4_data_b_mux[] = {
2524 SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
2525};
2526static const unsigned int scifa4_data_c_pins[] = {
2527 /* RXD, TXD */
2528 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
2529};
2530static const unsigned int scifa4_data_c_mux[] = {
2531 SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
2532};
2533static const unsigned int scifa4_data_d_pins[] = {
2534 /* RXD, TXD */
2535 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
2536};
2537static const unsigned int scifa4_data_d_mux[] = {
2538 SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK,
2539};
2540/* - SCIFA5 ----------------------------------------------------------------- */
2541static const unsigned int scifa5_data_pins[] = {
2542 /* RXD, TXD */
2543 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
2544};
2545static const unsigned int scifa5_data_mux[] = {
2546 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
2547};
2548static const unsigned int scifa5_data_b_pins[] = {
2549 /* RXD, TXD */
2550 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29),
2551};
2552static const unsigned int scifa5_data_b_mux[] = {
2553 SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
2554};
2555static const unsigned int scifa5_data_c_pins[] = {
2556 /* RXD, TXD */
2557 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
2558};
2559static const unsigned int scifa5_data_c_mux[] = {
2560 SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
2561};
2562static const unsigned int scifa5_data_d_pins[] = {
2563 /* RXD, TXD */
2564 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
2565};
2566static const unsigned int scifa5_data_d_mux[] = {
2567 SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK,
2568};
2569/* - SCIFB0 ----------------------------------------------------------------- */
2570static const unsigned int scifb0_data_pins[] = {
2571 /* RXD, TXD */
2572 RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20),
2573};
2574static const unsigned int scifb0_data_mux[] = {
2575 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
2576};
2577static const unsigned int scifb0_clk_pins[] = {
2578 /* SCK */
2579 RCAR_GP_PIN(0, 19),
2580};
2581static const unsigned int scifb0_clk_mux[] = {
2582 SCIFB0_SCK_MARK,
2583};
2584static const unsigned int scifb0_ctrl_pins[] = {
2585 /* RTS, CTS */
2586 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22),
2587};
2588static const unsigned int scifb0_ctrl_mux[] = {
2589 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
2590};
2591/* - SCIFB1 ----------------------------------------------------------------- */
2592static const unsigned int scifb1_data_pins[] = {
2593 /* RXD, TXD */
2594 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17),
2595};
2596static const unsigned int scifb1_data_mux[] = {
2597 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
2598};
2599static const unsigned int scifb1_clk_pins[] = {
2600 /* SCK */
2601 RCAR_GP_PIN(0, 16),
2602};
2603static const unsigned int scifb1_clk_mux[] = {
2604 SCIFB1_SCK_MARK,
2605};
2606/* - SCIFB2 ----------------------------------------------------------------- */
2607static const unsigned int scifb2_data_pins[] = {
2608 /* RXD, TXD */
2609 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
2610};
2611static const unsigned int scifb2_data_mux[] = {
2612 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
2613};
2614static const unsigned int scifb2_clk_pins[] = {
2615 /* SCK */
2616 RCAR_GP_PIN(1, 15),
2617};
2618static const unsigned int scifb2_clk_mux[] = {
2619 SCIFB2_SCK_MARK,
2620};
2621static const unsigned int scifb2_ctrl_pins[] = {
2622 /* RTS, CTS */
2623 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2624};
2625static const unsigned int scifb2_ctrl_mux[] = {
2626 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
2627};
2628
2629static const struct sh_pfc_pin_group pinmux_groups[] = {
2630 SH_PFC_PIN_GROUP(eth_link),
2631 SH_PFC_PIN_GROUP(eth_magic),
2632 SH_PFC_PIN_GROUP(eth_mdio),
2633 SH_PFC_PIN_GROUP(eth_rmii),
2634 SH_PFC_PIN_GROUP(eth_link_b),
2635 SH_PFC_PIN_GROUP(eth_magic_b),
2636 SH_PFC_PIN_GROUP(eth_mdio_b),
2637 SH_PFC_PIN_GROUP(eth_rmii_b),
2638 SH_PFC_PIN_GROUP(hscif0_data),
2639 SH_PFC_PIN_GROUP(hscif0_clk),
2640 SH_PFC_PIN_GROUP(hscif0_ctrl),
2641 SH_PFC_PIN_GROUP(hscif0_data_b),
2642 SH_PFC_PIN_GROUP(hscif0_clk_b),
2643 SH_PFC_PIN_GROUP(hscif1_data),
2644 SH_PFC_PIN_GROUP(hscif1_clk),
2645 SH_PFC_PIN_GROUP(hscif1_ctrl),
2646 SH_PFC_PIN_GROUP(hscif1_data_b),
2647 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
2648 SH_PFC_PIN_GROUP(hscif2_data),
2649 SH_PFC_PIN_GROUP(hscif2_clk),
2650 SH_PFC_PIN_GROUP(hscif2_ctrl),
2651 SH_PFC_PIN_GROUP(i2c0),
2652 SH_PFC_PIN_GROUP(i2c0_b),
2653 SH_PFC_PIN_GROUP(i2c0_c),
2654 SH_PFC_PIN_GROUP(i2c0_d),
2655 SH_PFC_PIN_GROUP(i2c0_e),
2656 SH_PFC_PIN_GROUP(i2c1),
2657 SH_PFC_PIN_GROUP(i2c1_b),
2658 SH_PFC_PIN_GROUP(i2c1_c),
2659 SH_PFC_PIN_GROUP(i2c1_d),
2660 SH_PFC_PIN_GROUP(i2c1_e),
2661 SH_PFC_PIN_GROUP(i2c2),
2662 SH_PFC_PIN_GROUP(i2c2_b),
2663 SH_PFC_PIN_GROUP(i2c2_c),
2664 SH_PFC_PIN_GROUP(i2c2_d),
2665 SH_PFC_PIN_GROUP(i2c2_e),
2666 SH_PFC_PIN_GROUP(i2c3),
2667 SH_PFC_PIN_GROUP(i2c3_b),
2668 SH_PFC_PIN_GROUP(i2c3_c),
2669 SH_PFC_PIN_GROUP(i2c3_d),
2670 SH_PFC_PIN_GROUP(i2c3_e),
2671 SH_PFC_PIN_GROUP(i2c4),
2672 SH_PFC_PIN_GROUP(i2c4_b),
2673 SH_PFC_PIN_GROUP(i2c4_c),
2674 SH_PFC_PIN_GROUP(i2c4_d),
2675 SH_PFC_PIN_GROUP(i2c4_e),
2676 SH_PFC_PIN_GROUP(intc_irq0),
2677 SH_PFC_PIN_GROUP(intc_irq1),
2678 SH_PFC_PIN_GROUP(intc_irq2),
2679 SH_PFC_PIN_GROUP(intc_irq3),
2680 SH_PFC_PIN_GROUP(intc_irq4),
2681 SH_PFC_PIN_GROUP(intc_irq5),
2682 SH_PFC_PIN_GROUP(intc_irq6),
2683 SH_PFC_PIN_GROUP(intc_irq7),
2684 SH_PFC_PIN_GROUP(intc_irq8),
2685 SH_PFC_PIN_GROUP(intc_irq9),
2686 SH_PFC_PIN_GROUP(msiof0_clk),
2687 SH_PFC_PIN_GROUP(msiof0_sync),
2688 SH_PFC_PIN_GROUP(msiof0_ss1),
2689 SH_PFC_PIN_GROUP(msiof0_ss2),
2690 SH_PFC_PIN_GROUP(msiof0_rx),
2691 SH_PFC_PIN_GROUP(msiof0_tx),
2692 SH_PFC_PIN_GROUP(msiof1_clk),
2693 SH_PFC_PIN_GROUP(msiof1_sync),
2694 SH_PFC_PIN_GROUP(msiof1_ss1),
2695 SH_PFC_PIN_GROUP(msiof1_ss2),
2696 SH_PFC_PIN_GROUP(msiof1_rx),
2697 SH_PFC_PIN_GROUP(msiof1_tx),
2698 SH_PFC_PIN_GROUP(msiof1_clk_b),
2699 SH_PFC_PIN_GROUP(msiof1_sync_b),
2700 SH_PFC_PIN_GROUP(msiof1_ss1_b),
2701 SH_PFC_PIN_GROUP(msiof1_ss2_b),
2702 SH_PFC_PIN_GROUP(msiof1_rx_b),
2703 SH_PFC_PIN_GROUP(msiof1_tx_b),
2704 SH_PFC_PIN_GROUP(msiof2_clk),
2705 SH_PFC_PIN_GROUP(msiof2_sync),
2706 SH_PFC_PIN_GROUP(msiof2_ss1),
2707 SH_PFC_PIN_GROUP(msiof2_ss2),
2708 SH_PFC_PIN_GROUP(msiof2_rx),
2709 SH_PFC_PIN_GROUP(msiof2_tx),
2710 SH_PFC_PIN_GROUP(msiof2_clk_b),
2711 SH_PFC_PIN_GROUP(msiof2_sync_b),
2712 SH_PFC_PIN_GROUP(msiof2_ss1_b),
2713 SH_PFC_PIN_GROUP(msiof2_ss2_b),
2714 SH_PFC_PIN_GROUP(msiof2_rx_b),
2715 SH_PFC_PIN_GROUP(msiof2_tx_b),
2716 SH_PFC_PIN_GROUP(qspi_ctrl),
2717 SH_PFC_PIN_GROUP(qspi_data2),
2718 SH_PFC_PIN_GROUP(qspi_data4),
2719 SH_PFC_PIN_GROUP(scif0_data),
2720 SH_PFC_PIN_GROUP(scif0_clk),
2721 SH_PFC_PIN_GROUP(scif0_data_b),
2722 SH_PFC_PIN_GROUP(scif0_clk_b),
2723 SH_PFC_PIN_GROUP(scif0_data_c),
2724 SH_PFC_PIN_GROUP(scif0_data_d),
2725 SH_PFC_PIN_GROUP(scif1_data),
2726 SH_PFC_PIN_GROUP(scif1_clk),
2727 SH_PFC_PIN_GROUP(scif1_data_b),
2728 SH_PFC_PIN_GROUP(scif1_clk_b),
2729 SH_PFC_PIN_GROUP(scif1_data_c),
2730 SH_PFC_PIN_GROUP(scif1_clk_c),
2731 SH_PFC_PIN_GROUP(scif2_data),
2732 SH_PFC_PIN_GROUP(scif2_clk),
2733 SH_PFC_PIN_GROUP(scif2_data_b),
2734 SH_PFC_PIN_GROUP(scif2_clk_b),
2735 SH_PFC_PIN_GROUP(scif2_data_c),
2736 SH_PFC_PIN_GROUP(scif2_clk_c),
2737 SH_PFC_PIN_GROUP(scif3_data),
2738 SH_PFC_PIN_GROUP(scif3_clk),
2739 SH_PFC_PIN_GROUP(scif3_data_b),
2740 SH_PFC_PIN_GROUP(scif3_clk_b),
2741 SH_PFC_PIN_GROUP(scif4_data),
2742 SH_PFC_PIN_GROUP(scif4_data_b),
2743 SH_PFC_PIN_GROUP(scif4_data_c),
2744 SH_PFC_PIN_GROUP(scif4_data_d),
2745 SH_PFC_PIN_GROUP(scif4_data_e),
2746 SH_PFC_PIN_GROUP(scif5_data),
2747 SH_PFC_PIN_GROUP(scif5_data_b),
2748 SH_PFC_PIN_GROUP(scif5_data_c),
2749 SH_PFC_PIN_GROUP(scif5_data_d),
2750 SH_PFC_PIN_GROUP(scifa0_data),
2751 SH_PFC_PIN_GROUP(scifa0_data_b),
2752 SH_PFC_PIN_GROUP(scifa0_data_c),
2753 SH_PFC_PIN_GROUP(scifa0_data_d),
2754 SH_PFC_PIN_GROUP(scifa1_data),
2755 SH_PFC_PIN_GROUP(scifa1_clk),
2756 SH_PFC_PIN_GROUP(scifa1_data_b),
2757 SH_PFC_PIN_GROUP(scifa1_clk_b),
2758 SH_PFC_PIN_GROUP(scifa1_data_c),
2759 SH_PFC_PIN_GROUP(scifa1_clk_c),
2760 SH_PFC_PIN_GROUP(scifa2_data),
2761 SH_PFC_PIN_GROUP(scifa2_clk),
2762 SH_PFC_PIN_GROUP(scifa2_data_b),
2763 SH_PFC_PIN_GROUP(scifa2_clk_b),
2764 SH_PFC_PIN_GROUP(scifa3_data),
2765 SH_PFC_PIN_GROUP(scifa3_clk),
2766 SH_PFC_PIN_GROUP(scifa3_data_b),
2767 SH_PFC_PIN_GROUP(scifa3_clk_b),
2768 SH_PFC_PIN_GROUP(scifa4_data),
2769 SH_PFC_PIN_GROUP(scifa4_data_b),
2770 SH_PFC_PIN_GROUP(scifa4_data_c),
2771 SH_PFC_PIN_GROUP(scifa4_data_d),
2772 SH_PFC_PIN_GROUP(scifa5_data),
2773 SH_PFC_PIN_GROUP(scifa5_data_b),
2774 SH_PFC_PIN_GROUP(scifa5_data_c),
2775 SH_PFC_PIN_GROUP(scifa5_data_d),
2776 SH_PFC_PIN_GROUP(scifb0_data),
2777 SH_PFC_PIN_GROUP(scifb0_clk),
2778 SH_PFC_PIN_GROUP(scifb0_ctrl),
2779 SH_PFC_PIN_GROUP(scifb1_data),
2780 SH_PFC_PIN_GROUP(scifb1_clk),
2781 SH_PFC_PIN_GROUP(scifb2_data),
2782 SH_PFC_PIN_GROUP(scifb2_clk),
2783 SH_PFC_PIN_GROUP(scifb2_ctrl),
2784};
2785
2786static const char * const eth_groups[] = {
2787 "eth_link",
2788 "eth_magic",
2789 "eth_mdio",
2790 "eth_rmii",
2791 "eth_link_b",
2792 "eth_magic_b",
2793 "eth_mdio_b",
2794 "eth_rmii_b",
2795};
2796
2797static const char * const hscif0_groups[] = {
2798 "hscif0_data",
2799 "hscif0_clk",
2800 "hscif0_ctrl",
2801 "hscif0_data_b",
2802 "hscif0_clk_b",
2803};
2804
2805static const char * const hscif1_groups[] = {
2806 "hscif1_data",
2807 "hscif1_clk",
2808 "hscif1_ctrl",
2809 "hscif1_data_b",
2810 "hscif1_ctrl_b",
2811};
2812
2813static const char * const hscif2_groups[] = {
2814 "hscif2_data",
2815 "hscif2_clk",
2816 "hscif2_ctrl",
2817};
2818
2819static const char * const i2c0_groups[] = {
2820 "i2c0",
2821 "i2c0_b",
2822 "i2c0_c",
2823 "i2c0_d",
2824 "i2c0_e",
2825};
2826
2827static const char * const i2c1_groups[] = {
2828 "i2c1",
2829 "i2c1_b",
2830 "i2c1_c",
2831 "i2c1_d",
2832 "i2c1_e",
2833};
2834
2835static const char * const i2c2_groups[] = {
2836 "i2c2",
2837 "i2c2_b",
2838 "i2c2_c",
2839 "i2c2_d",
2840 "i2c2_e",
2841};
2842
2843static const char * const i2c3_groups[] = {
2844 "i2c3",
2845 "i2c3_b",
2846 "i2c3_c",
2847 "i2c3_d",
2848 "i2c3_e",
2849};
2850
2851static const char * const i2c4_groups[] = {
2852 "i2c4",
2853 "i2c4_b",
2854 "i2c4_c",
2855 "i2c4_d",
2856 "i2c4_e",
2857};
2858
2859static const char * const intc_groups[] = {
2860 "intc_irq0",
2861 "intc_irq1",
2862 "intc_irq2",
2863 "intc_irq3",
2864 "intc_irq4",
2865 "intc_irq5",
2866 "intc_irq6",
2867 "intc_irq7",
2868 "intc_irq8",
2869 "intc_irq9",
2870};
2871
2872static const char * const msiof0_groups[] = {
2873 "msiof0_clk",
2874 "msiof0_sync",
2875 "msiof0_ss1",
2876 "msiof0_ss2",
2877 "msiof0_rx",
2878 "msiof0_tx",
2879};
2880
2881static const char * const msiof1_groups[] = {
2882 "msiof1_clk",
2883 "msiof1_sync",
2884 "msiof1_ss1",
2885 "msiof1_ss2",
2886 "msiof1_rx",
2887 "msiof1_tx",
2888 "msiof1_clk_b",
2889 "msiof1_sync_b",
2890 "msiof1_ss1_b",
2891 "msiof1_ss2_b",
2892 "msiof1_rx_b",
2893 "msiof1_tx_b",
2894};
2895
2896static const char * const msiof2_groups[] = {
2897 "msiof2_clk",
2898 "msiof2_sync",
2899 "msiof2_ss1",
2900 "msiof2_ss2",
2901 "msiof2_rx",
2902 "msiof2_tx",
2903 "msiof2_clk_b",
2904 "msiof2_sync_b",
2905 "msiof2_ss1_b",
2906 "msiof2_ss2_b",
2907 "msiof2_rx_b",
2908 "msiof2_tx_b",
2909};
2910
2911static const char * const qspi_groups[] = {
2912 "qspi_ctrl",
2913 "qspi_data2",
2914 "qspi_data4",
2915};
2916
2917static const char * const scif0_groups[] = {
2918 "scif0_data",
2919 "scif0_clk",
2920 "scif0_data_b",
2921 "scif0_clk_b",
2922 "scif0_data_c",
2923 "scif0_data_d",
2924};
2925
2926static const char * const scif1_groups[] = {
2927 "scif1_data",
2928 "scif1_clk",
2929 "scif1_data_b",
2930 "scif1_clk_b",
2931 "scif1_data_c",
2932 "scif1_clk_c",
2933};
2934
2935static const char * const scif2_groups[] = {
2936 "scif2_data",
2937 "scif2_clk",
2938 "scif2_data_b",
2939 "scif2_clk_b",
2940 "scif2_data_c",
2941 "scif2_clk_c",
2942};
2943
2944static const char * const scif3_groups[] = {
2945 "scif3_data",
2946 "scif3_clk",
2947 "scif3_data_b",
2948 "scif3_clk_b",
2949};
2950
2951static const char * const scif4_groups[] = {
2952 "scif4_data",
2953 "scif4_data_b",
2954 "scif4_data_c",
2955 "scif4_data_d",
2956 "scif4_data_e",
2957};
2958
2959static const char * const scif5_groups[] = {
2960 "scif5_data",
2961 "scif5_data_b",
2962 "scif5_data_c",
2963 "scif5_data_d",
2964};
2965
2966static const char * const scifa0_groups[] = {
2967 "scifa0_data",
2968 "scifa0_data_b",
2969 "scifa0_data_c",
2970 "scifa0_data_d",
2971};
2972
2973static const char * const scifa1_groups[] = {
2974 "scifa1_data",
2975 "scifa1_clk",
2976 "scifa1_data_b",
2977 "scifa1_clk_b",
2978 "scifa1_data_c",
2979 "scifa1_clk_c",
2980};
2981
2982static const char * const scifa2_groups[] = {
2983 "scifa2_data",
2984 "scifa2_clk",
2985 "scifa2_data_b",
2986 "scifa2_clk_b",
2987};
2988
2989static const char * const scifa3_groups[] = {
2990 "scifa3_data",
2991 "scifa3_clk",
2992 "scifa3_data_b",
2993 "scifa3_clk_b",
2994};
2995
2996static const char * const scifa4_groups[] = {
2997 "scifa4_data",
2998 "scifa4_data_b",
2999 "scifa4_data_c",
3000 "scifa4_data_d",
3001};
3002
3003static const char * const scifa5_groups[] = {
3004 "scifa5_data",
3005 "scifa5_data_b",
3006 "scifa5_data_c",
3007 "scifa5_data_d",
3008};
3009
3010static const char * const scifb0_groups[] = {
3011 "scifb0_data",
3012 "scifb0_clk",
3013 "scifb0_ctrl",
3014};
3015
3016static const char * const scifb1_groups[] = {
3017 "scifb1_data",
3018 "scifb1_clk",
3019};
3020
3021static const char * const scifb2_groups[] = {
3022 "scifb2_data",
3023 "scifb2_clk",
3024 "scifb2_ctrl",
3025};
3026
3027static const struct sh_pfc_function pinmux_functions[] = {
3028 SH_PFC_FUNCTION(eth),
3029 SH_PFC_FUNCTION(hscif0),
3030 SH_PFC_FUNCTION(hscif1),
3031 SH_PFC_FUNCTION(hscif2),
3032 SH_PFC_FUNCTION(i2c0),
3033 SH_PFC_FUNCTION(i2c1),
3034 SH_PFC_FUNCTION(i2c2),
3035 SH_PFC_FUNCTION(i2c3),
3036 SH_PFC_FUNCTION(i2c4),
3037 SH_PFC_FUNCTION(intc),
3038 SH_PFC_FUNCTION(msiof0),
3039 SH_PFC_FUNCTION(msiof1),
3040 SH_PFC_FUNCTION(msiof2),
3041 SH_PFC_FUNCTION(qspi),
3042 SH_PFC_FUNCTION(scif0),
3043 SH_PFC_FUNCTION(scif1),
3044 SH_PFC_FUNCTION(scif2),
3045 SH_PFC_FUNCTION(scif3),
3046 SH_PFC_FUNCTION(scif4),
3047 SH_PFC_FUNCTION(scif5),
3048 SH_PFC_FUNCTION(scifa0),
3049 SH_PFC_FUNCTION(scifa1),
3050 SH_PFC_FUNCTION(scifa2),
3051 SH_PFC_FUNCTION(scifa3),
3052 SH_PFC_FUNCTION(scifa4),
3053 SH_PFC_FUNCTION(scifa5),
3054 SH_PFC_FUNCTION(scifb0),
3055 SH_PFC_FUNCTION(scifb1),
3056 SH_PFC_FUNCTION(scifb2),
3057};
3058
3059static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3060 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
3061 GP_0_31_FN, FN_IP2_17_16,
3062 GP_0_30_FN, FN_IP2_15_14,
3063 GP_0_29_FN, FN_IP2_13_12,
3064 GP_0_28_FN, FN_IP2_11_10,
3065 GP_0_27_FN, FN_IP2_9_8,
3066 GP_0_26_FN, FN_IP2_7_6,
3067 GP_0_25_FN, FN_IP2_5_4,
3068 GP_0_24_FN, FN_IP2_3_2,
3069 GP_0_23_FN, FN_IP2_1_0,
3070 GP_0_22_FN, FN_IP1_31_30,
3071 GP_0_21_FN, FN_IP1_29_28,
3072 GP_0_20_FN, FN_IP1_27,
3073 GP_0_19_FN, FN_IP1_26,
3074 GP_0_18_FN, FN_A2,
3075 GP_0_17_FN, FN_IP1_24,
3076 GP_0_16_FN, FN_IP1_23_22,
3077 GP_0_15_FN, FN_IP1_21_20,
3078 GP_0_14_FN, FN_IP1_19_18,
3079 GP_0_13_FN, FN_IP1_17_15,
3080 GP_0_12_FN, FN_IP1_14_13,
3081 GP_0_11_FN, FN_IP1_12_11,
3082 GP_0_10_FN, FN_IP1_10_8,
3083 GP_0_9_FN, FN_IP1_7_6,
3084 GP_0_8_FN, FN_IP1_5_4,
3085 GP_0_7_FN, FN_IP1_3_2,
3086 GP_0_6_FN, FN_IP1_1_0,
3087 GP_0_5_FN, FN_IP0_31_30,
3088 GP_0_4_FN, FN_IP0_29_28,
3089 GP_0_3_FN, FN_IP0_27_26,
3090 GP_0_2_FN, FN_IP0_25,
3091 GP_0_1_FN, FN_IP0_24,
3092 GP_0_0_FN, FN_IP0_23_22, }
3093 },
3094 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
3095 0, 0,
3096 0, 0,
3097 0, 0,
3098 0, 0,
3099 0, 0,
3100 0, 0,
3101 GP_1_25_FN, FN_DACK0,
3102 GP_1_24_FN, FN_IP7_31,
3103 GP_1_23_FN, FN_IP4_1_0,
3104 GP_1_22_FN, FN_WE1_N,
3105 GP_1_21_FN, FN_WE0_N,
3106 GP_1_20_FN, FN_IP3_31,
3107 GP_1_19_FN, FN_IP3_30,
3108 GP_1_18_FN, FN_IP3_29_27,
3109 GP_1_17_FN, FN_IP3_26_24,
3110 GP_1_16_FN, FN_IP3_23_21,
3111 GP_1_15_FN, FN_IP3_20_18,
3112 GP_1_14_FN, FN_IP3_17_15,
3113 GP_1_13_FN, FN_IP3_14_13,
3114 GP_1_12_FN, FN_IP3_12,
3115 GP_1_11_FN, FN_IP3_11,
3116 GP_1_10_FN, FN_IP3_10,
3117 GP_1_9_FN, FN_IP3_9_8,
3118 GP_1_8_FN, FN_IP3_7_6,
3119 GP_1_7_FN, FN_IP3_5_4,
3120 GP_1_6_FN, FN_IP3_3_2,
3121 GP_1_5_FN, FN_IP3_1_0,
3122 GP_1_4_FN, FN_IP2_31_30,
3123 GP_1_3_FN, FN_IP2_29_27,
3124 GP_1_2_FN, FN_IP2_26_24,
3125 GP_1_1_FN, FN_IP2_23_21,
3126 GP_1_0_FN, FN_IP2_20_18, }
3127 },
3128 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
3129 GP_2_31_FN, FN_IP6_7_6,
3130 GP_2_30_FN, FN_IP6_5_4,
3131 GP_2_29_FN, FN_IP6_3_2,
3132 GP_2_28_FN, FN_IP6_1_0,
3133 GP_2_27_FN, FN_IP5_31_30,
3134 GP_2_26_FN, FN_IP5_29_28,
3135 GP_2_25_FN, FN_IP5_27_26,
3136 GP_2_24_FN, FN_IP5_25_24,
3137 GP_2_23_FN, FN_IP5_23_22,
3138 GP_2_22_FN, FN_IP5_21_20,
3139 GP_2_21_FN, FN_IP5_19_18,
3140 GP_2_20_FN, FN_IP5_17_16,
3141 GP_2_19_FN, FN_IP5_15_14,
3142 GP_2_18_FN, FN_IP5_13_12,
3143 GP_2_17_FN, FN_IP5_11_9,
3144 GP_2_16_FN, FN_IP5_8_6,
3145 GP_2_15_FN, FN_IP5_5_4,
3146 GP_2_14_FN, FN_IP5_3_2,
3147 GP_2_13_FN, FN_IP5_1_0,
3148 GP_2_12_FN, FN_IP4_31_30,
3149 GP_2_11_FN, FN_IP4_29_28,
3150 GP_2_10_FN, FN_IP4_27_26,
3151 GP_2_9_FN, FN_IP4_25_23,
3152 GP_2_8_FN, FN_IP4_22_20,
3153 GP_2_7_FN, FN_IP4_19_18,
3154 GP_2_6_FN, FN_IP4_17_16,
3155 GP_2_5_FN, FN_IP4_15_14,
3156 GP_2_4_FN, FN_IP4_13_12,
3157 GP_2_3_FN, FN_IP4_11_10,
3158 GP_2_2_FN, FN_IP4_9_8,
3159 GP_2_1_FN, FN_IP4_7_5,
3160 GP_2_0_FN, FN_IP4_4_2 }
3161 },
3162 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
3163 GP_3_31_FN, FN_IP8_22_20,
3164 GP_3_30_FN, FN_IP8_19_17,
3165 GP_3_29_FN, FN_IP8_16_15,
3166 GP_3_28_FN, FN_IP8_14_12,
3167 GP_3_27_FN, FN_IP8_11_9,
3168 GP_3_26_FN, FN_IP8_8_6,
3169 GP_3_25_FN, FN_IP8_5_3,
3170 GP_3_24_FN, FN_IP8_2_0,
3171 GP_3_23_FN, FN_IP7_29_27,
3172 GP_3_22_FN, FN_IP7_26_24,
3173 GP_3_21_FN, FN_IP7_23_21,
3174 GP_3_20_FN, FN_IP7_20_18,
3175 GP_3_19_FN, FN_IP7_17_15,
3176 GP_3_18_FN, FN_IP7_14_12,
3177 GP_3_17_FN, FN_IP7_11_9,
3178 GP_3_16_FN, FN_IP7_8_6,
3179 GP_3_15_FN, FN_IP7_5_3,
3180 GP_3_14_FN, FN_IP7_2_0,
3181 GP_3_13_FN, FN_IP6_31_29,
3182 GP_3_12_FN, FN_IP6_28_26,
3183 GP_3_11_FN, FN_IP6_25_23,
3184 GP_3_10_FN, FN_IP6_22_20,
3185 GP_3_9_FN, FN_IP6_19_17,
3186 GP_3_8_FN, FN_IP6_16,
3187 GP_3_7_FN, FN_IP6_15,
3188 GP_3_6_FN, FN_IP6_14,
3189 GP_3_5_FN, FN_IP6_13,
3190 GP_3_4_FN, FN_IP6_12,
3191 GP_3_3_FN, FN_IP6_11,
3192 GP_3_2_FN, FN_IP6_10,
3193 GP_3_1_FN, FN_IP6_9,
3194 GP_3_0_FN, FN_IP6_8 }
3195 },
3196 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
3197 GP_4_31_FN, FN_IP11_17_16,
3198 GP_4_30_FN, FN_IP11_15_14,
3199 GP_4_29_FN, FN_IP11_13_11,
3200 GP_4_28_FN, FN_IP11_10_8,
3201 GP_4_27_FN, FN_IP11_7_6,
3202 GP_4_26_FN, FN_IP11_5_3,
3203 GP_4_25_FN, FN_IP11_2_0,
3204 GP_4_24_FN, FN_IP10_31_30,
3205 GP_4_23_FN, FN_IP10_29_27,
3206 GP_4_22_FN, FN_IP10_26_24,
3207 GP_4_21_FN, FN_IP10_23_21,
3208 GP_4_20_FN, FN_IP10_20_18,
3209 GP_4_19_FN, FN_IP10_17_15,
3210 GP_4_18_FN, FN_IP10_14_12,
3211 GP_4_17_FN, FN_IP10_11_9,
3212 GP_4_16_FN, FN_IP10_8_6,
3213 GP_4_15_FN, FN_IP10_5_3,
3214 GP_4_14_FN, FN_IP10_2_0,
3215 GP_4_13_FN, FN_IP9_30_28,
3216 GP_4_12_FN, FN_IP9_27_25,
3217 GP_4_11_FN, FN_IP9_24_22,
3218 GP_4_10_FN, FN_IP9_21_19,
3219 GP_4_9_FN, FN_IP9_18_17,
3220 GP_4_8_FN, FN_IP9_16_15,
3221 GP_4_7_FN, FN_IP9_14_12,
3222 GP_4_6_FN, FN_IP9_11_9,
3223 GP_4_5_FN, FN_IP9_8_6,
3224 GP_4_4_FN, FN_IP9_5_3,
3225 GP_4_3_FN, FN_IP9_2_0,
3226 GP_4_2_FN, FN_IP8_31_29,
3227 GP_4_1_FN, FN_IP8_28_26,
3228 GP_4_0_FN, FN_IP8_25_23 }
3229 },
3230 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
3231 0, 0,
3232 0, 0,
3233 0, 0,
3234 0, 0,
3235 GP_5_27_FN, FN_USB1_OVC,
3236 GP_5_26_FN, FN_USB1_PWEN,
3237 GP_5_25_FN, FN_USB0_OVC,
3238 GP_5_24_FN, FN_USB0_PWEN,
3239 GP_5_23_FN, FN_IP13_26_24,
3240 GP_5_22_FN, FN_IP13_23_21,
3241 GP_5_21_FN, FN_IP13_20_18,
3242 GP_5_20_FN, FN_IP13_17_15,
3243 GP_5_19_FN, FN_IP13_14_12,
3244 GP_5_18_FN, FN_IP13_11_9,
3245 GP_5_17_FN, FN_IP13_8_6,
3246 GP_5_16_FN, FN_IP13_5_3,
3247 GP_5_15_FN, FN_IP13_2_0,
3248 GP_5_14_FN, FN_IP12_29_27,
3249 GP_5_13_FN, FN_IP12_26_24,
3250 GP_5_12_FN, FN_IP12_23_21,
3251 GP_5_11_FN, FN_IP12_20_18,
3252 GP_5_10_FN, FN_IP12_17_15,
3253 GP_5_9_FN, FN_IP12_14_13,
3254 GP_5_8_FN, FN_IP12_12_11,
3255 GP_5_7_FN, FN_IP12_10_9,
3256 GP_5_6_FN, FN_IP12_8_6,
3257 GP_5_5_FN, FN_IP12_5_3,
3258 GP_5_4_FN, FN_IP12_2_0,
3259 GP_5_3_FN, FN_IP11_29_27,
3260 GP_5_2_FN, FN_IP11_26_24,
3261 GP_5_1_FN, FN_IP11_23_21,
3262 GP_5_0_FN, FN_IP11_20_18 }
3263 },
3264 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
3265 0, 0,
3266 0, 0,
3267 0, 0,
3268 0, 0,
3269 0, 0,
3270 0, 0,
3271 GP_6_25_FN, FN_IP0_21_20,
3272 GP_6_24_FN, FN_IP0_19_18,
3273 GP_6_23_FN, FN_IP0_17,
3274 GP_6_22_FN, FN_IP0_16,
3275 GP_6_21_FN, FN_IP0_15,
3276 GP_6_20_FN, FN_IP0_14,
3277 GP_6_19_FN, FN_IP0_13,
3278 GP_6_18_FN, FN_IP0_12,
3279 GP_6_17_FN, FN_IP0_11,
3280 GP_6_16_FN, FN_IP0_10,
3281 GP_6_15_FN, FN_IP0_9_8,
3282 GP_6_14_FN, FN_IP0_0,
3283 GP_6_13_FN, FN_SD1_DATA3,
3284 GP_6_12_FN, FN_SD1_DATA2,
3285 GP_6_11_FN, FN_SD1_DATA1,
3286 GP_6_10_FN, FN_SD1_DATA0,
3287 GP_6_9_FN, FN_SD1_CMD,
3288 GP_6_8_FN, FN_SD1_CLK,
3289 GP_6_7_FN, FN_SD0_WP,
3290 GP_6_6_FN, FN_SD0_CD,
3291 GP_6_5_FN, FN_SD0_DATA3,
3292 GP_6_4_FN, FN_SD0_DATA2,
3293 GP_6_3_FN, FN_SD0_DATA1,
3294 GP_6_2_FN, FN_SD0_DATA0,
3295 GP_6_1_FN, FN_SD0_CMD,
3296 GP_6_0_FN, FN_SD0_CLK }
3297 },
3298 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
3299 2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
3300 2, 1, 1, 1, 1, 1, 1, 1, 1) {
3301 /* IP0_31_30 [2] */
3302 FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
3303 /* IP0_29_28 [2] */
3304 FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
3305 /* IP0_27_26 [2] */
3306 FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
3307 /* IP0_25 [1] */
3308 FN_D2, FN_SCIFA3_TXD_B,
3309 /* IP0_24 [1] */
3310 FN_D1, FN_SCIFA3_RXD_B,
3311 /* IP0_23_22 [2] */
3312 FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
3313 /* IP0_21_20 [2] */
3314 FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
3315 /* IP0_19_18 [2] */
3316 FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX,
3317 /* IP0_17 [1] */
3318 FN_MMC_D5, FN_SD2_WP,
3319 /* IP0_16 [1] */
3320 FN_MMC_D4, FN_SD2_CD,
3321 /* IP0_15 [1] */
3322 FN_MMC_D3, FN_SD2_DATA3,
3323 /* IP0_14 [1] */
3324 FN_MMC_D2, FN_SD2_DATA2,
3325 /* IP0_13 [1] */
3326 FN_MMC_D1, FN_SD2_DATA1,
3327 /* IP0_12 [1] */
3328 FN_MMC_D0, FN_SD2_DATA0,
3329 /* IP0_11 [1] */
3330 FN_MMC_CMD, FN_SD2_CMD,
3331 /* IP0_10 [1] */
3332 FN_MMC_CLK, FN_SD2_CLK,
3333 /* IP0_9_8 [2] */
3334 FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
3335 /* IP0_7 [1] */
3336 0, 0,
3337 /* IP0_6 [1] */
3338 0, 0,
3339 /* IP0_5 [1] */
3340 0, 0,
3341 /* IP0_4 [1] */
3342 0, 0,
3343 /* IP0_3 [1] */
3344 0, 0,
3345 /* IP0_2 [1] */
3346 0, 0,
3347 /* IP0_1 [1] */
3348 0, 0,
3349 /* IP0_0 [1] */
3350 FN_SD1_CD, FN_CAN0_RX, }
3351 },
3352 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
3353 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2,
3354 2, 2) {
3355 /* IP1_31_30 [2] */
3356 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
3357 /* IP1_29_28 [2] */
3358 FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
3359 /* IP1_27 [1] */
3360 FN_A4, FN_SCIFB0_TXD,
3361 /* IP1_26 [1] */
3362 FN_A3, FN_SCIFB0_SCK,
3363 /* IP1_25 [1] */
3364 0, 0,
3365 /* IP1_24 [1] */
3366 FN_A1, FN_SCIFB1_TXD,
3367 /* IP1_23_22 [2] */
3368 FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0,
3369 /* IP1_21_20 [2] */
3370 FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, 0,
3371 /* IP1_19_18 [2] */
3372 FN_D14, FN_SCIFA1_RXD, FN_IIC0_SCL_B, 0,
3373 /* IP1_17_15 [3] */
3374 FN_D13, FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B,
3375 0, 0, 0,
3376 /* IP1_14_13 [2] */
3377 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
3378 /* IP1_12_11 [2] */
3379 FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
3380 /* IP1_10_8 [3] */
3381 FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
3382 0, 0, 0,
3383 /* IP1_7_6 [2] */
3384 FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0,
3385 /* IP1_5_4 [2] */
3386 FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0,
3387 /* IP1_3_2 [2] */
3388 FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
3389 /* IP1_1_0 [2] */
3390 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, }
3391 },
3392 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
3393 2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
3394 /* IP2_31_30 [2] */
3395 FN_A20, FN_SPCLK, FN_MOUT1, 0,
3396 /* IP2_29_27 [3] */
3397 FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
3398 FN_MOUT0, 0, 0, 0,
3399 /* IP2_26_24 [3] */
3400 FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
3401 FN_AVB_AVTP_MATCH_B, 0, 0, 0,
3402 /* IP2_23_21 [3] */
3403 FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
3404 FN_AVB_AVTP_CAPTURE_B, 0, 0, 0,
3405 /* IP2_20_18 [3] */
3406 FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN,
3407 FN_VSP, FN_CAN_CLK_C, FN_TPUTO2_B, 0,
3408 /* IP2_17_16 [2] */
3409 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
3410 /* IP2_15_14 [2] */
3411 FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
3412 /* IP2_13_12 [2] */
3413 FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0,
3414 /* IP2_11_10 [2] */
3415 FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0,
3416 /* IP2_9_8 [2] */
3417 FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B, 0,
3418 /* IP2_7_6 [2] */
3419 FN_A10, FN_MSIOF1_SCK, FN_IIC1_SCL_B, 0,
3420 /* IP2_5_4 [2] */
3421 FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0,
3422 /* IP2_3_2 [2] */
3423 FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0,
3424 /* IP2_1_0 [2] */
3425 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, }
3426 },
3427 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
3428 1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 2, 2, 2, 2) {
3429 /* IP3_31 [1] */
3430 FN_RD_WR_N, FN_ATAG1_N,
3431 /* IP3_30 [1] */
3432 FN_RD_N, FN_ATACS11_N,
3433 /* IP3_29_27 [3] */
3434 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
3435 FN_MTS_N_B, 0, 0,
3436 /* IP3_26_24 [3] */
3437 FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B,
3438 FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B,
3439 /* IP3_23_21 [3] */
3440 FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B,
3441 FN_RIF0_D0, FN_FMCLK, FN_SCIFB2_CTS_N, FN_SCKZ_B,
3442 /* IP3_20_18 [3] */
3443 FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
3444 FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B,
3445 /* IP3_17_15 [3] */
3446 FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B,
3447 FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD, FN_SDATA_B,
3448 /* IP3_14_13 [2] */
3449 FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
3450 /* IP3_12 [1] */
3451 FN_EX_CS0_N, FN_VI1_DATA10,
3452 /* IP3_11 [1] */
3453 FN_CS1_N_A26, FN_VI1_DATA9,
3454 /* IP3_10 [1] */
3455 FN_CS0_N, FN_VI1_DATA8,
3456 /* IP3_9_8 [2] */
3457 FN_A25, FN_SSL, FN_ATARD1_N, 0,
3458 /* IP3_7_6 [2] */
3459 FN_A24, FN_IO3, FN_EX_WAIT2, 0,
3460 /* IP3_5_4 [2] */
3461 FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N,
3462 /* IP3_3_2 [2] */
3463 FN_A22, FN_MISO_IO1, FN_MOUT5, FN_ATADIR1_N,
3464 /* IP3_1_0 [2] */
3465 FN_A21, FN_MOSI_IO0, FN_MOUT2, 0, }
3466 },
3467 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
3468 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) {
3469 /* IP4_31_30 [2] */
3470 FN_DU0_DG4, FN_LCDOUT12, FN_CC50_STATE12, 0,
3471 /* IP4_29_28 [2] */
3472 FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, 0,
3473 /* IP4_27_26 [2] */
3474 FN_DU0_DG2, FN_LCDOUT10, FN_CC50_STATE10, 0,
3475 /* IP4_25_23 [3] */
3476 FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
3477 FN_CC50_STATE9, 0, 0, 0,
3478 /* IP4_22_20 [3] */
3479 FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
3480 FN_CC50_STATE8, 0, 0, 0,
3481 /* IP4_19_18 [2] */
3482 FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, 0,
3483 /* IP4_17_16 [2] */
3484 FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6, 0,
3485 /* IP4_15_14 [2] */
3486 FN_DU0_DR5, FN_LCDOUT21, FN_CC50_STATE5, 0,
3487 /* IP4_13_12 [2] */
3488 FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, 0,
3489 /* IP4_11_10 [2] */
3490 FN_DU0_DR3, FN_LCDOUT19, FN_CC50_STATE3, 0,
3491 /* IP4_9_8 [2] */
3492 FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, 0,
3493 /* IP4_7_5 [3] */
3494 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
3495 FN_CC50_STATE1, 0, 0, 0,
3496 /* IP4_4_2 [3] */
3497 FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
3498 FN_CC50_STATE0, 0, 0, 0,
3499 /* IP4_1_0 [2] */
3500 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, }
3501 },
3502 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
3503 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) {
3504 /* IP5_31_30 [2] */
3505 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27, 0,
3506 /* IP5_29_28 [2] */
3507 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_CC50_STATE26, 0,
3508 /* IP5_27_26 [2] */
3509 FN_DU0_DOTCLKOUT0, FN_QCLK, FN_CC50_STATE25, 0,
3510 /* IP5_25_24 [2] */
3511 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, 0,
3512 /* IP5_23_22 [2] */
3513 FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23, 0,
3514 /* IP5_21_20 [2] */
3515 FN_DU0_DB6, FN_LCDOUT6, FN_CC50_STATE22, 0,
3516 /* IP5_19_18 [2] */
3517 FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, 0,
3518 /* IP5_17_16 [2] */
3519 FN_DU0_DB4, FN_LCDOUT4, FN_CC50_STATE20, 0,
3520 /* IP5_15_14 [2] */
3521 FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, 0,
3522 /* IP5_13_12 [2] */
3523 FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18, 0,
3524 /* IP5_11_9 [3] */
3525 FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
3526 FN_CAN0_TX_C, FN_CC50_STATE17, 0, 0,
3527 /* IP5_8_6 [3] */
3528 FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D,
3529 FN_CAN0_RX_C, FN_CC50_STATE16, 0, 0,
3530 /* IP5_5_4 [2] */
3531 FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, 0,
3532 /* IP5_3_2 [2] */
3533 FN_DU0_DG6, FN_LCDOUT14, FN_CC50_STATE14, 0,
3534 /* IP5_1_0 [2] */
3535 FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, 0, }
3536 },
3537 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
3538 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
3539 2, 2) {
3540 /* IP6_31_29 [3] */
3541 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D,
3542 FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0,
3543 /* IP6_28_26 [3] */
3544 FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
3545 FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
3546 /* IP6_25_23 [3] */
3547 FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
3548 FN_AVB_COL, 0, 0, 0,
3549 /* IP6_22_20 [3] */
3550 FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
3551 FN_AVB_RX_ER, 0, 0, 0,
3552 /* IP6_19_17 [3] */
3553 FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
3554 FN_AVB_RXD7, 0, 0, 0,
3555 /* IP6_16 [1] */
3556 FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
3557 /* IP6_15 [1] */
3558 FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
3559 /* IP6_14 [1] */
3560 FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
3561 /* IP6_13 [1] */
3562 FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
3563 /* IP6_12 [1] */
3564 FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
3565 /* IP6_11 [1] */
3566 FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
3567 /* IP6_10 [1] */
3568 FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
3569 /* IP6_9 [1] */
3570 FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
3571 /* IP6_8 [1] */
3572 FN_VI0_CLK, FN_AVB_RX_CLK,
3573 /* IP6_7_6 [2] */
3574 FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0,
3575 /* IP6_5_4 [2] */
3576 FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0,
3577 /* IP6_3_2 [2] */
3578 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
3579 /* IP6_1_0 [2] */
3580 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, }
3581 },
3582 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
3583 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
3584 /* IP7_31 [1] */
3585 FN_DREQ0_N, FN_SCIFB1_RXD,
3586 /* IP7_30 [1] */
3587 0, 0,
3588 /* IP7_29_27 [3] */
3589 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
3590 FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
3591 /* IP7_26_24 [3] */
3592 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
3593 FN_SSI_SCK6_B, 0, 0, 0,
3594 /* IP7_23_21 [3] */
3595 FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D,
3596 FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
3597 /* IP7_20_18 [3] */
3598 FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D,
3599 FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
3600 /* IP7_17_15 [3] */
3601 FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
3602 FN_SSI_SCK5_B, 0, 0, 0,
3603 /* IP7_14_12 [3] */
3604 FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
3605 FN_AVB_TXD4, FN_ADICHS2, 0, 0,
3606 /* IP7_11_9 [3] */
3607 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
3608 FN_AVB_TXD3, FN_ADICHS1, 0, 0,
3609 /* IP7_8_6 [3] */
3610 FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
3611 FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0,
3612 /* IP7_5_3 [3] */
3613 FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
3614 FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0,
3615 /* IP7_2_0 [3] */
3616 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D,
3617 FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, }
3618 },
3619 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
3620 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) {
3621 /* IP8_31_29 [3] */
3622 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
3623 FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
3624 /* IP8_28_26 [3] */
3625 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
3626 FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0,
3627 /* IP8_25_23 [3] */
3628 FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
3629 FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
3630 /* IP8_22_20 [3] */
3631 FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
3632 FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
3633 /* IP8_19_17 [3] */
3634 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
3635 FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
3636 /* IP8_16_15 [2] */
3637 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
3638 /* IP8_14_12 [3] */
3639 FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
3640 FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
3641 /* IP8_11_9 [3] */
3642 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
3643 FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
3644 /* IP8_8_6 [3] */
3645 FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
3646 FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
3647 /* IP8_5_3 [3] */
3648 FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
3649 FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
3650 /* IP8_2_0 [3] */
3651 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
3652 FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, }
3653 },
3654 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
3655 1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3, 3) {
3656 /* IP9_31 [1] */
3657 0, 0,
3658 /* IP9_30_28 [3] */
3659 FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5,
3660 FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34, 0,
3661 /* IP9_27_25 [3] */
3662 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4,
3663 FN_SSI_WS1_B, FN_CAN_STEP0, FN_CC50_STATE33, 0,
3664 /* IP9_24_22 [3] */
3665 FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3,
3666 FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32, 0,
3667 /* IP9_21_19 [3] */
3668 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2,
3669 FN_REMOCON_B, FN_SPEEDIN_B, FN_VSP_B, 0,
3670 /* IP9_18_17 [2] */
3671 FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
3672 /* IP9_16_15 [2] */
3673 FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
3674 /* IP9_14_12 [3] */
3675 FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
3676 FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, 0,
3677 /* IP9_11_9 [3] */
3678 FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6,
3679 FN_RIF1_D0, FN_FMCLK_B, FN_RDS_CLK_B, 0,
3680 /* IP9_8_6 [3] */
3681 FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5,
3682 FN_RIF1_CLK, FN_BPFCLK_B, 0, 0,
3683 /* IP9_5_3 [3] */
3684 FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4,
3685 FN_RIF1_SYNC, FN_TPUTO1_C, 0, 0,
3686 /* IP9_2_0 [3] */
3687 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
3688 FN_RIF1_D1_B, FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, }
3689 },
3690 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
3691 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
3692 /* IP10_31_30 [2] */
3693 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10,
3694 /* IP10_29_27 [3] */
3695 FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
3696 FN_CAN_DEBUGOUT9, 0, 0, 0,
3697 /* IP10_26_24 [3] */
3698 FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
3699 FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, 0, 0,
3700 /* IP10_23_21 [3] */
3701 FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5,
3702 FN_AUDIO_CLKB_C, FN_SSI_WS4_B, FN_CAN_DEBUGOUT7, FN_RDS_DATA_C,
3703 /* IP10_20_18 [3] */
3704 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4,
3705 FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C,
3706 /* IP10_17_15 [3] */
3707 FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
3708 FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT,
3709 /* IP10_14_12 [3] */
3710 FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
3711 FN_USB0_IDIN, FN_CAN_DEBUGOUT4, FN_CC50_STATE39, 0,
3712 /* IP10_11_9 [3] */
3713 FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
3714 FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, 0,
3715 /* IP10_8_6 [3] */
3716 FN_SCIF2_RXD, FN_IIC1_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
3717 FN_USB0_EXTLP, FN_CAN_DEBUGOUT2, FN_CC50_STATE37, 0,
3718 /* IP10_5_3 [3] */
3719 FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
3720 FN_CAN_DEBUGOUT1, FN_CC50_STATE36, 0, 0,
3721 /* IP10_2_0 [3] */
3722 FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
3723 FN_CAN_DEBUGOUT0, FN_CC50_STATE35, 0, 0, }
3724 },
3725 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
3726 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) {
3727 /* IP11_31_30 [2] */
3728 0, 0, 0, 0,
3729 /* IP11_29_27 [3] */
3730 FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
3731 FN_AD_CLK_B, 0, 0, 0,
3732 /* IP11_26_24 [3] */
3733 FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
3734 FN_AD_DO_B, 0, 0, 0,
3735 /* IP11_23_21 [3] */
3736 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
3737 FN_AD_DI_B, FN_PCMWE_N, 0, 0,
3738 /* IP11_20_18 [3] */
3739 FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
3740 FN_CAN_CLK_D, FN_PCMOE_N, 0, 0,
3741 /* IP11_17_16 [2] */
3742 FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE,
3743 /* IP11_15_14 [2] */
3744 FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP,
3745 /* IP11_13_11 [3] */
3746 FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
3747 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0,
3748 /* IP11_10_8 [3] */
3749 FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
3750 FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0,
3751 /* IP11_7_6 [2] */
3752 FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
3753 FN_CAN_DEBUGOUT13,
3754 /* IP11_5_3 [3] */
3755 FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
3756 FN_CAN_DEBUGOUT12, 0, 0, 0,
3757 /* IP11_2_0 [3] */
3758 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
3759 FN_CAN_DEBUGOUT11, 0, 0, 0, }
3760 },
3761 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
3762 2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) {
3763 /* IP12_31_30 [2] */
3764 0, 0, 0, 0,
3765 /* IP12_29_27 [3] */
3766 FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_MDATA,
3767 FN_ATAWR0_N, FN_ETH_RXD1_B, 0, 0,
3768 /* IP12_26_24 [3] */
3769 FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_SDATA,
3770 FN_ATAG0_N, FN_ETH_RXD0_B, 0, 0,
3771 /* IP12_23_21 [3] */
3772 FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC1_SDA_C, FN_VI1_DATA0,
3773 FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, FN_ETH_RX_ER_B, 0,
3774 /* IP12_20_18 [3] */
3775 FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK,
3776 FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, 0,
3777 /* IP12_17_15 [3] */
3778 FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
3779 FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0,
3780 /* IP12_14_13 [2] */
3781 FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, FN_IRD_SCK,
3782 /* IP12_12_11 [2] */
3783 FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX,
3784 /* IP12_10_9 [2] */
3785 FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX,
3786 /* IP12_8_6 [3] */
3787 FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
3788 FN_CAN1_TX_C, FN_DREQ2_N, 0, 0,
3789 /* IP12_5_3 [3] */
3790 FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
3791 FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
3792 /* IP12_2_0 [3] */
3793 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
3794 FN_AD_NCS_N_B, FN_DREQ1_N_B, 0, 0, }
3795 },
3796 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
3797 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
3798 /* IP13_31 [1] */
3799 0, 0,
3800 /* IP13_30 [1] */
3801 0, 0,
3802 /* IP13_29 [1] */
3803 0, 0,
3804 /* IP13_28 [1] */
3805 0, 0,
3806 /* IP13_27 [1] */
3807 0, 0,
3808 /* IP13_26_24 [3] */
3809 FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
3810 FN_TS_SPSYNC_C, FN_RIF0_D1_B, FN_FMIN_E, FN_RDS_DATA_D,
3811 /* IP13_23_21 [3] */
3812 FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
3813 FN_TS_SDEN_C, FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D,
3814 /* IP13_20_18 [3] */
3815 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
3816 FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B,
3817 /* IP13_17_15 [3] */
3818 FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
3819 FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B, 0,
3820 /* IP13_14_12 [3] */
3821 FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
3822 FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0,
3823 /* IP13_11_9 [3] */
3824 FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6,
3825 FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0,
3826 /* IP13_8_6 [3] */
3827 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5,
3828 FN_MTS_N, FN_EX_WAIT1, FN_ETH_TXD1_B, 0,
3829 /* IP13_5_3 [2] */
3830 FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D,
3831 FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
3832 /* IP13_2_0 [3] */
3833 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
3834 FN_SCKZ, FN_ATACS00_N, FN_ETH_LINK_B, 0, }
3835 },
3836 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
3837 2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3,
3838 2, 1) {
3839 /* SEL_ADG [2] */
3840 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
3841 /* SEL_ADI [1] */
3842 FN_SEL_ADI_0, FN_SEL_ADI_1,
3843 /* SEL_CAN [2] */
3844 FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
3845 /* SEL_DARC [3] */
3846 FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
3847 FN_SEL_DARC_4, 0, 0, 0,
3848 /* SEL_DR0 [1] */
3849 FN_SEL_DR0_0, FN_SEL_DR0_1,
3850 /* SEL_DR1 [1] */
3851 FN_SEL_DR1_0, FN_SEL_DR1_1,
3852 /* SEL_DR2 [1] */
3853 FN_SEL_DR2_0, FN_SEL_DR2_1,
3854 /* SEL_DR3 [1] */
3855 FN_SEL_DR3_0, FN_SEL_DR3_1,
3856 /* SEL_ETH [1] */
3857 FN_SEL_ETH_0, FN_SEL_ETH_1,
3858 /* SLE_FSN [1] */
3859 FN_SEL_FSN_0, FN_SEL_FSN_1,
3860 /* SEL_IC200 [3] */
3861 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
3862 FN_SEL_I2C00_4, 0, 0, 0,
3863 /* SEL_I2C01 [3] */
3864 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
3865 FN_SEL_I2C01_4, 0, 0, 0,
3866 /* SEL_I2C02 [3] */
3867 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
3868 FN_SEL_I2C02_4, 0, 0, 0,
3869 /* SEL_I2C03 [3] */
3870 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
3871 FN_SEL_I2C03_4, 0, 0, 0,
3872 /* SEL_I2C04 [3] */
3873 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
3874 FN_SEL_I2C04_4, 0, 0, 0,
3875 /* SEL_IIC00 [2] */
3876 FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3,
3877 /* SEL_AVB [1] */
3878 FN_SEL_AVB_0, FN_SEL_AVB_1, }
3879 },
3880 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
3881 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
3882 2, 2, 2, 1, 1, 2) {
3883 /* SEL_IEB [2] */
3884 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
3885 /* SEL_IIC0 [2] */
3886 FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3,
3887 /* SEL_LBS [1] */
3888 FN_SEL_LBS_0, FN_SEL_LBS_1,
3889 /* SEL_MSI1 [1] */
3890 FN_SEL_MSI1_0, FN_SEL_MSI1_1,
3891 /* SEL_MSI2 [1] */
3892 FN_SEL_MSI2_0, FN_SEL_MSI2_1,
3893 /* SEL_RAD [1] */
3894 FN_SEL_RAD_0, FN_SEL_RAD_1,
3895 /* SEL_RCN [1] */
3896 FN_SEL_RCN_0, FN_SEL_RCN_1,
3897 /* SEL_RSP [1] */
3898 FN_SEL_RSP_0, FN_SEL_RSP_1,
3899 /* SEL_SCIFA0 [2] */
3900 FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
3901 FN_SEL_SCIFA0_3,
3902 /* SEL_SCIFA1 [2] */
3903 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
3904 /* SEL_SCIFA2 [1] */
3905 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
3906 /* SEL_SCIFA3 [1] */
3907 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
3908 /* SEL_SCIFA4 [2] */
3909 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
3910 FN_SEL_SCIFA4_3,
3911 /* SEL_SCIFA5 [2] */
3912 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
3913 FN_SEL_SCIFA5_3,
3914 /* SEL_SPDM [1] */
3915 FN_SEL_SPDM_0, FN_SEL_SPDM_1,
3916 /* SEL_TMU [1] */
3917 FN_SEL_TMU_0, FN_SEL_TMU_1,
3918 /* SEL_TSIF0 [2] */
3919 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
3920 /* SEL_CAN0 [2] */
3921 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
3922 /* SEL_CAN1 [2] */
3923 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
3924 /* SEL_HSCIF0 [1] */
3925 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
3926 /* SEL_HSCIF1 [1] */
3927 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
3928 /* SEL_RDS [2] */
3929 FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, }
3930 },
3931 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
3932 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
3933 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
3934 /* SEL_SCIF0 [2] */
3935 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
3936 /* SEL_SCIF1 [2] */
3937 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
3938 /* SEL_SCIF2 [2] */
3939 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
3940 /* SEL_SCIF3 [1] */
3941 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
3942 /* SEL_SCIF4 [3] */
3943 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
3944 FN_SEL_SCIF4_4, 0, 0, 0,
3945 /* SEL_SCIF5 [2] */
3946 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
3947 /* SEL_SSI1 [1] */
3948 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
3949 /* SEL_SSI2 [1] */
3950 FN_SEL_SSI2_0, FN_SEL_SSI2_1,
3951 /* SEL_SSI4 [1] */
3952 FN_SEL_SSI4_0, FN_SEL_SSI4_1,
3953 /* SEL_SSI5 [1] */
3954 FN_SEL_SSI5_0, FN_SEL_SSI5_1,
3955 /* SEL_SSI6 [1] */
3956 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
3957 /* SEL_SSI7 [1] */
3958 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
3959 /* SEL_SSI8 [1] */
3960 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
3961 /* SEL_SSI9 [1] */
3962 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
3963 /* RESERVED [1] */
3964 0, 0,
3965 /* RESERVED [1] */
3966 0, 0,
3967 /* RESERVED [1] */
3968 0, 0,
3969 /* RESERVED [1] */
3970 0, 0,
3971 /* RESERVED [1] */
3972 0, 0,
3973 /* RESERVED [1] */
3974 0, 0,
3975 /* RESERVED [1] */
3976 0, 0,
3977 /* RESERVED [1] */
3978 0, 0,
3979 /* RESERVED [1] */
3980 0, 0,
3981 /* RESERVED [1] */
3982 0, 0,
3983 /* RESERVED [1] */
3984 0, 0,
3985 /* RESERVED [1] */
3986 0, 0, }
3987 },
3988 { },
3989};
3990
3991const struct sh_pfc_soc_info r8a7794_pinmux_info = {
3992 .name = "r8a77940_pfc",
3993 .unlock_reg = 0xe6060000, /* PMMR */
3994
3995 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3996
3997 .pins = pinmux_pins,
3998 .nr_pins = ARRAY_SIZE(pinmux_pins),
3999 .groups = pinmux_groups,
4000 .nr_groups = ARRAY_SIZE(pinmux_groups),
4001 .functions = pinmux_functions,
4002 .nr_functions = ARRAY_SIZE(pinmux_functions),
4003
4004 .cfg_regs = pinmux_config_regs,
4005
4006 .gpio_data = pinmux_data,
4007 .gpio_data_size = ARRAY_SIZE(pinmux_data),
4008};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 01:31:46 -0400