diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2015-08-20 00:54:23 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2015-08-27 22:40:49 -0400 |
commit | 43a70661eaa64aa4e36e421eee3b9ded3190837b (patch) | |
tree | c0792db927aec0ba026039edb894c9460d252c7e | |
parent | 340b0e7c500a0ac8fb649c58cf8528550642c1d8 (diff) |
drm/nouveau/tegra: merge platform setup from nouveau drm
The copyright header in nvkm/engine/device/platform.c has been replaced
with the NVIDIA one from drm/nouveau_platform.c, as most of the actual
code is now theirs.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r-- | drivers/gpu/drm/nouveau/include/nvif/os.h | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/include/nvkm/core/device.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h | 20 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_platform.c | 224 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_platform.h | 37 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 181 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c | 20 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c | 11 |
9 files changed, 221 insertions, 285 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvif/os.h b/drivers/gpu/drm/nouveau/include/nvif/os.h index 97317f7fe4e5..3accc99d8e0b 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/os.h +++ b/drivers/gpu/drm/nouveau/include/nvif/os.h | |||
@@ -25,10 +25,13 @@ | |||
25 | #include <linux/clk.h> | 25 | #include <linux/clk.h> |
26 | #include <linux/regulator/consumer.h> | 26 | #include <linux/regulator/consumer.h> |
27 | #include <linux/agp_backend.h> | 27 | #include <linux/agp_backend.h> |
28 | #include <linux/reset.h> | ||
29 | #include <linux/iommu.h> | ||
28 | 30 | ||
29 | #include <asm/unaligned.h> | 31 | #include <asm/unaligned.h> |
30 | 32 | ||
31 | #include <soc/tegra/fuse.h> | 33 | #include <soc/tegra/fuse.h> |
34 | #include <soc/tegra/pmc.h> | ||
32 | 35 | ||
33 | #ifndef ioread32_native | 36 | #ifndef ioread32_native |
34 | #ifdef __BIG_ENDIAN | 37 | #ifdef __BIG_ENDIAN |
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h index 773951bfd200..8f760002e401 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h | |||
@@ -139,8 +139,6 @@ struct nvkm_device { | |||
139 | struct nvkm_sw *sw; | 139 | struct nvkm_sw *sw; |
140 | struct nvkm_engine *vic; | 140 | struct nvkm_engine *vic; |
141 | struct nvkm_engine *vp; | 141 | struct nvkm_engine *vp; |
142 | |||
143 | struct nouveau_platform_gpu *gpu; | ||
144 | }; | 142 | }; |
145 | 143 | ||
146 | struct nvkm_subdev *nvkm_device_subdev(struct nvkm_device *, int index); | 144 | struct nvkm_subdev *nvkm_device_subdev(struct nvkm_device *, int index); |
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h b/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h index 1755c2d30fcd..5aa2480da25f 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h | |||
@@ -1,11 +1,31 @@ | |||
1 | #ifndef __NVKM_DEVICE_TEGRA_H__ | 1 | #ifndef __NVKM_DEVICE_TEGRA_H__ |
2 | #define __NVKM_DEVICE_TEGRA_H__ | 2 | #define __NVKM_DEVICE_TEGRA_H__ |
3 | #include <core/device.h> | 3 | #include <core/device.h> |
4 | #include <core/mm.h> | ||
4 | 5 | ||
5 | struct nvkm_device_tegra { | 6 | struct nvkm_device_tegra { |
6 | struct nvkm_device device; | 7 | struct nvkm_device device; |
7 | struct platform_device *pdev; | 8 | struct platform_device *pdev; |
8 | int irq; | 9 | int irq; |
10 | |||
11 | struct reset_control *rst; | ||
12 | struct clk *clk; | ||
13 | struct clk *clk_pwr; | ||
14 | |||
15 | struct regulator *vdd; | ||
16 | |||
17 | struct { | ||
18 | /* | ||
19 | * Protects accesses to mm from subsystems | ||
20 | */ | ||
21 | struct mutex mutex; | ||
22 | |||
23 | struct nvkm_mm mm; | ||
24 | struct iommu_domain *domain; | ||
25 | unsigned long pgshift; | ||
26 | } iommu; | ||
27 | |||
28 | int gpu_speedo; | ||
9 | }; | 29 | }; |
10 | 30 | ||
11 | int nvkm_device_tegra_new(struct platform_device *, | 31 | int nvkm_device_tegra_new(struct platform_device *, |
diff --git a/drivers/gpu/drm/nouveau/nouveau_platform.c b/drivers/gpu/drm/nouveau/nouveau_platform.c index c03736bce953..3eb665453165 100644 --- a/drivers/gpu/drm/nouveau/nouveau_platform.c +++ b/drivers/gpu/drm/nouveau/nouveau_platform.c | |||
@@ -19,234 +19,32 @@ | |||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | 19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
20 | * DEALINGS IN THE SOFTWARE. | 20 | * DEALINGS IN THE SOFTWARE. |
21 | */ | 21 | */ |
22 | |||
23 | #include <linux/clk.h> | ||
24 | #include <linux/io.h> | ||
25 | #include <linux/module.h> | ||
26 | #include <linux/platform_device.h> | ||
27 | #include <linux/of.h> | ||
28 | #include <linux/reset.h> | ||
29 | #include <linux/regulator/consumer.h> | ||
30 | #include <linux/iommu.h> | ||
31 | #include <soc/tegra/fuse.h> | ||
32 | #include <soc/tegra/pmc.h> | ||
33 | |||
34 | #include "nouveau_drm.h" | ||
35 | #include "nouveau_platform.h" | 22 | #include "nouveau_platform.h" |
36 | 23 | ||
37 | static int nouveau_platform_power_up(struct nouveau_platform_gpu *gpu) | ||
38 | { | ||
39 | int err; | ||
40 | |||
41 | err = regulator_enable(gpu->vdd); | ||
42 | if (err) | ||
43 | goto err_power; | ||
44 | |||
45 | err = clk_prepare_enable(gpu->clk); | ||
46 | if (err) | ||
47 | goto err_clk; | ||
48 | err = clk_prepare_enable(gpu->clk_pwr); | ||
49 | if (err) | ||
50 | goto err_clk_pwr; | ||
51 | clk_set_rate(gpu->clk_pwr, 204000000); | ||
52 | udelay(10); | ||
53 | |||
54 | reset_control_assert(gpu->rst); | ||
55 | udelay(10); | ||
56 | |||
57 | err = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D); | ||
58 | if (err) | ||
59 | goto err_clamp; | ||
60 | udelay(10); | ||
61 | |||
62 | reset_control_deassert(gpu->rst); | ||
63 | udelay(10); | ||
64 | |||
65 | return 0; | ||
66 | |||
67 | err_clamp: | ||
68 | clk_disable_unprepare(gpu->clk_pwr); | ||
69 | err_clk_pwr: | ||
70 | clk_disable_unprepare(gpu->clk); | ||
71 | err_clk: | ||
72 | regulator_disable(gpu->vdd); | ||
73 | err_power: | ||
74 | return err; | ||
75 | } | ||
76 | |||
77 | static int nouveau_platform_power_down(struct nouveau_platform_gpu *gpu) | ||
78 | { | ||
79 | int err; | ||
80 | |||
81 | reset_control_assert(gpu->rst); | ||
82 | udelay(10); | ||
83 | |||
84 | clk_disable_unprepare(gpu->clk_pwr); | ||
85 | clk_disable_unprepare(gpu->clk); | ||
86 | udelay(10); | ||
87 | |||
88 | err = regulator_disable(gpu->vdd); | ||
89 | if (err) | ||
90 | return err; | ||
91 | |||
92 | return 0; | ||
93 | } | ||
94 | |||
95 | #if IS_ENABLED(CONFIG_IOMMU_API) | ||
96 | |||
97 | static void nouveau_platform_probe_iommu(struct device *dev, | ||
98 | struct nouveau_platform_gpu *gpu) | ||
99 | { | ||
100 | int err; | ||
101 | unsigned long pgsize_bitmap; | ||
102 | |||
103 | mutex_init(&gpu->iommu.mutex); | ||
104 | |||
105 | if (iommu_present(&platform_bus_type)) { | ||
106 | gpu->iommu.domain = iommu_domain_alloc(&platform_bus_type); | ||
107 | if (IS_ERR(gpu->iommu.domain)) | ||
108 | goto error; | ||
109 | |||
110 | /* | ||
111 | * A IOMMU is only usable if it supports page sizes smaller | ||
112 | * or equal to the system's PAGE_SIZE, with a preference if | ||
113 | * both are equal. | ||
114 | */ | ||
115 | pgsize_bitmap = gpu->iommu.domain->ops->pgsize_bitmap; | ||
116 | if (pgsize_bitmap & PAGE_SIZE) { | ||
117 | gpu->iommu.pgshift = PAGE_SHIFT; | ||
118 | } else { | ||
119 | gpu->iommu.pgshift = fls(pgsize_bitmap & ~PAGE_MASK); | ||
120 | if (gpu->iommu.pgshift == 0) { | ||
121 | dev_warn(dev, "unsupported IOMMU page size\n"); | ||
122 | goto free_domain; | ||
123 | } | ||
124 | gpu->iommu.pgshift -= 1; | ||
125 | } | ||
126 | |||
127 | err = iommu_attach_device(gpu->iommu.domain, dev); | ||
128 | if (err) | ||
129 | goto free_domain; | ||
130 | |||
131 | err = nvkm_mm_init(&gpu->iommu._mm, 0, | ||
132 | (1ULL << 40) >> gpu->iommu.pgshift, 1); | ||
133 | if (err) | ||
134 | goto detach_device; | ||
135 | |||
136 | gpu->iommu.mm = &gpu->iommu._mm; | ||
137 | } | ||
138 | |||
139 | return; | ||
140 | |||
141 | detach_device: | ||
142 | iommu_detach_device(gpu->iommu.domain, dev); | ||
143 | |||
144 | free_domain: | ||
145 | iommu_domain_free(gpu->iommu.domain); | ||
146 | |||
147 | error: | ||
148 | gpu->iommu.domain = NULL; | ||
149 | gpu->iommu.pgshift = 0; | ||
150 | dev_err(dev, "cannot initialize IOMMU MM\n"); | ||
151 | } | ||
152 | |||
153 | static void nouveau_platform_remove_iommu(struct device *dev, | ||
154 | struct nouveau_platform_gpu *gpu) | ||
155 | { | ||
156 | if (gpu->iommu.domain) { | ||
157 | nvkm_mm_fini(&gpu->iommu._mm); | ||
158 | iommu_detach_device(gpu->iommu.domain, dev); | ||
159 | iommu_domain_free(gpu->iommu.domain); | ||
160 | } | ||
161 | } | ||
162 | |||
163 | #else | ||
164 | |||
165 | static void nouveau_platform_probe_iommu(struct device *dev, | ||
166 | struct nouveau_platform_gpu *gpu) | ||
167 | { | ||
168 | } | ||
169 | |||
170 | static void nouveau_platform_remove_iommu(struct device *dev, | ||
171 | struct nouveau_platform_gpu *gpu) | ||
172 | { | ||
173 | } | ||
174 | |||
175 | #endif | ||
176 | |||
177 | static int nouveau_platform_probe(struct platform_device *pdev) | 24 | static int nouveau_platform_probe(struct platform_device *pdev) |
178 | { | 25 | { |
179 | struct nouveau_platform_gpu *gpu; | ||
180 | struct nvkm_device *device; | 26 | struct nvkm_device *device; |
181 | struct drm_device *drm; | 27 | struct drm_device *drm; |
182 | int err; | 28 | int ret; |
183 | |||
184 | gpu = devm_kzalloc(&pdev->dev, sizeof(*gpu), GFP_KERNEL); | ||
185 | if (!gpu) | ||
186 | return -ENOMEM; | ||
187 | |||
188 | gpu->vdd = devm_regulator_get(&pdev->dev, "vdd"); | ||
189 | if (IS_ERR(gpu->vdd)) | ||
190 | return PTR_ERR(gpu->vdd); | ||
191 | |||
192 | gpu->rst = devm_reset_control_get(&pdev->dev, "gpu"); | ||
193 | if (IS_ERR(gpu->rst)) | ||
194 | return PTR_ERR(gpu->rst); | ||
195 | |||
196 | gpu->clk = devm_clk_get(&pdev->dev, "gpu"); | ||
197 | if (IS_ERR(gpu->clk)) | ||
198 | return PTR_ERR(gpu->clk); | ||
199 | |||
200 | gpu->clk_pwr = devm_clk_get(&pdev->dev, "pwr"); | ||
201 | if (IS_ERR(gpu->clk_pwr)) | ||
202 | return PTR_ERR(gpu->clk_pwr); | ||
203 | |||
204 | nouveau_platform_probe_iommu(&pdev->dev, gpu); | ||
205 | |||
206 | err = nouveau_platform_power_up(gpu); | ||
207 | if (err) | ||
208 | return err; | ||
209 | 29 | ||
210 | drm = nouveau_platform_device_create(pdev, &device); | 30 | drm = nouveau_platform_device_create(pdev, &device); |
211 | if (IS_ERR(drm)) { | 31 | if (IS_ERR(drm)) |
212 | err = PTR_ERR(drm); | 32 | return PTR_ERR(drm); |
213 | goto power_down; | ||
214 | } | ||
215 | 33 | ||
216 | device->gpu = gpu; | 34 | ret = drm_dev_register(drm, 0); |
217 | gpu->gpu_speedo = tegra_sku_info.gpu_speedo_value; | 35 | if (ret < 0) { |
218 | 36 | drm_dev_unref(drm); | |
219 | err = drm_dev_register(drm, 0); | 37 | return ret; |
220 | if (err < 0) | 38 | } |
221 | goto err_unref; | ||
222 | 39 | ||
223 | return 0; | 40 | return 0; |
224 | |||
225 | err_unref: | ||
226 | drm_dev_unref(drm); | ||
227 | |||
228 | power_down: | ||
229 | nouveau_platform_power_down(gpu); | ||
230 | nouveau_platform_remove_iommu(&pdev->dev, gpu); | ||
231 | |||
232 | return err; | ||
233 | } | 41 | } |
234 | 42 | ||
235 | static int nouveau_platform_remove(struct platform_device *pdev) | 43 | static int nouveau_platform_remove(struct platform_device *pdev) |
236 | { | 44 | { |
237 | struct drm_device *drm_dev = platform_get_drvdata(pdev); | 45 | struct drm_device *dev = platform_get_drvdata(pdev); |
238 | struct nouveau_drm *drm = nouveau_drm(drm_dev); | 46 | nouveau_drm_device_remove(dev); |
239 | struct nvkm_device *device = nvxx_device(&drm->device); | 47 | return 0; |
240 | struct nouveau_platform_gpu *gpu = device->gpu; | ||
241 | int err; | ||
242 | |||
243 | nouveau_drm_device_remove(drm_dev); | ||
244 | |||
245 | err = nouveau_platform_power_down(gpu); | ||
246 | |||
247 | nouveau_platform_remove_iommu(&pdev->dev, gpu); | ||
248 | |||
249 | return err; | ||
250 | } | 48 | } |
251 | 49 | ||
252 | #if IS_ENABLED(CONFIG_OF) | 50 | #if IS_ENABLED(CONFIG_OF) |
diff --git a/drivers/gpu/drm/nouveau/nouveau_platform.h b/drivers/gpu/drm/nouveau/nouveau_platform.h index 7a4020f31cc5..f41056d0f5f4 100644 --- a/drivers/gpu/drm/nouveau/nouveau_platform.h +++ b/drivers/gpu/drm/nouveau/nouveau_platform.h | |||
@@ -19,44 +19,9 @@ | |||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | 19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
20 | * DEALINGS IN THE SOFTWARE. | 20 | * DEALINGS IN THE SOFTWARE. |
21 | */ | 21 | */ |
22 | |||
23 | #ifndef __NOUVEAU_PLATFORM_H__ | 22 | #ifndef __NOUVEAU_PLATFORM_H__ |
24 | #define __NOUVEAU_PLATFORM_H__ | 23 | #define __NOUVEAU_PLATFORM_H__ |
25 | 24 | #include "nouveau_drm.h" | |
26 | #include "core/device.h" | ||
27 | #include "core/mm.h" | ||
28 | |||
29 | struct reset_control; | ||
30 | struct clk; | ||
31 | struct regulator; | ||
32 | struct iommu_domain; | ||
33 | struct platform_driver; | ||
34 | |||
35 | struct nouveau_platform_gpu { | ||
36 | struct reset_control *rst; | ||
37 | struct clk *clk; | ||
38 | struct clk *clk_pwr; | ||
39 | |||
40 | struct regulator *vdd; | ||
41 | |||
42 | struct { | ||
43 | /* | ||
44 | * Protects accesses to mm from subsystems | ||
45 | */ | ||
46 | struct mutex mutex; | ||
47 | |||
48 | struct nvkm_mm _mm; | ||
49 | /* | ||
50 | * Just points to _mm. We need this to avoid embedding | ||
51 | * struct nvkm_mm in os.h | ||
52 | */ | ||
53 | struct nvkm_mm *mm; | ||
54 | struct iommu_domain *domain; | ||
55 | unsigned long pgshift; | ||
56 | } iommu; | ||
57 | |||
58 | int gpu_speedo; | ||
59 | }; | ||
60 | 25 | ||
61 | extern struct platform_driver nouveau_platform_driver; | 26 | extern struct platform_driver nouveau_platform_driver; |
62 | #endif | 27 | #endif |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c index ada73e13d1af..da57c8a60608 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright 2015 Red Hat Inc. | 2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -14,17 +14,138 @@ | |||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | 17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | 18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | 19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
20 | * OTHER DEALINGS IN THE SOFTWARE. | 20 | * DEALINGS IN THE SOFTWARE. |
21 | * | ||
22 | * Authors: Ben Skeggs <bskeggs@redhat.com> | ||
23 | */ | 21 | */ |
24 | #include <core/tegra.h> | 22 | #include <core/tegra.h> |
25 | #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER | 23 | #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER |
26 | #include "priv.h" | 24 | #include "priv.h" |
27 | 25 | ||
26 | static int | ||
27 | nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev) | ||
28 | { | ||
29 | int ret; | ||
30 | |||
31 | ret = regulator_enable(tdev->vdd); | ||
32 | if (ret) | ||
33 | goto err_power; | ||
34 | |||
35 | ret = clk_prepare_enable(tdev->clk); | ||
36 | if (ret) | ||
37 | goto err_clk; | ||
38 | ret = clk_prepare_enable(tdev->clk_pwr); | ||
39 | if (ret) | ||
40 | goto err_clk_pwr; | ||
41 | clk_set_rate(tdev->clk_pwr, 204000000); | ||
42 | udelay(10); | ||
43 | |||
44 | reset_control_assert(tdev->rst); | ||
45 | udelay(10); | ||
46 | |||
47 | ret = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D); | ||
48 | if (ret) | ||
49 | goto err_clamp; | ||
50 | udelay(10); | ||
51 | |||
52 | reset_control_deassert(tdev->rst); | ||
53 | udelay(10); | ||
54 | |||
55 | return 0; | ||
56 | |||
57 | err_clamp: | ||
58 | clk_disable_unprepare(tdev->clk_pwr); | ||
59 | err_clk_pwr: | ||
60 | clk_disable_unprepare(tdev->clk); | ||
61 | err_clk: | ||
62 | regulator_disable(tdev->vdd); | ||
63 | err_power: | ||
64 | return ret; | ||
65 | } | ||
66 | |||
67 | static int | ||
68 | nvkm_device_tegra_power_down(struct nvkm_device_tegra *tdev) | ||
69 | { | ||
70 | reset_control_assert(tdev->rst); | ||
71 | udelay(10); | ||
72 | |||
73 | clk_disable_unprepare(tdev->clk_pwr); | ||
74 | clk_disable_unprepare(tdev->clk); | ||
75 | udelay(10); | ||
76 | |||
77 | return regulator_disable(tdev->vdd); | ||
78 | } | ||
79 | |||
80 | static void | ||
81 | nvkm_device_tegra_probe_iommu(struct nvkm_device_tegra *tdev) | ||
82 | { | ||
83 | #if IS_ENABLED(CONFIG_IOMMU_API) | ||
84 | struct device *dev = &tdev->pdev->dev; | ||
85 | unsigned long pgsize_bitmap; | ||
86 | int ret; | ||
87 | |||
88 | mutex_init(&tdev->iommu.mutex); | ||
89 | |||
90 | if (iommu_present(&platform_bus_type)) { | ||
91 | tdev->iommu.domain = iommu_domain_alloc(&platform_bus_type); | ||
92 | if (IS_ERR(tdev->iommu.domain)) | ||
93 | goto error; | ||
94 | |||
95 | /* | ||
96 | * A IOMMU is only usable if it supports page sizes smaller | ||
97 | * or equal to the system's PAGE_SIZE, with a preference if | ||
98 | * both are equal. | ||
99 | */ | ||
100 | pgsize_bitmap = tdev->iommu.domain->ops->pgsize_bitmap; | ||
101 | if (pgsize_bitmap & PAGE_SIZE) { | ||
102 | tdev->iommu.pgshift = PAGE_SHIFT; | ||
103 | } else { | ||
104 | tdev->iommu.pgshift = fls(pgsize_bitmap & ~PAGE_MASK); | ||
105 | if (tdev->iommu.pgshift == 0) { | ||
106 | dev_warn(dev, "unsupported IOMMU page size\n"); | ||
107 | goto free_domain; | ||
108 | } | ||
109 | tdev->iommu.pgshift -= 1; | ||
110 | } | ||
111 | |||
112 | ret = iommu_attach_device(tdev->iommu.domain, dev); | ||
113 | if (ret) | ||
114 | goto free_domain; | ||
115 | |||
116 | ret = nvkm_mm_init(&tdev->iommu.mm, 0, | ||
117 | (1ULL << 40) >> tdev->iommu.pgshift, 1); | ||
118 | if (ret) | ||
119 | goto detach_device; | ||
120 | } | ||
121 | |||
122 | return; | ||
123 | |||
124 | detach_device: | ||
125 | iommu_detach_device(tdev->iommu.domain, dev); | ||
126 | |||
127 | free_domain: | ||
128 | iommu_domain_free(tdev->iommu.domain); | ||
129 | |||
130 | error: | ||
131 | tdev->iommu.domain = NULL; | ||
132 | tdev->iommu.pgshift = 0; | ||
133 | dev_err(dev, "cannot initialize IOMMU MM\n"); | ||
134 | #endif | ||
135 | } | ||
136 | |||
137 | static void | ||
138 | nvkm_device_tegra_remove_iommu(struct nvkm_device_tegra *tdev) | ||
139 | { | ||
140 | #if IS_ENABLED(CONFIG_IOMMU_API) | ||
141 | if (tdev->iommu.domain) { | ||
142 | nvkm_mm_fini(&tdev->iommu.mm); | ||
143 | iommu_detach_device(tdev->iommu.domain, tdev->device.dev); | ||
144 | iommu_domain_free(tdev->iommu.domain); | ||
145 | } | ||
146 | #endif | ||
147 | } | ||
148 | |||
28 | static struct nvkm_device_tegra * | 149 | static struct nvkm_device_tegra * |
29 | nvkm_device_tegra(struct nvkm_device *device) | 150 | nvkm_device_tegra(struct nvkm_device *device) |
30 | { | 151 | { |
@@ -95,9 +216,19 @@ nvkm_device_tegra_init(struct nvkm_device *device) | |||
95 | return 0; | 216 | return 0; |
96 | } | 217 | } |
97 | 218 | ||
219 | static void * | ||
220 | nvkm_device_tegra_dtor(struct nvkm_device *device) | ||
221 | { | ||
222 | struct nvkm_device_tegra *tdev = nvkm_device_tegra(device); | ||
223 | nvkm_device_tegra_power_down(tdev); | ||
224 | nvkm_device_tegra_remove_iommu(tdev); | ||
225 | return tdev; | ||
226 | } | ||
227 | |||
98 | static const struct nvkm_device_func | 228 | static const struct nvkm_device_func |
99 | nvkm_device_tegra_func = { | 229 | nvkm_device_tegra_func = { |
100 | .tegra = nvkm_device_tegra, | 230 | .tegra = nvkm_device_tegra, |
231 | .dtor = nvkm_device_tegra_dtor, | ||
101 | .init = nvkm_device_tegra_init, | 232 | .init = nvkm_device_tegra_init, |
102 | .fini = nvkm_device_tegra_fini, | 233 | .fini = nvkm_device_tegra_fini, |
103 | .resource_addr = nvkm_device_tegra_resource_addr, | 234 | .resource_addr = nvkm_device_tegra_resource_addr, |
@@ -112,6 +243,7 @@ nvkm_device_tegra_new(struct platform_device *pdev, | |||
112 | struct nvkm_device **pdevice) | 243 | struct nvkm_device **pdevice) |
113 | { | 244 | { |
114 | struct nvkm_device_tegra *tdev; | 245 | struct nvkm_device_tegra *tdev; |
246 | int ret; | ||
115 | 247 | ||
116 | if (!(tdev = kzalloc(sizeof(*tdev), GFP_KERNEL))) | 248 | if (!(tdev = kzalloc(sizeof(*tdev), GFP_KERNEL))) |
117 | return -ENOMEM; | 249 | return -ENOMEM; |
@@ -119,10 +251,37 @@ nvkm_device_tegra_new(struct platform_device *pdev, | |||
119 | tdev->pdev = pdev; | 251 | tdev->pdev = pdev; |
120 | tdev->irq = -1; | 252 | tdev->irq = -1; |
121 | 253 | ||
122 | return nvkm_device_ctor(&nvkm_device_tegra_func, NULL, &pdev->dev, | 254 | tdev->vdd = devm_regulator_get(&pdev->dev, "vdd"); |
123 | NVKM_DEVICE_TEGRA, pdev->id, NULL, | 255 | if (IS_ERR(tdev->vdd)) |
124 | cfg, dbg, detect, mmio, subdev_mask, | 256 | return PTR_ERR(tdev->vdd); |
125 | &tdev->device); | 257 | |
258 | tdev->rst = devm_reset_control_get(&pdev->dev, "gpu"); | ||
259 | if (IS_ERR(tdev->rst)) | ||
260 | return PTR_ERR(tdev->rst); | ||
261 | |||
262 | tdev->clk = devm_clk_get(&pdev->dev, "gpu"); | ||
263 | if (IS_ERR(tdev->clk)) | ||
264 | return PTR_ERR(tdev->clk); | ||
265 | |||
266 | tdev->clk_pwr = devm_clk_get(&pdev->dev, "pwr"); | ||
267 | if (IS_ERR(tdev->clk_pwr)) | ||
268 | return PTR_ERR(tdev->clk_pwr); | ||
269 | |||
270 | nvkm_device_tegra_probe_iommu(tdev); | ||
271 | |||
272 | ret = nvkm_device_tegra_power_up(tdev); | ||
273 | if (ret) | ||
274 | return ret; | ||
275 | |||
276 | tdev->gpu_speedo = tegra_sku_info.gpu_speedo_value; | ||
277 | ret = nvkm_device_ctor(&nvkm_device_tegra_func, NULL, &pdev->dev, | ||
278 | NVKM_DEVICE_TEGRA, pdev->id, NULL, | ||
279 | cfg, dbg, detect, mmio, subdev_mask, | ||
280 | &tdev->device); | ||
281 | if (ret) | ||
282 | return ret; | ||
283 | |||
284 | return 0; | ||
126 | } | 285 | } |
127 | #else | 286 | #else |
128 | int | 287 | int |
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c index 6a74ce3730d0..254094ab7fb8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c | |||
@@ -25,12 +25,9 @@ | |||
25 | #define gk20a_clk(p) container_of((p), struct gk20a_clk, base) | 25 | #define gk20a_clk(p) container_of((p), struct gk20a_clk, base) |
26 | #include "priv.h" | 26 | #include "priv.h" |
27 | 27 | ||
28 | #include <core/tegra.h> | ||
28 | #include <subdev/timer.h> | 29 | #include <subdev/timer.h> |
29 | 30 | ||
30 | #ifdef __KERNEL__ | ||
31 | #include <nouveau_platform.h> | ||
32 | #endif | ||
33 | |||
34 | #define MHZ (1000 * 1000) | 31 | #define MHZ (1000 * 1000) |
35 | 32 | ||
36 | #define MASK(w) ((1 << w) - 1) | 33 | #define MASK(w) ((1 << w) - 1) |
@@ -649,6 +646,7 @@ gk20a_clk = { | |||
649 | int | 646 | int |
650 | gk20a_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) | 647 | gk20a_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) |
651 | { | 648 | { |
649 | struct nvkm_device_tegra *tdev = device->func->tegra(device); | ||
652 | struct gk20a_clk *clk; | 650 | struct gk20a_clk *clk; |
653 | int ret, i; | 651 | int ret, i; |
654 | 652 | ||
@@ -663,7 +661,7 @@ gk20a_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) | |||
663 | } | 661 | } |
664 | 662 | ||
665 | clk->params = &gk20a_pllg_params; | 663 | clk->params = &gk20a_pllg_params; |
666 | clk->parent_rate = clk_get_rate(device->gpu->clk); | 664 | clk->parent_rate = clk_get_rate(tdev->clk); |
667 | 665 | ||
668 | ret = nvkm_clk_ctor(&gk20a_clk, device, index, true, &clk->base); | 666 | ret = nvkm_clk_ctor(&gk20a_clk, device, index, true, &clk->base); |
669 | nvkm_info(&clk->base.subdev, "parent clock rate: %d Mhz\n", | 667 | nvkm_info(&clk->base.subdev, "parent clock rate: %d Mhz\n", |
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c index 5ef04b72a80a..cd7feb1b25f6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c | |||
@@ -42,14 +42,9 @@ | |||
42 | 42 | ||
43 | #include <core/memory.h> | 43 | #include <core/memory.h> |
44 | #include <core/mm.h> | 44 | #include <core/mm.h> |
45 | #include <core/tegra.h> | ||
45 | #include <subdev/fb.h> | 46 | #include <subdev/fb.h> |
46 | 47 | ||
47 | #ifdef __KERNEL__ | ||
48 | #include <linux/dma-attrs.h> | ||
49 | #include <linux/iommu.h> | ||
50 | #include <nouveau_platform.h> | ||
51 | #endif | ||
52 | |||
53 | #define gk20a_instobj(p) container_of((p), struct gk20a_instobj, memory) | 48 | #define gk20a_instobj(p) container_of((p), struct gk20a_instobj, memory) |
54 | 49 | ||
55 | struct gk20a_instobj { | 50 | struct gk20a_instobj { |
@@ -423,8 +418,9 @@ gk20a_instmem = { | |||
423 | 418 | ||
424 | int | 419 | int |
425 | gk20a_instmem_new(struct nvkm_device *device, int index, | 420 | gk20a_instmem_new(struct nvkm_device *device, int index, |
426 | struct nvkm_instmem **pimem) | 421 | struct nvkm_instmem **pimem) |
427 | { | 422 | { |
423 | struct nvkm_device_tegra *tdev = device->func->tegra(device); | ||
428 | struct gk20a_instmem *imem; | 424 | struct gk20a_instmem *imem; |
429 | 425 | ||
430 | if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL))) | 426 | if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL))) |
@@ -433,11 +429,11 @@ gk20a_instmem_new(struct nvkm_device *device, int index, | |||
433 | spin_lock_init(&imem->lock); | 429 | spin_lock_init(&imem->lock); |
434 | *pimem = &imem->base; | 430 | *pimem = &imem->base; |
435 | 431 | ||
436 | if (device->gpu->iommu.domain) { | 432 | if (tdev->iommu.domain) { |
437 | imem->domain = device->gpu->iommu.domain; | 433 | imem->domain = tdev->iommu.domain; |
438 | imem->mm = device->gpu->iommu.mm; | 434 | imem->mm = &tdev->iommu.mm; |
439 | imem->iommu_pgshift = device->gpu->iommu.pgshift; | 435 | imem->iommu_pgshift = tdev->iommu.pgshift; |
440 | imem->mm_mutex = &device->gpu->iommu.mutex; | 436 | imem->mm_mutex = &tdev->iommu.mutex; |
441 | 437 | ||
442 | nvkm_info(&imem->base.subdev, "using IOMMU\n"); | 438 | nvkm_info(&imem->base.subdev, "using IOMMU\n"); |
443 | } else { | 439 | } else { |
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c index 01394a05e9d8..fd56c6476064 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c | |||
@@ -22,9 +22,7 @@ | |||
22 | #define gk20a_volt(p) container_of((p), struct gk20a_volt, base) | 22 | #define gk20a_volt(p) container_of((p), struct gk20a_volt, base) |
23 | #include "priv.h" | 23 | #include "priv.h" |
24 | 24 | ||
25 | #ifdef __KERNEL__ | 25 | #include <core/tegra.h> |
26 | #include <nouveau_platform.h> | ||
27 | #endif | ||
28 | 26 | ||
29 | struct cvb_coef { | 27 | struct cvb_coef { |
30 | int c0; | 28 | int c0; |
@@ -159,6 +157,7 @@ gk20a_volt = { | |||
159 | int | 157 | int |
160 | gk20a_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) | 158 | gk20a_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) |
161 | { | 159 | { |
160 | struct nvkm_device_tegra *tdev = device->func->tegra(device); | ||
162 | struct gk20a_volt *volt; | 161 | struct gk20a_volt *volt; |
163 | int i, uv; | 162 | int i, uv; |
164 | 163 | ||
@@ -168,10 +167,10 @@ gk20a_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) | |||
168 | nvkm_volt_ctor(&gk20a_volt, device, index, &volt->base); | 167 | nvkm_volt_ctor(&gk20a_volt, device, index, &volt->base); |
169 | *pvolt = &volt->base; | 168 | *pvolt = &volt->base; |
170 | 169 | ||
171 | uv = regulator_get_voltage(device->gpu->vdd); | 170 | uv = regulator_get_voltage(tdev->vdd); |
172 | nvkm_info(&volt->base.subdev, "The default voltage is %duV\n", uv); | 171 | nvkm_info(&volt->base.subdev, "The default voltage is %duV\n", uv); |
173 | 172 | ||
174 | volt->vdd = device->gpu->vdd; | 173 | volt->vdd = tdev->vdd; |
175 | 174 | ||
176 | volt->base.vid_nr = ARRAY_SIZE(gk20a_cvb_coef); | 175 | volt->base.vid_nr = ARRAY_SIZE(gk20a_cvb_coef); |
177 | nvkm_debug(&volt->base.subdev, "%s - vid_nr = %d\n", __func__, | 176 | nvkm_debug(&volt->base.subdev, "%s - vid_nr = %d\n", __func__, |
@@ -180,7 +179,7 @@ gk20a_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) | |||
180 | volt->base.vid[i].vid = i; | 179 | volt->base.vid[i].vid = i; |
181 | volt->base.vid[i].uv = | 180 | volt->base.vid[i].uv = |
182 | gk20a_volt_calc_voltage(&gk20a_cvb_coef[i], | 181 | gk20a_volt_calc_voltage(&gk20a_cvb_coef[i], |
183 | device->gpu->gpu_speedo); | 182 | tdev->gpu_speedo); |
184 | nvkm_debug(&volt->base.subdev, "%2d: vid=%d, uv=%d\n", i, | 183 | nvkm_debug(&volt->base.subdev, "%2d: vid=%d, uv=%d\n", i, |
185 | volt->base.vid[i].vid, volt->base.vid[i].uv); | 184 | volt->base.vid[i].vid, volt->base.vid[i].uv); |
186 | } | 185 | } |