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authorLinus Torvalds <torvalds@linux-foundation.org>2018-08-22 17:04:41 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2018-08-22 17:04:41 -0400
commit433bcf67370bc170a345634aa1be4ee8ac905de9 (patch)
treef2a7afc2ccc3346515e8e12208f3b2bff4e84f33
parentb372115311942202346d93849991f07382783ef1 (diff)
parent35d231db53a60b76e218a56da30ad071d4717b56 (diff)
Merge tag 'xtensa-20180820' of git://github.com/jcmvbkbc/linux-xtensa
Pull Xtensa updates from Max Filippov: - switch xtensa arch to the generic noncoherent direct mapping operations - add support for DMA_ATTR_NO_KERNEL_MAPPING attribute - clean up users of platform/hardware.h in generic Xtensa code - fix assembly cache maintenance code for long cache lines - rework noMMU cache attributes initialization - add big-endian HiFi2 test_kc705_be CPU variant * tag 'xtensa-20180820' of git://github.com/jcmvbkbc/linux-xtensa: xtensa: add test_kc705_be variant xtensa: clean up boot-elf/bootstrap.S xtensa: make bootparam parsing optional xtensa: drop variant IRQ support xtensa: drop unneeded platform/hardware.h headers xtensa: move PLATFORM_NR_IRQS to Kconfig xtensa: rework {CONFIG,PLATFORM}_DEFAULT_MEM_START xtensa: drop unused {CONFIG,PLATFORM}_DEFAULT_MEM_SIZE xtensa: rework noMMU cache attributes initialization xtensa: increase ranges in ___invalidate_{i,d}cache_all xtensa: limit offsets in __loop_cache_{all,page} xtensa: platform-specific handling of coherent memory xtensa: support DMA_ATTR_NO_KERNEL_MAPPING attribute xtensa: use generic dma_noncoherent_ops
Diffstat
-rw-r--r--arch/xtensa/Kconfig60
-rw-r--r--arch/xtensa/boot/boot-elf/bootstrap.S19
-rw-r--r--arch/xtensa/configs/nommu_kc705_defconfig2
-rw-r--r--arch/xtensa/include/asm/Kbuild1
-rw-r--r--arch/xtensa/include/asm/cacheasm.h69
-rw-r--r--arch/xtensa/include/asm/dma-mapping.h26
-rw-r--r--arch/xtensa/include/asm/initialize_mmu.h42
-rw-r--r--arch/xtensa/include/asm/irq.h21
-rw-r--r--arch/xtensa/include/asm/kmem_layout.h6
-rw-r--r--arch/xtensa/include/asm/page.h5
-rw-r--r--arch/xtensa/include/asm/pgtable.h8
-rw-r--r--arch/xtensa/include/asm/platform.h27
-rw-r--r--arch/xtensa/include/asm/processor.h1
-rw-r--r--arch/xtensa/include/asm/vectors.h1
-rw-r--r--arch/xtensa/kernel/head.S2
-rw-r--r--arch/xtensa/kernel/irq.c1
-rw-r--r--arch/xtensa/kernel/pci-dma.c193
-rw-r--r--arch/xtensa/kernel/setup.c10
-rw-r--r--arch/xtensa/kernel/vmlinux.lds.S2
-rw-r--r--arch/xtensa/platforms/iss/include/platform/hardware.h29
-rw-r--r--arch/xtensa/platforms/xt2000/include/platform/hardware.h11
-rw-r--r--arch/xtensa/platforms/xtfpga/include/platform/hardware.h9
-rw-r--r--arch/xtensa/variants/test_kc705_be/include/variant/core.h575
-rw-r--r--arch/xtensa/variants/test_kc705_be/include/variant/tie-asm.h308
-rw-r--r--arch/xtensa/variants/test_kc705_be/include/variant/tie.h182
-rw-r--r--drivers/irqchip/irq-xtensa-mx.c2
-rw-r--r--drivers/irqchip/irq-xtensa-pic.c2
27 files changed, 1300 insertions, 314 deletions
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 801491e98890..04d038f3b6fa 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -4,12 +4,15 @@ config ZONE_DMA
4 4
5config XTENSA 5config XTENSA
6 def_bool y 6 def_bool y
7 select ARCH_HAS_SYNC_DMA_FOR_CPU
8 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
7 select ARCH_NO_COHERENT_DMA_MMAP if !MMU 9 select ARCH_NO_COHERENT_DMA_MMAP if !MMU
8 select ARCH_WANT_FRAME_POINTERS 10 select ARCH_WANT_FRAME_POINTERS
9 select ARCH_WANT_IPC_PARSE_VERSION 11 select ARCH_WANT_IPC_PARSE_VERSION
10 select BUILDTIME_EXTABLE_SORT 12 select BUILDTIME_EXTABLE_SORT
11 select CLONE_BACKWARDS 13 select CLONE_BACKWARDS
12 select COMMON_CLK 14 select COMMON_CLK
15 select DMA_NONCOHERENT_OPS
13 select GENERIC_ATOMIC64 16 select GENERIC_ATOMIC64
14 select GENERIC_CLOCKEVENTS 17 select GENERIC_CLOCKEVENTS
15 select GENERIC_IRQ_SHOW 18 select GENERIC_IRQ_SHOW
@@ -72,9 +75,6 @@ config TRACE_IRQFLAGS_SUPPORT
72config MMU 75config MMU
73 def_bool n 76 def_bool n
74 77
75config VARIANT_IRQ_SWITCH
76 def_bool n
77
78config HAVE_XTENSA_GPIO32 78config HAVE_XTENSA_GPIO32
79 def_bool n 79 def_bool n
80 80
@@ -244,6 +244,23 @@ config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
244 244
245 If in doubt, say Y. 245 If in doubt, say Y.
246 246
247config MEMMAP_CACHEATTR
248 hex "Cache attributes for the memory address space"
249 depends on !MMU
250 default 0x22222222
251 help
252 These cache attributes are set up for noMMU systems. Each hex digit
253 specifies cache attributes for the corresponding 512MB memory
254 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,
255 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.
256
257 Cache attribute values are specific for the MMU type, so e.g.
258 for region protection MMUs: 2 is cache bypass, 4 is WB cached,
259 1 is WT cached, f is illegal. For ful MMU: bit 0 makes it executable,
260 bit 1 makes it writable, bits 2..3 meaning is 0: cache bypass,
261 1: WB cache, 2: WT cache, 3: special (c and e are illegal, f is
262 reserved).
263
247config KSEG_PADDR 264config KSEG_PADDR
248 hex "Physical address of the KSEG mapping" 265 hex "Physical address of the KSEG mapping"
249 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU 266 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU
@@ -413,6 +430,10 @@ config XTENSA_PLATFORM_XTFPGA
413 430
414endchoice 431endchoice
415 432
433config PLATFORM_NR_IRQS
434 int
435 default 3 if XTENSA_PLATFORM_XT2000
436 default 0
416 437
417config XTENSA_CPU_CLOCK 438config XTENSA_CPU_CLOCK
418 int "CPU clock rate [MHz]" 439 int "CPU clock rate [MHz]"
@@ -450,6 +471,15 @@ config BUILTIN_DTB
450 string "DTB to build into the kernel image" 471 string "DTB to build into the kernel image"
451 depends on OF 472 depends on OF
452 473
474config PARSE_BOOTPARAM
475 bool "Parse bootparam block"
476 default y
477 help
478 Parse parameters passed to the kernel from the bootloader. It may
479 be disabled if the kernel is known to run without the bootloader.
480
481 If unsure, say Y.
482
453config BLK_DEV_SIMDISK 483config BLK_DEV_SIMDISK
454 tristate "Host file-based simulated block device support" 484 tristate "Host file-based simulated block device support"
455 default n 485 default n
@@ -506,25 +536,13 @@ config PLATFORM_WANT_DEFAULT_MEM
506 def_bool n 536 def_bool n
507 537
508config DEFAULT_MEM_START 538config DEFAULT_MEM_START
509 hex "Physical address of the default memory area start" 539 hex
510 depends on PLATFORM_WANT_DEFAULT_MEM 540 prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM
511 default 0x00000000 if MMU 541 default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM
512 default 0x60000000 if !MMU 542 default 0x00000000
513 help
514 This is the base address of the default memory area.
515 Default memory area has platform-specific meaning, it may be used
516 for e.g. early cache initialization.
517
518 If unsure, leave the default value here.
519
520config DEFAULT_MEM_SIZE
521 hex "Maximal size of the default memory area"
522 depends on PLATFORM_WANT_DEFAULT_MEM
523 default 0x04000000
524 help 543 help
525 This is the size of the default memory area. 544 This is the base address used for both PAGE_OFFSET and PHYS_OFFSET
526 Default memory area has platform-specific meaning, it may be used 545 in noMMU configurations.
527 for e.g. early cache initialization.
528 546
529 If unsure, leave the default value here. 547 If unsure, leave the default value here.
530 548
diff --git a/arch/xtensa/boot/boot-elf/bootstrap.S b/arch/xtensa/boot/boot-elf/bootstrap.S
index b6aa85328ac0..29c68426ab56 100644
--- a/arch/xtensa/boot/boot-elf/bootstrap.S
+++ b/arch/xtensa/boot/boot-elf/bootstrap.S
@@ -15,10 +15,6 @@
15 */ 15 */
16 16
17#include <asm/bootparam.h> 17#include <asm/bootparam.h>
18#include <asm/processor.h>
19#include <asm/pgtable.h>
20#include <asm/page.h>
21#include <asm/cacheasm.h>
22#include <asm/initialize_mmu.h> 18#include <asm/initialize_mmu.h>
23#include <asm/vectors.h> 19#include <asm/vectors.h>
24#include <linux/linkage.h> 20#include <linux/linkage.h>
@@ -33,16 +29,18 @@ _ResetVector:
33 .begin no-absolute-literals 29 .begin no-absolute-literals
34 .literal_position 30 .literal_position
35 31
36 .align 4
37RomInitAddr:
38#if defined(CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) && \ 32#if defined(CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) && \
39 XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY 33 XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
40 .word CONFIG_KERNEL_LOAD_ADDRESS 34 .literal RomInitAddr, CONFIG_KERNEL_LOAD_ADDRESS
41#else 35#else
42 .word KERNELOFFSET 36 .literal RomInitAddr, KERNELOFFSET
43#endif 37#endif
44RomBootParam: 38#ifndef CONFIG_PARSE_BOOTPARAM
45 .word _bootparam 39 .literal RomBootParam, 0
40#else
41 .literal RomBootParam, _bootparam
42
43 .align 4
46_bootparam: 44_bootparam:
47 .short BP_TAG_FIRST 45 .short BP_TAG_FIRST
48 .short 4 46 .short 4
@@ -50,6 +48,7 @@ _bootparam:
50 .short BP_TAG_LAST 48 .short BP_TAG_LAST
51 .short 0 49 .short 0
52 .long 0 50 .long 0
51#endif
53 52
54 .align 4 53 .align 4
55_SetupMMU: 54_SetupMMU:
diff --git a/arch/xtensa/configs/nommu_kc705_defconfig b/arch/xtensa/configs/nommu_kc705_defconfig
index 624f9b3a3878..f3fc4f970ca8 100644
--- a/arch/xtensa/configs/nommu_kc705_defconfig
+++ b/arch/xtensa/configs/nommu_kc705_defconfig
@@ -33,13 +33,13 @@ CONFIG_XTENSA_VARIANT_CUSTOM_NAME="de212"
33# CONFIG_XTENSA_VARIANT_MMU is not set 33# CONFIG_XTENSA_VARIANT_MMU is not set
34CONFIG_XTENSA_UNALIGNED_USER=y 34CONFIG_XTENSA_UNALIGNED_USER=y
35CONFIG_PREEMPT=y 35CONFIG_PREEMPT=y
36CONFIG_MEMMAP_CACHEATTR=0xfff2442f
36# CONFIG_PCI is not set 37# CONFIG_PCI is not set
37CONFIG_XTENSA_PLATFORM_XTFPGA=y 38CONFIG_XTENSA_PLATFORM_XTFPGA=y
38CONFIG_CMDLINE_BOOL=y 39CONFIG_CMDLINE_BOOL=y
39CONFIG_CMDLINE="earlycon=uart8250,mmio32native,0x9d050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug memmap=256M@0x60000000" 40CONFIG_CMDLINE="earlycon=uart8250,mmio32native,0x9d050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug memmap=256M@0x60000000"
40CONFIG_USE_OF=y 41CONFIG_USE_OF=y
41CONFIG_BUILTIN_DTB="kc705_nommu" 42CONFIG_BUILTIN_DTB="kc705_nommu"
42CONFIG_DEFAULT_MEM_SIZE=0x10000000
43CONFIG_BINFMT_FLAT=y 43CONFIG_BINFMT_FLAT=y
44CONFIG_NET=y 44CONFIG_NET=y
45CONFIG_PACKET=y 45CONFIG_PACKET=y
diff --git a/arch/xtensa/include/asm/Kbuild b/arch/xtensa/include/asm/Kbuild
index e5e1e61c538c..82c756431b49 100644
--- a/arch/xtensa/include/asm/Kbuild
+++ b/arch/xtensa/include/asm/Kbuild
@@ -3,6 +3,7 @@ generic-y += compat.h
3generic-y += device.h 3generic-y += device.h
4generic-y += div64.h 4generic-y += div64.h
5generic-y += dma-contiguous.h 5generic-y += dma-contiguous.h
6generic-y += dma-mapping.h
6generic-y += emergency-restart.h 7generic-y += emergency-restart.h
7generic-y += exec.h 8generic-y += exec.h
8generic-y += extable.h 9generic-y += extable.h
diff --git a/arch/xtensa/include/asm/cacheasm.h b/arch/xtensa/include/asm/cacheasm.h
index 2041abb10a23..34545ecfdd6b 100644
--- a/arch/xtensa/include/asm/cacheasm.h
+++ b/arch/xtensa/include/asm/cacheasm.h
@@ -31,16 +31,32 @@
31 * 31 *
32 */ 32 */
33 33
34 .macro __loop_cache_all ar at insn size line_width
35 34
36 movi \ar, 0 35 .macro __loop_cache_unroll ar at insn size line_width max_immed
36
37 .if (1 << (\line_width)) > (\max_immed)
38 .set _reps, 1
39 .elseif (2 << (\line_width)) > (\max_immed)
40 .set _reps, 2
41 .else
42 .set _reps, 4
43 .endif
44
45 __loopi \ar, \at, \size, (_reps << (\line_width))
46 .set _index, 0
47 .rep _reps
48 \insn \ar, _index << (\line_width)
49 .set _index, _index + 1
50 .endr
51 __endla \ar, \at, _reps << (\line_width)
52
53 .endm
54
37 55
38 __loopi \ar, \at, \size, (4 << (\line_width)) 56 .macro __loop_cache_all ar at insn size line_width max_immed
39 \insn \ar, 0 << (\line_width) 57
40 \insn \ar, 1 << (\line_width) 58 movi \ar, 0
41 \insn \ar, 2 << (\line_width) 59 __loop_cache_unroll \ar, \at, \insn, \size, \line_width, \max_immed
42 \insn \ar, 3 << (\line_width)
43 __endla \ar, \at, 4 << (\line_width)
44 60
45 .endm 61 .endm
46 62
@@ -57,14 +73,9 @@
57 .endm 73 .endm
58 74
59 75
60 .macro __loop_cache_page ar at insn line_width 76 .macro __loop_cache_page ar at insn line_width max_immed
61 77
62 __loopi \ar, \at, PAGE_SIZE, 4 << (\line_width) 78 __loop_cache_unroll \ar, \at, \insn, PAGE_SIZE, \line_width, \max_immed
63 \insn \ar, 0 << (\line_width)
64 \insn \ar, 1 << (\line_width)
65 \insn \ar, 2 << (\line_width)
66 \insn \ar, 3 << (\line_width)
67 __endla \ar, \at, 4 << (\line_width)
68 79
69 .endm 80 .endm
70 81
@@ -72,7 +83,8 @@
72 .macro ___unlock_dcache_all ar at 83 .macro ___unlock_dcache_all ar at
73 84
74#if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE 85#if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE
75 __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH 86 __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE \
87 XCHAL_DCACHE_LINEWIDTH 240
76#endif 88#endif
77 89
78 .endm 90 .endm
@@ -81,7 +93,8 @@
81 .macro ___unlock_icache_all ar at 93 .macro ___unlock_icache_all ar at
82 94
83#if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE 95#if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE
84 __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH 96 __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE \
97 XCHAL_ICACHE_LINEWIDTH 240
85#endif 98#endif
86 99
87 .endm 100 .endm
@@ -90,7 +103,8 @@
90 .macro ___flush_invalidate_dcache_all ar at 103 .macro ___flush_invalidate_dcache_all ar at
91 104
92#if XCHAL_DCACHE_SIZE 105#if XCHAL_DCACHE_SIZE
93 __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH 106 __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE \
107 XCHAL_DCACHE_LINEWIDTH 240
94#endif 108#endif
95 109
96 .endm 110 .endm
@@ -99,7 +113,8 @@
99 .macro ___flush_dcache_all ar at 113 .macro ___flush_dcache_all ar at
100 114
101#if XCHAL_DCACHE_SIZE 115#if XCHAL_DCACHE_SIZE
102 __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH 116 __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE \
117 XCHAL_DCACHE_LINEWIDTH 240
103#endif 118#endif
104 119
105 .endm 120 .endm
@@ -108,8 +123,8 @@
108 .macro ___invalidate_dcache_all ar at 123 .macro ___invalidate_dcache_all ar at
109 124
110#if XCHAL_DCACHE_SIZE 125#if XCHAL_DCACHE_SIZE
111 __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \ 126 __loop_cache_all \ar \at dii XCHAL_DCACHE_SIZE \
112 XCHAL_DCACHE_LINEWIDTH 127 XCHAL_DCACHE_LINEWIDTH 1020
113#endif 128#endif
114 129
115 .endm 130 .endm
@@ -118,8 +133,8 @@
118 .macro ___invalidate_icache_all ar at 133 .macro ___invalidate_icache_all ar at
119 134
120#if XCHAL_ICACHE_SIZE 135#if XCHAL_ICACHE_SIZE
121 __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \ 136 __loop_cache_all \ar \at iii XCHAL_ICACHE_SIZE \
122 XCHAL_ICACHE_LINEWIDTH 137 XCHAL_ICACHE_LINEWIDTH 1020
123#endif 138#endif
124 139
125 .endm 140 .endm
@@ -166,7 +181,7 @@
166 .macro ___flush_invalidate_dcache_page ar as 181 .macro ___flush_invalidate_dcache_page ar as
167 182
168#if XCHAL_DCACHE_SIZE 183#if XCHAL_DCACHE_SIZE
169 __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH 184 __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH 1020
170#endif 185#endif
171 186
172 .endm 187 .endm
@@ -175,7 +190,7 @@
175 .macro ___flush_dcache_page ar as 190 .macro ___flush_dcache_page ar as
176 191
177#if XCHAL_DCACHE_SIZE 192#if XCHAL_DCACHE_SIZE
178 __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH 193 __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH 1020
179#endif 194#endif
180 195
181 .endm 196 .endm
@@ -184,7 +199,7 @@
184 .macro ___invalidate_dcache_page ar as 199 .macro ___invalidate_dcache_page ar as
185 200
186#if XCHAL_DCACHE_SIZE 201#if XCHAL_DCACHE_SIZE
187 __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH 202 __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH 1020
188#endif 203#endif
189 204
190 .endm 205 .endm
@@ -193,7 +208,7 @@
193 .macro ___invalidate_icache_page ar as 208 .macro ___invalidate_icache_page ar as
194 209
195#if XCHAL_ICACHE_SIZE 210#if XCHAL_ICACHE_SIZE
196 __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH 211 __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH 1020
197#endif 212#endif
198 213
199 .endm 214 .endm
diff --git a/arch/xtensa/include/asm/dma-mapping.h b/arch/xtensa/include/asm/dma-mapping.h
deleted file mode 100644
index 44098800dad7..000000000000
--- a/arch/xtensa/include/asm/dma-mapping.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 - 2005 Tensilica Inc.
7 * Copyright (C) 2015 Cadence Design Systems Inc.
8 */
9
10#ifndef _XTENSA_DMA_MAPPING_H
11#define _XTENSA_DMA_MAPPING_H
12
13#include <asm/cache.h>
14#include <asm/io.h>
15
16#include <linux/mm.h>
17#include <linux/scatterlist.h>
18
19extern const struct dma_map_ops xtensa_dma_map_ops;
20
21static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
22{
23 return &xtensa_dma_map_ops;
24}
25
26#endif /* _XTENSA_DMA_MAPPING_H */
diff --git a/arch/xtensa/include/asm/initialize_mmu.h b/arch/xtensa/include/asm/initialize_mmu.h
index 42410f253597..10e9852b2fb4 100644
--- a/arch/xtensa/include/asm/initialize_mmu.h
+++ b/arch/xtensa/include/asm/initialize_mmu.h
@@ -177,36 +177,36 @@
177#endif /* defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU && 177#endif /* defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU &&
178 XCHAL_HAVE_SPANNING_WAY */ 178 XCHAL_HAVE_SPANNING_WAY */
179 179
180#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS && \ 180 .endm
181 (XCHAL_DCACHE_SIZE || XCHAL_ICACHE_SIZE) 181
182 /* Enable data and instruction cache in the DEFAULT_MEMORY region 182 .macro initialize_cacheattr
183 * if the processor has DTLB and ITLB.
184 */
185 183
186 movi a5, PLATFORM_DEFAULT_MEM_START | XCHAL_SPANNING_WAY 184#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS
185#if CONFIG_MEMMAP_CACHEATTR == 0x22222222 && XCHAL_HAVE_PTP_MMU
186#error Default MEMMAP_CACHEATTR of 0x22222222 does not work with full MMU.
187#endif
188
189 movi a5, XCHAL_SPANNING_WAY
187 movi a6, ~_PAGE_ATTRIB_MASK 190 movi a6, ~_PAGE_ATTRIB_MASK
188 movi a7, CA_WRITEBACK 191 movi a4, CONFIG_MEMMAP_CACHEATTR
189 movi a8, 0x20000000 192 movi a8, 0x20000000
190 movi a9, PLATFORM_DEFAULT_MEM_SIZE
191 j 2f
1921: 1931:
193 sub a9, a9, a8
1942:
195#if XCHAL_DCACHE_SIZE
196 rdtlb1 a3, a5 194 rdtlb1 a3, a5
195 xor a3, a3, a4
197 and a3, a3, a6 196 and a3, a3, a6
198 or a3, a3, a7 197 xor a3, a3, a4
199 wdtlb a3, a5 198 wdtlb a3, a5
200#endif 199 ritlb1 a3, a5
201#if XCHAL_ICACHE_SIZE 200 xor a3, a3, a4
202 ritlb1 a4, a5 201 and a3, a3, a6
203 and a4, a4, a6 202 xor a3, a3, a4
204 or a4, a4, a7 203 witlb a3, a5
205 witlb a4, a5 204
206#endif
207 add a5, a5, a8 205 add a5, a5, a8
208 bltu a8, a9, 1b 206 srli a4, a4, 4
207 bgeu a5, a8, 1b
209 208
209 isync
210#endif 210#endif
211 211
212 .endm 212 .endm
diff --git a/arch/xtensa/include/asm/irq.h b/arch/xtensa/include/asm/irq.h
index 19707db966f1..6c6ed23e0c79 100644
--- a/arch/xtensa/include/asm/irq.h
+++ b/arch/xtensa/include/asm/irq.h
@@ -12,32 +12,17 @@
12#define _XTENSA_IRQ_H 12#define _XTENSA_IRQ_H
13 13
14#include <linux/init.h> 14#include <linux/init.h>
15#include <platform/hardware.h>
16#include <variant/core.h> 15#include <variant/core.h>
17 16
18#ifdef CONFIG_VARIANT_IRQ_SWITCH 17#ifdef CONFIG_PLATFORM_NR_IRQS
19#include <variant/irq.h> 18# define PLATFORM_NR_IRQS CONFIG_PLATFORM_NR_IRQS
20#else 19#else
21static inline void variant_irq_enable(unsigned int irq) { }
22static inline void variant_irq_disable(unsigned int irq) { }
23#endif
24
25#ifndef VARIANT_NR_IRQS
26# define VARIANT_NR_IRQS 0
27#endif
28#ifndef PLATFORM_NR_IRQS
29# define PLATFORM_NR_IRQS 0 20# define PLATFORM_NR_IRQS 0
30#endif 21#endif
31#define XTENSA_NR_IRQS XCHAL_NUM_INTERRUPTS 22#define XTENSA_NR_IRQS XCHAL_NUM_INTERRUPTS
32#define NR_IRQS (XTENSA_NR_IRQS + VARIANT_NR_IRQS + PLATFORM_NR_IRQS + 1) 23#define NR_IRQS (XTENSA_NR_IRQS + PLATFORM_NR_IRQS + 1)
33#define XTENSA_PIC_LINUX_IRQ(hwirq) ((hwirq) + 1) 24#define XTENSA_PIC_LINUX_IRQ(hwirq) ((hwirq) + 1)
34 25
35#if VARIANT_NR_IRQS == 0
36static inline void variant_init_irq(void) { }
37#else
38void variant_init_irq(void) __init;
39#endif
40
41static __inline__ int irq_canonicalize(int irq) 26static __inline__ int irq_canonicalize(int irq)
42{ 27{
43 return (irq); 28 return (irq);
diff --git a/arch/xtensa/include/asm/kmem_layout.h b/arch/xtensa/include/asm/kmem_layout.h
index 2317c835a4db..9c12babc016c 100644
--- a/arch/xtensa/include/asm/kmem_layout.h
+++ b/arch/xtensa/include/asm/kmem_layout.h
@@ -63,12 +63,6 @@
63#error XCHAL_KSEG_PADDR is not properly aligned to XCHAL_KSEG_ALIGNMENT 63#error XCHAL_KSEG_PADDR is not properly aligned to XCHAL_KSEG_ALIGNMENT
64#endif 64#endif
65 65
66#else
67
68#define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xd0000000)
69#define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xd8000000)
70#define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x08000000)
71
72#endif 66#endif
73 67
74#ifndef CONFIG_KASAN 68#ifndef CONFIG_KASAN
diff --git a/arch/xtensa/include/asm/page.h b/arch/xtensa/include/asm/page.h
index 5d69c11c01b8..09c56cba442e 100644
--- a/arch/xtensa/include/asm/page.h
+++ b/arch/xtensa/include/asm/page.h
@@ -14,7 +14,6 @@
14#include <asm/processor.h> 14#include <asm/processor.h>
15#include <asm/types.h> 15#include <asm/types.h>
16#include <asm/cache.h> 16#include <asm/cache.h>
17#include <platform/hardware.h>
18#include <asm/kmem_layout.h> 17#include <asm/kmem_layout.h>
19 18
20/* 19/*
@@ -31,8 +30,8 @@
31#define MAX_LOW_PFN (PHYS_PFN(XCHAL_KSEG_PADDR) + \ 30#define MAX_LOW_PFN (PHYS_PFN(XCHAL_KSEG_PADDR) + \
32 PHYS_PFN(XCHAL_KSEG_SIZE)) 31 PHYS_PFN(XCHAL_KSEG_SIZE))
33#else 32#else
34#define PAGE_OFFSET PLATFORM_DEFAULT_MEM_START 33#define PAGE_OFFSET _AC(CONFIG_DEFAULT_MEM_START, UL)
35#define PHYS_OFFSET PLATFORM_DEFAULT_MEM_START 34#define PHYS_OFFSET _AC(CONFIG_DEFAULT_MEM_START, UL)
36#define MAX_LOW_PFN PHYS_PFN(0xfffffffful) 35#define MAX_LOW_PFN PHYS_PFN(0xfffffffful)
37#endif 36#endif
38 37
diff --git a/arch/xtensa/include/asm/pgtable.h b/arch/xtensa/include/asm/pgtable.h
index 38802259978f..29cfe421cf41 100644
--- a/arch/xtensa/include/asm/pgtable.h
+++ b/arch/xtensa/include/asm/pgtable.h
@@ -66,6 +66,7 @@
66#define FIRST_USER_ADDRESS 0UL 66#define FIRST_USER_ADDRESS 0UL
67#define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT) 67#define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT)
68 68
69#ifdef CONFIG_MMU
69/* 70/*
70 * Virtual memory area. We keep a distance to other memory regions to be 71 * Virtual memory area. We keep a distance to other memory regions to be
71 * on the safe side. We also use this area for cache aliasing. 72 * on the safe side. We also use this area for cache aliasing.
@@ -80,6 +81,13 @@
80#define TLBTEMP_SIZE ICACHE_WAY_SIZE 81#define TLBTEMP_SIZE ICACHE_WAY_SIZE
81#endif 82#endif
82 83
84#else
85
86#define VMALLOC_START __XTENSA_UL_CONST(0)
87#define VMALLOC_END __XTENSA_UL_CONST(0xffffffff)
88
89#endif
90
83/* 91/*
84 * For the Xtensa architecture, the PTE layout is as follows: 92 * For the Xtensa architecture, the PTE layout is as follows:
85 * 93 *
diff --git a/arch/xtensa/include/asm/platform.h b/arch/xtensa/include/asm/platform.h
index f8fbef67bc5f..560483356a06 100644
--- a/arch/xtensa/include/asm/platform.h
+++ b/arch/xtensa/include/asm/platform.h
@@ -75,4 +75,31 @@ extern void platform_calibrate_ccount (void);
75 */ 75 */
76void cpu_reset(void) __attribute__((noreturn)); 76void cpu_reset(void) __attribute__((noreturn));
77 77
78/*
79 * Memory caching is platform-dependent in noMMU xtensa configurations.
80 * The following set of functions should be implemented in platform code
81 * in order to enable coherent DMA memory operations when CONFIG_MMU is not
82 * enabled. Default implementations do nothing and issue a warning.
83 */
84
85/*
86 * Check whether p points to a cached memory.
87 */
88bool platform_vaddr_cached(const void *p);
89
90/*
91 * Check whether p points to an uncached memory.
92 */
93bool platform_vaddr_uncached(const void *p);
94
95/*
96 * Return pointer to an uncached view of the cached sddress p.
97 */
98void *platform_vaddr_to_uncached(void *p);
99
100/*
101 * Return pointer to a cached view of the uncached sddress p.
102 */
103void *platform_vaddr_to_cached(void *p);
104
78#endif /* _XTENSA_PLATFORM_H */ 105#endif /* _XTENSA_PLATFORM_H */
diff --git a/arch/xtensa/include/asm/processor.h b/arch/xtensa/include/asm/processor.h
index 5b0027d4ecc0..e4ccb88b7996 100644
--- a/arch/xtensa/include/asm/processor.h
+++ b/arch/xtensa/include/asm/processor.h
@@ -11,7 +11,6 @@
11#define _XTENSA_PROCESSOR_H 11#define _XTENSA_PROCESSOR_H
12 12
13#include <variant/core.h> 13#include <variant/core.h>
14#include <platform/hardware.h>
15 14
16#include <linux/compiler.h> 15#include <linux/compiler.h>
17#include <asm/ptrace.h> 16#include <asm/ptrace.h>
diff --git a/arch/xtensa/include/asm/vectors.h b/arch/xtensa/include/asm/vectors.h
index 65d3da9db19b..7111280c8842 100644
--- a/arch/xtensa/include/asm/vectors.h
+++ b/arch/xtensa/include/asm/vectors.h
@@ -19,7 +19,6 @@
19#define _XTENSA_VECTORS_H 19#define _XTENSA_VECTORS_H
20 20
21#include <variant/core.h> 21#include <variant/core.h>
22#include <platform/hardware.h>
23#include <asm/kmem_layout.h> 22#include <asm/kmem_layout.h>
24 23
25#if XCHAL_HAVE_PTP_MMU 24#if XCHAL_HAVE_PTP_MMU
diff --git a/arch/xtensa/kernel/head.S b/arch/xtensa/kernel/head.S
index 9c4e9433e536..2f76118ecf62 100644
--- a/arch/xtensa/kernel/head.S
+++ b/arch/xtensa/kernel/head.S
@@ -181,6 +181,8 @@ ENTRY(_startup)
181 181
182 isync 182 isync
183 183
184 initialize_cacheattr
185
184#ifdef CONFIG_HAVE_SMP 186#ifdef CONFIG_HAVE_SMP
185 movi a2, CCON # MX External Register to Configure Cache 187 movi a2, CCON # MX External Register to Configure Cache
186 movi a3, 1 188 movi a3, 1
diff --git a/arch/xtensa/kernel/irq.c b/arch/xtensa/kernel/irq.c
index 18e4ef34ac45..a48bf2d10ac2 100644
--- a/arch/xtensa/kernel/irq.c
+++ b/arch/xtensa/kernel/irq.c
@@ -158,7 +158,6 @@ void __init init_IRQ(void)
158#ifdef CONFIG_SMP 158#ifdef CONFIG_SMP
159 ipi_init(); 159 ipi_init();
160#endif 160#endif
161 variant_init_irq();
162} 161}
163 162
164#ifdef CONFIG_HOTPLUG_CPU 163#ifdef CONFIG_HOTPLUG_CPU
diff --git a/arch/xtensa/kernel/pci-dma.c b/arch/xtensa/kernel/pci-dma.c
index a02dc563d290..1fc138b6bc0a 100644
--- a/arch/xtensa/kernel/pci-dma.c
+++ b/arch/xtensa/kernel/pci-dma.c
@@ -16,26 +16,25 @@
16 */ 16 */
17 17
18#include <linux/dma-contiguous.h> 18#include <linux/dma-contiguous.h>
19#include <linux/dma-noncoherent.h>
19#include <linux/dma-direct.h> 20#include <linux/dma-direct.h>
20#include <linux/gfp.h> 21#include <linux/gfp.h>
21#include <linux/highmem.h> 22#include <linux/highmem.h>
22#include <linux/mm.h> 23#include <linux/mm.h>
23#include <linux/module.h>
24#include <linux/pci.h>
25#include <linux/string.h>
26#include <linux/types.h> 24#include <linux/types.h>
27#include <asm/cacheflush.h> 25#include <asm/cacheflush.h>
28#include <asm/io.h> 26#include <asm/io.h>
27#include <asm/platform.h>
29 28
30static void do_cache_op(dma_addr_t dma_handle, size_t size, 29static void do_cache_op(phys_addr_t paddr, size_t size,
31 void (*fn)(unsigned long, unsigned long)) 30 void (*fn)(unsigned long, unsigned long))
32{ 31{
33 unsigned long off = dma_handle & (PAGE_SIZE - 1); 32 unsigned long off = paddr & (PAGE_SIZE - 1);
34 unsigned long pfn = PFN_DOWN(dma_handle); 33 unsigned long pfn = PFN_DOWN(paddr);
35 struct page *page = pfn_to_page(pfn); 34 struct page *page = pfn_to_page(pfn);
36 35
37 if (!PageHighMem(page)) 36 if (!PageHighMem(page))
38 fn((unsigned long)bus_to_virt(dma_handle), size); 37 fn((unsigned long)phys_to_virt(paddr), size);
39 else 38 else
40 while (size > 0) { 39 while (size > 0) {
41 size_t sz = min_t(size_t, size, PAGE_SIZE - off); 40 size_t sz = min_t(size_t, size, PAGE_SIZE - off);
@@ -49,14 +48,13 @@ static void do_cache_op(dma_addr_t dma_handle, size_t size,
49 } 48 }
50} 49}
51 50
52static void xtensa_sync_single_for_cpu(struct device *dev, 51void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr,
53 dma_addr_t dma_handle, size_t size, 52 size_t size, enum dma_data_direction dir)
54 enum dma_data_direction dir)
55{ 53{
56 switch (dir) { 54 switch (dir) {
57 case DMA_BIDIRECTIONAL: 55 case DMA_BIDIRECTIONAL:
58 case DMA_FROM_DEVICE: 56 case DMA_FROM_DEVICE:
59 do_cache_op(dma_handle, size, __invalidate_dcache_range); 57 do_cache_op(paddr, size, __invalidate_dcache_range);
60 break; 58 break;
61 59
62 case DMA_NONE: 60 case DMA_NONE:
@@ -68,15 +66,14 @@ static void xtensa_sync_single_for_cpu(struct device *dev,
68 } 66 }
69} 67}
70 68
71static void xtensa_sync_single_for_device(struct device *dev, 69void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr,
72 dma_addr_t dma_handle, size_t size, 70 size_t size, enum dma_data_direction dir)
73 enum dma_data_direction dir)
74{ 71{
75 switch (dir) { 72 switch (dir) {
76 case DMA_BIDIRECTIONAL: 73 case DMA_BIDIRECTIONAL:
77 case DMA_TO_DEVICE: 74 case DMA_TO_DEVICE:
78 if (XCHAL_DCACHE_IS_WRITEBACK) 75 if (XCHAL_DCACHE_IS_WRITEBACK)
79 do_cache_op(dma_handle, size, __flush_dcache_range); 76 do_cache_op(paddr, size, __flush_dcache_range);
80 break; 77 break;
81 78
82 case DMA_NONE: 79 case DMA_NONE:
@@ -88,43 +85,66 @@ static void xtensa_sync_single_for_device(struct device *dev,
88 } 85 }
89} 86}
90 87
91static void xtensa_sync_sg_for_cpu(struct device *dev, 88#ifdef CONFIG_MMU
92 struct scatterlist *sg, int nents, 89bool platform_vaddr_cached(const void *p)
93 enum dma_data_direction dir)
94{ 90{
95 struct scatterlist *s; 91 unsigned long addr = (unsigned long)p;
96 int i;
97 92
98 for_each_sg(sg, s, nents, i) { 93 return addr >= XCHAL_KSEG_CACHED_VADDR &&
99 xtensa_sync_single_for_cpu(dev, sg_dma_address(s), 94 addr - XCHAL_KSEG_CACHED_VADDR < XCHAL_KSEG_SIZE;
100 sg_dma_len(s), dir);
101 }
102} 95}
103 96
104static void xtensa_sync_sg_for_device(struct device *dev, 97bool platform_vaddr_uncached(const void *p)
105 struct scatterlist *sg, int nents,
106 enum dma_data_direction dir)
107{ 98{
108 struct scatterlist *s; 99 unsigned long addr = (unsigned long)p;
109 int i;
110 100
111 for_each_sg(sg, s, nents, i) { 101 return addr >= XCHAL_KSEG_BYPASS_VADDR &&
112 xtensa_sync_single_for_device(dev, sg_dma_address(s), 102 addr - XCHAL_KSEG_BYPASS_VADDR < XCHAL_KSEG_SIZE;
113 sg_dma_len(s), dir); 103}
114 } 104
105void *platform_vaddr_to_uncached(void *p)
106{
107 return p + XCHAL_KSEG_BYPASS_VADDR - XCHAL_KSEG_CACHED_VADDR;
108}
109
110void *platform_vaddr_to_cached(void *p)
111{
112 return p + XCHAL_KSEG_CACHED_VADDR - XCHAL_KSEG_BYPASS_VADDR;
113}
114#else
115bool __attribute__((weak)) platform_vaddr_cached(const void *p)
116{
117 WARN_ONCE(1, "Default %s implementation is used\n", __func__);
118 return true;
119}
120
121bool __attribute__((weak)) platform_vaddr_uncached(const void *p)
122{
123 WARN_ONCE(1, "Default %s implementation is used\n", __func__);
124 return false;
125}
126
127void __attribute__((weak)) *platform_vaddr_to_uncached(void *p)
128{
129 WARN_ONCE(1, "Default %s implementation is used\n", __func__);
130 return p;
131}
132
133void __attribute__((weak)) *platform_vaddr_to_cached(void *p)
134{
135 WARN_ONCE(1, "Default %s implementation is used\n", __func__);
136 return p;
115} 137}
138#endif
116 139
117/* 140/*
118 * Note: We assume that the full memory space is always mapped to 'kseg' 141 * Note: We assume that the full memory space is always mapped to 'kseg'
119 * Otherwise we have to use page attributes (not implemented). 142 * Otherwise we have to use page attributes (not implemented).
120 */ 143 */
121 144
122static void *xtensa_dma_alloc(struct device *dev, size_t size, 145void *arch_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
123 dma_addr_t *handle, gfp_t flag, 146 gfp_t flag, unsigned long attrs)
124 unsigned long attrs)
125{ 147{
126 unsigned long ret;
127 unsigned long uncached;
128 unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT; 148 unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
129 struct page *page = NULL; 149 struct page *page = NULL;
130 150
@@ -147,6 +167,10 @@ static void *xtensa_dma_alloc(struct device *dev, size_t size,
147 167
148 *handle = phys_to_dma(dev, page_to_phys(page)); 168 *handle = phys_to_dma(dev, page_to_phys(page));
149 169
170 if (attrs & DMA_ATTR_NO_KERNEL_MAPPING) {
171 return page;
172 }
173
150#ifdef CONFIG_MMU 174#ifdef CONFIG_MMU
151 if (PageHighMem(page)) { 175 if (PageHighMem(page)) {
152 void *p; 176 void *p;
@@ -161,27 +185,21 @@ static void *xtensa_dma_alloc(struct device *dev, size_t size,
161 return p; 185 return p;
162 } 186 }
163#endif 187#endif
164 ret = (unsigned long)page_address(page); 188 BUG_ON(!platform_vaddr_cached(page_address(page)));
165 BUG_ON(ret < XCHAL_KSEG_CACHED_VADDR || 189 __invalidate_dcache_range((unsigned long)page_address(page), size);
166 ret > XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_SIZE - 1); 190 return platform_vaddr_to_uncached(page_address(page));
167
168 uncached = ret + XCHAL_KSEG_BYPASS_VADDR - XCHAL_KSEG_CACHED_VADDR;
169 __invalidate_dcache_range(ret, size);
170
171 return (void *)uncached;
172} 191}
173 192
174static void xtensa_dma_free(struct device *dev, size_t size, void *vaddr, 193void arch_dma_free(struct device *dev, size_t size, void *vaddr,
175 dma_addr_t dma_handle, unsigned long attrs) 194 dma_addr_t dma_handle, unsigned long attrs)
176{ 195{
177 unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT; 196 unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
178 unsigned long addr = (unsigned long)vaddr;
179 struct page *page; 197 struct page *page;
180 198
181 if (addr >= XCHAL_KSEG_BYPASS_VADDR && 199 if (attrs & DMA_ATTR_NO_KERNEL_MAPPING) {
182 addr - XCHAL_KSEG_BYPASS_VADDR < XCHAL_KSEG_SIZE) { 200 page = vaddr;
183 addr += XCHAL_KSEG_CACHED_VADDR - XCHAL_KSEG_BYPASS_VADDR; 201 } else if (platform_vaddr_uncached(vaddr)) {
184 page = virt_to_page(addr); 202 page = virt_to_page(platform_vaddr_to_cached(vaddr));
185 } else { 203 } else {
186#ifdef CONFIG_MMU 204#ifdef CONFIG_MMU
187 dma_common_free_remap(vaddr, size, VM_MAP); 205 dma_common_free_remap(vaddr, size, VM_MAP);
@@ -192,72 +210,3 @@ static void xtensa_dma_free(struct device *dev, size_t size, void *vaddr,
192 if (!dma_release_from_contiguous(dev, page, count)) 210 if (!dma_release_from_contiguous(dev, page, count))
193 __free_pages(page, get_order(size)); 211 __free_pages(page, get_order(size));
194} 212}
195
196static dma_addr_t xtensa_map_page(struct device *dev, struct page *page,
197 unsigned long offset, size_t size,
198 enum dma_data_direction dir,
199 unsigned long attrs)
200{
201 dma_addr_t dma_handle = page_to_phys(page) + offset;
202
203 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
204 xtensa_sync_single_for_device(dev, dma_handle, size, dir);
205
206 return dma_handle;
207}
208
209static void xtensa_unmap_page(struct device *dev, dma_addr_t dma_handle,
210 size_t size, enum dma_data_direction dir,
211 unsigned long attrs)
212{
213 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
214 xtensa_sync_single_for_cpu(dev, dma_handle, size, dir);
215}
216
217static int xtensa_map_sg(struct device *dev, struct scatterlist *sg,
218 int nents, enum dma_data_direction dir,
219 unsigned long attrs)
220{
221 struct scatterlist *s;
222 int i;
223
224 for_each_sg(sg, s, nents, i) {
225 s->dma_address = xtensa_map_page(dev, sg_page(s), s->offset,
226 s->length, dir, attrs);
227 }
228 return nents;
229}
230
231static void xtensa_unmap_sg(struct device *dev,
232 struct scatterlist *sg, int nents,
233 enum dma_data_direction dir,
234 unsigned long attrs)
235{
236 struct scatterlist *s;
237 int i;
238
239 for_each_sg(sg, s, nents, i) {
240 xtensa_unmap_page(dev, sg_dma_address(s),
241 sg_dma_len(s), dir, attrs);
242 }
243}
244
245int xtensa_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
246{
247 return 0;
248}
249
250const struct dma_map_ops xtensa_dma_map_ops = {
251 .alloc = xtensa_dma_alloc,
252 .free = xtensa_dma_free,
253 .map_page = xtensa_map_page,
254 .unmap_page = xtensa_unmap_page,
255 .map_sg = xtensa_map_sg,
256 .unmap_sg = xtensa_unmap_sg,
257 .sync_single_for_cpu = xtensa_sync_single_for_cpu,
258 .sync_single_for_device = xtensa_sync_single_for_device,
259 .sync_sg_for_cpu = xtensa_sync_sg_for_cpu,
260 .sync_sg_for_device = xtensa_sync_sg_for_device,
261 .mapping_error = xtensa_dma_mapping_error,
262};
263EXPORT_SYMBOL(xtensa_dma_map_ops);
diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c
index 686a27444bba..351283b60df6 100644
--- a/arch/xtensa/kernel/setup.c
+++ b/arch/xtensa/kernel/setup.c
@@ -47,8 +47,6 @@
47#include <asm/smp.h> 47#include <asm/smp.h>
48#include <asm/sysmem.h> 48#include <asm/sysmem.h>
49 49
50#include <platform/hardware.h>
51
52#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) 50#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
53struct screen_info screen_info = { 51struct screen_info screen_info = {
54 .orig_x = 0, 52 .orig_x = 0,
@@ -81,6 +79,7 @@ static char __initdata command_line[COMMAND_LINE_SIZE];
81static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE; 79static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
82#endif 80#endif
83 81
82#ifdef CONFIG_PARSE_BOOTPARAM
84/* 83/*
85 * Boot parameter parsing. 84 * Boot parameter parsing.
86 * 85 *
@@ -178,6 +177,13 @@ static int __init parse_bootparam(const bp_tag_t* tag)
178 177
179 return 0; 178 return 0;
180} 179}
180#else
181static int __init parse_bootparam(const bp_tag_t *tag)
182{
183 pr_info("Ignoring boot parameters at %p\n", tag);
184 return 0;
185}
186#endif
181 187
182#ifdef CONFIG_OF 188#ifdef CONFIG_OF
183 189
diff --git a/arch/xtensa/kernel/vmlinux.lds.S b/arch/xtensa/kernel/vmlinux.lds.S
index 70b731edc7b8..a1c3edb8ad56 100644
--- a/arch/xtensa/kernel/vmlinux.lds.S
+++ b/arch/xtensa/kernel/vmlinux.lds.S
@@ -20,7 +20,7 @@
20 20
21#include <asm/vectors.h> 21#include <asm/vectors.h>
22#include <variant/core.h> 22#include <variant/core.h>
23#include <platform/hardware.h> 23
24OUTPUT_ARCH(xtensa) 24OUTPUT_ARCH(xtensa)
25ENTRY(_start) 25ENTRY(_start)
26 26
diff --git a/arch/xtensa/platforms/iss/include/platform/hardware.h b/arch/xtensa/platforms/iss/include/platform/hardware.h
deleted file mode 100644
index 6930c12adc16..000000000000
--- a/arch/xtensa/platforms/iss/include/platform/hardware.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * include/asm-xtensa/platform-iss/hardware.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 Tensilica Inc.
9 */
10
11/*
12 * This file contains the default configuration of ISS.
13 */
14
15#ifndef _XTENSA_PLATFORM_ISS_HARDWARE_H
16#define _XTENSA_PLATFORM_ISS_HARDWARE_H
17
18/*
19 * Memory configuration.
20 */
21
22#define PLATFORM_DEFAULT_MEM_START 0x00000000
23#define PLATFORM_DEFAULT_MEM_SIZE 0x08000000
24
25/*
26 * Interrupt configuration.
27 */
28
29#endif /* _XTENSA_PLATFORM_ISS_HARDWARE_H */
diff --git a/arch/xtensa/platforms/xt2000/include/platform/hardware.h b/arch/xtensa/platforms/xt2000/include/platform/hardware.h
index 886ef156ded3..8e5e0d6a81ec 100644
--- a/arch/xtensa/platforms/xt2000/include/platform/hardware.h
+++ b/arch/xtensa/platforms/xt2000/include/platform/hardware.h
@@ -17,17 +17,6 @@
17 17
18#include <variant/core.h> 18#include <variant/core.h>
19 19
20/*
21 * Memory configuration.
22 */
23
24#define PLATFORM_DEFAULT_MEM_START 0x00000000
25#define PLATFORM_DEFAULT_MEM_SIZE 0x08000000
26
27/*
28 * Number of platform IRQs
29 */
30#define PLATFORM_NR_IRQS 3
31/* 20/*
32 * On-board components. 21 * On-board components.
33 */ 22 */
diff --git a/arch/xtensa/platforms/xtfpga/include/platform/hardware.h b/arch/xtensa/platforms/xtfpga/include/platform/hardware.h
index 1fda7e20dfcb..30d9cb6cf168 100644
--- a/arch/xtensa/platforms/xtfpga/include/platform/hardware.h
+++ b/arch/xtensa/platforms/xtfpga/include/platform/hardware.h
@@ -17,15 +17,6 @@
17#ifndef __XTENSA_XTAVNET_HARDWARE_H 17#ifndef __XTENSA_XTAVNET_HARDWARE_H
18#define __XTENSA_XTAVNET_HARDWARE_H 18#define __XTENSA_XTAVNET_HARDWARE_H
19 19
20/* Memory configuration. */
21
22#define PLATFORM_DEFAULT_MEM_START __XTENSA_UL(CONFIG_DEFAULT_MEM_START)
23#define PLATFORM_DEFAULT_MEM_SIZE __XTENSA_UL(CONFIG_DEFAULT_MEM_SIZE)
24
25/* Interrupt configuration. */
26
27#define PLATFORM_NR_IRQS 0
28
29/* Default assignment of LX60 devices to external interrupts. */ 20/* Default assignment of LX60 devices to external interrupts. */
30 21
31#ifdef CONFIG_XTENSA_MX 22#ifdef CONFIG_XTENSA_MX
diff --git a/arch/xtensa/variants/test_kc705_be/include/variant/core.h b/arch/xtensa/variants/test_kc705_be/include/variant/core.h
new file mode 100644
index 000000000000..a4ebdf7197d7
--- /dev/null
+++ b/arch/xtensa/variants/test_kc705_be/include/variant/core.h
@@ -0,0 +1,575 @@
1/*
2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
3 * processor CORE configuration
4 *
5 * See <xtensa/config/core.h>, which includes this file, for more details.
6 */
7
8/* Xtensa processor core configuration information.
9
10 Copyright (c) 1999-2015 Tensilica Inc.
11
12 Permission is hereby granted, free of charge, to any person obtaining
13 a copy of this software and associated documentation files (the
14 "Software"), to deal in the Software without restriction, including
15 without limitation the rights to use, copy, modify, merge, publish,
16 distribute, sublicense, and/or sell copies of the Software, and to
17 permit persons to whom the Software is furnished to do so, subject to
18 the following conditions:
19
20 The above copyright notice and this permission notice shall be included
21 in all copies or substantial portions of the Software.
22
23 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
26 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
27 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
28 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
29 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
30
31#ifndef _XTENSA_CORE_CONFIGURATION_H
32#define _XTENSA_CORE_CONFIGURATION_H
33
34
35/****************************************************************************
36 Parameters Useful for Any Code, USER or PRIVILEGED
37 ****************************************************************************/
38
39/*
40 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
41 * configured, and a value of 0 otherwise. These macros are always defined.
42 */
43
44
45/*----------------------------------------------------------------------
46 ISA
47 ----------------------------------------------------------------------*/
48
49#define XCHAL_HAVE_BE 1 /* big-endian byte ordering */
50#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
51#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
52#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
53#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
54#define XCHAL_HAVE_DEBUG 1 /* debug option */
55#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
56#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
57#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
58#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
59#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
60#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
61#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
62#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
63#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
64#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
65#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
66#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
67#define XCHAL_HAVE_L32R 1 /* L32R instruction */
68#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
69#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
70#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
71#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
72#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
73#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
74#define XCHAL_HAVE_ABS 1 /* ABS instruction */
75/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
76/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
77#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
78#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
79#define XCHAL_HAVE_SPECULATION 0 /* speculation */
80#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
81#define XCHAL_NUM_CONTEXTS 1 /* */
82#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
83#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
84#define XCHAL_HAVE_PRID 1 /* processor ID register */
85#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
86#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
87#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
88#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
89#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
90#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
91#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
92#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
93#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
94#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
95#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
96#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
97
98#define XCHAL_HAVE_FUSION 0 /* Fusion*/
99#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
100#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
101#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
102#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
103#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
104#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
105#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
106#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
107#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
108#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
109#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
110#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
111#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
112#define XCHAL_HAVE_HIFI2 1 /* HiFi2 Audio Engine pkg */
113#define XCHAL_HAVE_HIFI2_MUL32X24 1 /* HiFi2 and 32x24 MACs */
114#define XCHAL_HAVE_HIFI2EP 1 /* HiFi2EP */
115#define XCHAL_HAVE_HIFI_MINI 0
116
117
118#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */
119#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
120#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
121#define XCHAL_HAVE_FP 0 /* single prec floating point */
122#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */
123#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */
124#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */
125#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */
126#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
127#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
128#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
129#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
130#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
131#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
132#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
133
134#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
135#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
136#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
137#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
138#define XCHAL_HAVE_PDX4 0 /* PDX4 */
139#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
140#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
141#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
142#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
143#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
144#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
145#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
146#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
147#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
148#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
149#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
150#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
151#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
152#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
153#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
154#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
155
156
157/*----------------------------------------------------------------------
158 MISC
159 ----------------------------------------------------------------------*/
160
161#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
162#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
163#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
164#define XCHAL_DATA_WIDTH 8 /* data width in bytes */
165#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
166 (1 = 5-stage, 2 = 7-stage) */
167#define XCHAL_CLOCK_GATING_GLOBAL 0 /* global clock gating */
168#define XCHAL_CLOCK_GATING_FUNCUNIT 0 /* funct. unit clock gating */
169/* In T1050, applies to selected core load and store instructions (see ISA): */
170#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
171#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
172#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
173#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
174
175#define XCHAL_SW_VERSION 1100002 /* sw version of this header */
176
177#define XCHAL_CORE_ID "test_kc705_be" /* alphanum core name
178 (CoreID) set in the Xtensa
179 Processor Generator */
180
181#define XCHAL_BUILD_UNIQUE_ID 0x00058D8C /* 22-bit sw build ID */
182
183/*
184 * These definitions describe the hardware targeted by this software.
185 */
186#define XCHAL_HW_CONFIGID0 0xC1B3FFFF /* ConfigID hi 32 bits*/
187#define XCHAL_HW_CONFIGID1 0x1C858D8C /* ConfigID lo 32 bits*/
188#define XCHAL_HW_VERSION_NAME "LX6.0.2" /* full version name */
189#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */
190#define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */
191#define XCHAL_HW_VERSION 260002 /* major*100+minor */
192#define XCHAL_HW_REL_LX6 1
193#define XCHAL_HW_REL_LX6_0 1
194#define XCHAL_HW_REL_LX6_0_2 1
195#define XCHAL_HW_CONFIGID_RELIABLE 1
196/* If software targets a *range* of hardware versions, these are the bounds: */
197#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */
198#define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */
199#define XCHAL_HW_MIN_VERSION 260002 /* earliest targeted hw */
200#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */
201#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */
202#define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */
203
204
205/*----------------------------------------------------------------------
206 CACHE
207 ----------------------------------------------------------------------*/
208
209#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
210#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
211#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */
212#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */
213
214#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */
215#define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */
216
217#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
218#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
219
220#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */
221#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
222#define XCHAL_PREFETCH_CASTOUT_LINES 1 /* dcache pref. castout bufsz */
223#define XCHAL_PREFETCH_ENTRIES 8 /* cache prefetch entries */
224#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
225#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
226#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */
227#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */
228#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
229#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
230
231
232
233
234/****************************************************************************
235 Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
236 ****************************************************************************/
237
238
239#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
240
241/*----------------------------------------------------------------------
242 CACHE
243 ----------------------------------------------------------------------*/
244
245#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
246
247/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
248
249/* Number of cache sets in log2(lines per way): */
250#define XCHAL_ICACHE_SETWIDTH 7
251#define XCHAL_DCACHE_SETWIDTH 7
252
253/* Cache set associativity (number of ways): */
254#define XCHAL_ICACHE_WAYS 4
255#define XCHAL_DCACHE_WAYS 4
256
257/* Cache features: */
258#define XCHAL_ICACHE_LINE_LOCKABLE 1
259#define XCHAL_DCACHE_LINE_LOCKABLE 1
260#define XCHAL_ICACHE_ECC_PARITY 0
261#define XCHAL_DCACHE_ECC_PARITY 0
262
263/* Cache access size in bytes (affects operation of SICW instruction): */
264#define XCHAL_ICACHE_ACCESS_SIZE 8
265#define XCHAL_DCACHE_ACCESS_SIZE 8
266
267#define XCHAL_DCACHE_BANKS 1 /* number of banks */
268
269/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
270#define XCHAL_CA_BITS 4
271
272/* Whether MEMCTL register has anything useful */
273#define XCHAL_USE_MEMCTL (((XCHAL_LOOP_BUFFER_SIZE > 0) || \
274 XCHAL_DCACHE_IS_COHERENT || \
275 XCHAL_HAVE_ICACHE_DYN_WAYS || \
276 XCHAL_HAVE_DCACHE_DYN_WAYS) && \
277 (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0))
278
279
280/*----------------------------------------------------------------------
281 INTERNAL I/D RAM/ROMs and XLMI
282 ----------------------------------------------------------------------*/
283
284#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
285#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
286#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
287#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
288#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
289#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
290
291#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
292
293
294/*----------------------------------------------------------------------
295 INTERRUPTS and TIMERS
296 ----------------------------------------------------------------------*/
297
298#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
299#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
300#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
301#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
302#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
303#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
304#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
305#define XCHAL_NUM_EXTINTERRUPTS 16 /* num of external interrupts */
306#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
307 (not including level zero) */
308#define XCHAL_EXCM_LEVEL 4 /* level masked by PS.EXCM */
309 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
310
311/* Masks of interrupts at each interrupt level: */
312#define XCHAL_INTLEVEL1_MASK 0x001F00BF
313#define XCHAL_INTLEVEL2_MASK 0x00000140
314#define XCHAL_INTLEVEL3_MASK 0x00200E00
315#define XCHAL_INTLEVEL4_MASK 0x00008000
316#define XCHAL_INTLEVEL5_MASK 0x00003000
317#define XCHAL_INTLEVEL6_MASK 0x00000000
318#define XCHAL_INTLEVEL7_MASK 0x00004000
319
320/* Masks of interrupts at each range 1..n of interrupt levels: */
321#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F00BF
322#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F01FF
323#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F0FFF
324#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F8FFF
325#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF
326#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF
327#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF
328
329/* Level of each interrupt: */
330#define XCHAL_INT0_LEVEL 1
331#define XCHAL_INT1_LEVEL 1
332#define XCHAL_INT2_LEVEL 1
333#define XCHAL_INT3_LEVEL 1
334#define XCHAL_INT4_LEVEL 1
335#define XCHAL_INT5_LEVEL 1
336#define XCHAL_INT6_LEVEL 2
337#define XCHAL_INT7_LEVEL 1
338#define XCHAL_INT8_LEVEL 2
339#define XCHAL_INT9_LEVEL 3
340#define XCHAL_INT10_LEVEL 3
341#define XCHAL_INT11_LEVEL 3
342#define XCHAL_INT12_LEVEL 5
343#define XCHAL_INT13_LEVEL 5
344#define XCHAL_INT14_LEVEL 7
345#define XCHAL_INT15_LEVEL 4
346#define XCHAL_INT16_LEVEL 1
347#define XCHAL_INT17_LEVEL 1
348#define XCHAL_INT18_LEVEL 1
349#define XCHAL_INT19_LEVEL 1
350#define XCHAL_INT20_LEVEL 1
351#define XCHAL_INT21_LEVEL 3
352#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
353#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
354#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
355 EXCSAVE/EPS/EPC_n, RFI n) */
356
357/* Type of each interrupt: */
358#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
359#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
360#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
361#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
362#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
363#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
364#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
365#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
366#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
367#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
368#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
369#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
370#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
371#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
372#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
373#define XCHAL_INT15_TYPE XTHAL_INTTYPE_PROFILING
374#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
375#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
376#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
377#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
378#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
379#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
380
381/* Masks of interrupts for each type of interrupt: */
382#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
383#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880
384#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F0000
385#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F
386#define XCHAL_INTTYPE_MASK_TIMER 0x00002440
387#define XCHAL_INTTYPE_MASK_NMI 0x00004000
388#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
389#define XCHAL_INTTYPE_MASK_PROFILING 0x00008000
390
391/* Interrupt numbers assigned to specific interrupt sources: */
392#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
393#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */
394#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */
395#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
396#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
397#define XCHAL_PROFILING_INTERRUPT 15 /* profiling interrupt */
398
399/* Interrupt numbers for levels at which only one interrupt is configured: */
400#define XCHAL_INTLEVEL4_NUM 15
401#define XCHAL_INTLEVEL7_NUM 14
402/* (There are many interrupts each at level(s) 1, 2, 3, 5.) */
403
404
405/*
406 * External interrupt mapping.
407 * These macros describe how Xtensa processor interrupt numbers
408 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
409 * map to external BInterrupt<n> pins, for those interrupts
410 * configured as external (level-triggered, edge-triggered, or NMI).
411 * See the Xtensa processor databook for more details.
412 */
413
414/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
415#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
416#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
417#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
418#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
419#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
420#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
421#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
422#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
423#define XCHAL_EXTINT8_NUM 12 /* (intlevel 5) */
424#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
425#define XCHAL_EXTINT10_NUM 16 /* (intlevel 1) */
426#define XCHAL_EXTINT11_NUM 17 /* (intlevel 1) */
427#define XCHAL_EXTINT12_NUM 18 /* (intlevel 1) */
428#define XCHAL_EXTINT13_NUM 19 /* (intlevel 1) */
429#define XCHAL_EXTINT14_NUM 20 /* (intlevel 1) */
430#define XCHAL_EXTINT15_NUM 21 /* (intlevel 3) */
431/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
432#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
433#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
434#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
435#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
436#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
437#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
438#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */
439#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */
440#define XCHAL_INT12_EXTNUM 8 /* (intlevel 5) */
441#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */
442#define XCHAL_INT16_EXTNUM 10 /* (intlevel 1) */
443#define XCHAL_INT17_EXTNUM 11 /* (intlevel 1) */
444#define XCHAL_INT18_EXTNUM 12 /* (intlevel 1) */
445#define XCHAL_INT19_EXTNUM 13 /* (intlevel 1) */
446#define XCHAL_INT20_EXTNUM 14 /* (intlevel 1) */
447#define XCHAL_INT21_EXTNUM 15 /* (intlevel 3) */
448
449
450/*----------------------------------------------------------------------
451 EXCEPTIONS and VECTORS
452 ----------------------------------------------------------------------*/
453
454#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
455 number: 1 == XEA1 (old)
456 2 == XEA2 (new)
457 0 == XEAX (extern) or TX */
458#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
459#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
460#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
461#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
462#define XCHAL_HAVE_HALT 0 /* halt architecture option */
463#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
464#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
465#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
466#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
467#define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */
468#define XCHAL_VECBASE_RESET_PADDR 0x00002000
469#define XCHAL_RESET_VECBASE_OVERLAP 0
470
471#define XCHAL_RESET_VECTOR0_VADDR 0xFE000000
472#define XCHAL_RESET_VECTOR0_PADDR 0xFE000000
473#define XCHAL_RESET_VECTOR1_VADDR 0x00001000
474#define XCHAL_RESET_VECTOR1_PADDR 0x00001000
475#define XCHAL_RESET_VECTOR_VADDR 0xFE000000
476#define XCHAL_RESET_VECTOR_PADDR 0xFE000000
477#define XCHAL_USER_VECOFS 0x00000340
478#define XCHAL_USER_VECTOR_VADDR 0x00002340
479#define XCHAL_USER_VECTOR_PADDR 0x00002340
480#define XCHAL_KERNEL_VECOFS 0x00000300
481#define XCHAL_KERNEL_VECTOR_VADDR 0x00002300
482#define XCHAL_KERNEL_VECTOR_PADDR 0x00002300
483#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
484#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000023C0
485#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000023C0
486#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
487#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
488#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
489#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
490#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
491#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
492#define XCHAL_WINDOW_VECTORS_VADDR 0x00002000
493#define XCHAL_WINDOW_VECTORS_PADDR 0x00002000
494#define XCHAL_INTLEVEL2_VECOFS 0x00000180
495#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00002180
496#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00002180
497#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
498#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x000021C0
499#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000021C0
500#define XCHAL_INTLEVEL4_VECOFS 0x00000200
501#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x00002200
502#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00002200
503#define XCHAL_INTLEVEL5_VECOFS 0x00000240
504#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x00002240
505#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00002240
506#define XCHAL_INTLEVEL6_VECOFS 0x00000280
507#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00002280
508#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00002280
509#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
510#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
511#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
512#define XCHAL_NMI_VECOFS 0x000002C0
513#define XCHAL_NMI_VECTOR_VADDR 0x000022C0
514#define XCHAL_NMI_VECTOR_PADDR 0x000022C0
515#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
516#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
517#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
518
519
520/*----------------------------------------------------------------------
521 DEBUG MODULE
522 ----------------------------------------------------------------------*/
523
524/* Misc */
525#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */
526#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
527#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
528
529/* On-Chip Debug (OCD) */
530#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
531#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
532#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
533#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
534#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
535
536/* TRAX (in core) */
537#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */
538#define XCHAL_TRAX_MEM_SIZE 262144 /* TRAX memory size in bytes */
539#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */
540#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
541#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
542
543/* Perf counters */
544#define XCHAL_NUM_PERF_COUNTERS 8 /* performance counters */
545
546
547/*----------------------------------------------------------------------
548 MMU
549 ----------------------------------------------------------------------*/
550
551/* See core-matmap.h header file for more details. */
552
553#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
554#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
555#define XCHAL_SPANNING_WAY 6 /* TLB spanning way number */
556#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
557#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
558#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
559#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
560#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table
561 [autorefill] and protection)
562 usable for an MMU-based OS */
563/* If none of the above last 4 are set, it's a custom TLB configuration. */
564#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
565#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
566
567#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */
568#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */
569#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */
570
571#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
572
573
574#endif /* _XTENSA_CORE_CONFIGURATION_H */
575
diff --git a/arch/xtensa/variants/test_kc705_be/include/variant/tie-asm.h b/arch/xtensa/variants/test_kc705_be/include/variant/tie-asm.h
new file mode 100644
index 000000000000..b87fe1a5177b
--- /dev/null
+++ b/arch/xtensa/variants/test_kc705_be/include/variant/tie-asm.h
@@ -0,0 +1,308 @@
1/*
2 * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
3 *
4 * NOTE: This header file is not meant to be included directly.
5 */
6
7/* This header file contains assembly-language definitions (assembly
8 macros, etc.) for this specific Xtensa processor's TIE extensions
9 and options. It is customized to this Xtensa processor configuration.
10
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
12
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
15 "Software"), to deal in the Software without restriction, including
16 without limitation the rights to use, copy, modify, merge, publish,
17 distribute, sublicense, and/or sell copies of the Software, and to
18 permit persons to whom the Software is furnished to do so, subject to
19 the following conditions:
20
21 The above copyright notice and this permission notice shall be included
22 in all copies or substantial portions of the Software.
23
24 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
27 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
28 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
29 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
30 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
31
32#ifndef _XTENSA_CORE_TIE_ASM_H
33#define _XTENSA_CORE_TIE_ASM_H
34
35/* Selection parameter values for save-area save/restore macros: */
36/* Option vs. TIE: */
37#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
38#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
39#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
40/* Whether used automatically by compiler: */
41#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
42#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
43#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
44/* ABI handling across function calls: */
45#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
46#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
47#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
48#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
49/* Misc */
50#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
51#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
52 | ((ccuse) & XTHAL_SAS_ANYCC) \
53 | ((abi) & XTHAL_SAS_ANYABI) )
54
55
56 /*
57 * Macro to store all non-coprocessor (extra) custom TIE and optional state
58 * (not including zero-overhead loop registers).
59 * Required parameters:
60 * ptr Save area pointer address register (clobbered)
61 * (register must contain a 4 byte aligned address).
62 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
63 * registers are clobbered, the remaining are unused).
64 * Optional parameters:
65 * continue If macro invoked as part of a larger store sequence, set to 1
66 * if this is not the first in the sequence. Defaults to 0.
67 * ofs Offset from start of larger sequence (from value of first ptr
68 * in sequence) at which to store. Defaults to next available space
69 * (or 0 if <continue> is 0).
70 * select Select what category(ies) of registers to store, as a bitmask
71 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
72 * alloc Select what category(ies) of registers to allocate; if any
73 * category is selected here that is not in <select>, space for
74 * the corresponding registers is skipped without doing any store.
75 */
76 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
77 xchal_sa_start \continue, \ofs
78 // Optional global registers used by default by the compiler:
79 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
80 xchal_sa_align \ptr, 0, 1020, 4, 4
81 rur.THREADPTR \at1 // threadptr option
82 s32i \at1, \ptr, .Lxchal_ofs_+0
83 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
84 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
85 xchal_sa_align \ptr, 0, 1020, 4, 4
86 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
87 .endif
88 // Optional caller-saved registers used by default by the compiler:
89 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
90 xchal_sa_align \ptr, 0, 1016, 4, 4
91 rsr.ACCLO \at1 // MAC16 option
92 s32i \at1, \ptr, .Lxchal_ofs_+0
93 rsr.ACCHI \at1 // MAC16 option
94 s32i \at1, \ptr, .Lxchal_ofs_+4
95 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
96 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
97 xchal_sa_align \ptr, 0, 1016, 4, 4
98 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
99 .endif
100 // Optional caller-saved registers not used by default by the compiler:
101 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
102 xchal_sa_align \ptr, 0, 1000, 4, 4
103 rsr.BR \at1 // boolean option
104 s32i \at1, \ptr, .Lxchal_ofs_+0
105 rsr.SCOMPARE1 \at1 // conditional store option
106 s32i \at1, \ptr, .Lxchal_ofs_+4
107 rsr.M0 \at1 // MAC16 option
108 s32i \at1, \ptr, .Lxchal_ofs_+8
109 rsr.M1 \at1 // MAC16 option
110 s32i \at1, \ptr, .Lxchal_ofs_+12
111 rsr.M2 \at1 // MAC16 option
112 s32i \at1, \ptr, .Lxchal_ofs_+16
113 rsr.M3 \at1 // MAC16 option
114 s32i \at1, \ptr, .Lxchal_ofs_+20
115 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24
116 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
117 xchal_sa_align \ptr, 0, 1000, 4, 4
118 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24
119 .endif
120 .endm // xchal_ncp_store
121
122 /*
123 * Macro to load all non-coprocessor (extra) custom TIE and optional state
124 * (not including zero-overhead loop registers).
125 * Required parameters:
126 * ptr Save area pointer address register (clobbered)
127 * (register must contain a 4 byte aligned address).
128 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
129 * registers are clobbered, the remaining are unused).
130 * Optional parameters:
131 * continue If macro invoked as part of a larger load sequence, set to 1
132 * if this is not the first in the sequence. Defaults to 0.
133 * ofs Offset from start of larger sequence (from value of first ptr
134 * in sequence) at which to load. Defaults to next available space
135 * (or 0 if <continue> is 0).
136 * select Select what category(ies) of registers to load, as a bitmask
137 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
138 * alloc Select what category(ies) of registers to allocate; if any
139 * category is selected here that is not in <select>, space for
140 * the corresponding registers is skipped without doing any load.
141 */
142 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
143 xchal_sa_start \continue, \ofs
144 // Optional global registers used by default by the compiler:
145 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
146 xchal_sa_align \ptr, 0, 1020, 4, 4
147 l32i \at1, \ptr, .Lxchal_ofs_+0
148 wur.THREADPTR \at1 // threadptr option
149 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
150 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
151 xchal_sa_align \ptr, 0, 1020, 4, 4
152 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
153 .endif
154 // Optional caller-saved registers used by default by the compiler:
155 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
156 xchal_sa_align \ptr, 0, 1016, 4, 4
157 l32i \at1, \ptr, .Lxchal_ofs_+0
158 wsr.ACCLO \at1 // MAC16 option
159 l32i \at1, \ptr, .Lxchal_ofs_+4
160 wsr.ACCHI \at1 // MAC16 option
161 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
162 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
163 xchal_sa_align \ptr, 0, 1016, 4, 4
164 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
165 .endif
166 // Optional caller-saved registers not used by default by the compiler:
167 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
168 xchal_sa_align \ptr, 0, 1000, 4, 4
169 l32i \at1, \ptr, .Lxchal_ofs_+0
170 wsr.BR \at1 // boolean option
171 l32i \at1, \ptr, .Lxchal_ofs_+4
172 wsr.SCOMPARE1 \at1 // conditional store option
173 l32i \at1, \ptr, .Lxchal_ofs_+8
174 wsr.M0 \at1 // MAC16 option
175 l32i \at1, \ptr, .Lxchal_ofs_+12
176 wsr.M1 \at1 // MAC16 option
177 l32i \at1, \ptr, .Lxchal_ofs_+16
178 wsr.M2 \at1 // MAC16 option
179 l32i \at1, \ptr, .Lxchal_ofs_+20
180 wsr.M3 \at1 // MAC16 option
181 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24
182 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
183 xchal_sa_align \ptr, 0, 1000, 4, 4
184 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24
185 .endif
186 .endm // xchal_ncp_load
187
188
189#define XCHAL_NCP_NUM_ATMPS 1
190
191 /*
192 * Macro to store the state of TIE coprocessor AudioEngineLX.
193 * Required parameters:
194 * ptr Save area pointer address register (clobbered)
195 * (register must contain a 8 byte aligned address).
196 * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
197 * registers are clobbered, the remaining are unused).
198 * Optional parameters are the same as for xchal_ncp_store.
199 */
200#define xchal_cp_AudioEngineLX_store xchal_cp1_store
201 .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
202 xchal_sa_start \continue, \ofs
203 // Custom caller-saved registers not used by default by the compiler:
204 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
205 xchal_sa_align \ptr, 0, 0, 8, 8
206 rur.AE_OVF_SAR \at1 // ureg 240
207 s32i \at1, \ptr, .Lxchal_ofs_+0
208 rur.AE_BITHEAD \at1 // ureg 241
209 s32i \at1, \ptr, .Lxchal_ofs_+4
210 rur.AE_TS_FTS_BU_BP \at1 // ureg 242
211 s32i \at1, \ptr, .Lxchal_ofs_+8
212 rur.AE_SD_NO \at1 // ureg 243
213 s32i \at1, \ptr, .Lxchal_ofs_+12
214 rur.AE_CBEGIN0 \at1 // ureg 246
215 s32i \at1, \ptr, .Lxchal_ofs_+16
216 rur.AE_CEND0 \at1 // ureg 247
217 s32i \at1, \ptr, .Lxchal_ofs_+20
218 ae_sp24x2s.i aep0, \ptr, .Lxchal_ofs_+24
219 ae_sp24x2s.i aep1, \ptr, .Lxchal_ofs_+32
220 ae_sp24x2s.i aep2, \ptr, .Lxchal_ofs_+40
221 ae_sp24x2s.i aep3, \ptr, .Lxchal_ofs_+48
222 ae_sp24x2s.i aep4, \ptr, .Lxchal_ofs_+56
223 addi \ptr, \ptr, 64
224 ae_sp24x2s.i aep5, \ptr, .Lxchal_ofs_+0
225 ae_sp24x2s.i aep6, \ptr, .Lxchal_ofs_+8
226 ae_sp24x2s.i aep7, \ptr, .Lxchal_ofs_+16
227 ae_sq56s.i aeq0, \ptr, .Lxchal_ofs_+24
228 ae_sq56s.i aeq1, \ptr, .Lxchal_ofs_+32
229 ae_sq56s.i aeq2, \ptr, .Lxchal_ofs_+40
230 ae_sq56s.i aeq3, \ptr, .Lxchal_ofs_+48
231 .set .Lxchal_pofs_, .Lxchal_pofs_ + 64
232 .set .Lxchal_ofs_, .Lxchal_ofs_ + 56
233 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
234 xchal_sa_align \ptr, 0, 0, 8, 8
235 .set .Lxchal_ofs_, .Lxchal_ofs_ + 120
236 .endif
237 .endm // xchal_cp1_store
238
239 /*
240 * Macro to load the state of TIE coprocessor AudioEngineLX.
241 * Required parameters:
242 * ptr Save area pointer address register (clobbered)
243 * (register must contain a 8 byte aligned address).
244 * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
245 * registers are clobbered, the remaining are unused).
246 * Optional parameters are the same as for xchal_ncp_load.
247 */
248#define xchal_cp_AudioEngineLX_load xchal_cp1_load
249 .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
250 xchal_sa_start \continue, \ofs
251 // Custom caller-saved registers not used by default by the compiler:
252 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
253 xchal_sa_align \ptr, 0, 0, 8, 8
254 l32i \at1, \ptr, .Lxchal_ofs_+0
255 wur.AE_OVF_SAR \at1 // ureg 240
256 l32i \at1, \ptr, .Lxchal_ofs_+4
257 wur.AE_BITHEAD \at1 // ureg 241
258 l32i \at1, \ptr, .Lxchal_ofs_+8
259 wur.AE_TS_FTS_BU_BP \at1 // ureg 242
260 l32i \at1, \ptr, .Lxchal_ofs_+12
261 wur.AE_SD_NO \at1 // ureg 243
262 l32i \at1, \ptr, .Lxchal_ofs_+16
263 wur.AE_CBEGIN0 \at1 // ureg 246
264 l32i \at1, \ptr, .Lxchal_ofs_+20
265 wur.AE_CEND0 \at1 // ureg 247
266 ae_lp24x2.i aep0, \ptr, .Lxchal_ofs_+24
267 ae_lp24x2.i aep1, \ptr, .Lxchal_ofs_+32
268 ae_lp24x2.i aep2, \ptr, .Lxchal_ofs_+40
269 ae_lp24x2.i aep3, \ptr, .Lxchal_ofs_+48
270 ae_lp24x2.i aep4, \ptr, .Lxchal_ofs_+56
271 addi \ptr, \ptr, 64
272 ae_lp24x2.i aep5, \ptr, .Lxchal_ofs_+0
273 ae_lp24x2.i aep6, \ptr, .Lxchal_ofs_+8
274 ae_lp24x2.i aep7, \ptr, .Lxchal_ofs_+16
275 addi \ptr, \ptr, 24
276 ae_lq56.i aeq0, \ptr, .Lxchal_ofs_+0
277 ae_lq56.i aeq1, \ptr, .Lxchal_ofs_+8
278 ae_lq56.i aeq2, \ptr, .Lxchal_ofs_+16
279 ae_lq56.i aeq3, \ptr, .Lxchal_ofs_+24
280 .set .Lxchal_pofs_, .Lxchal_pofs_ + 88
281 .set .Lxchal_ofs_, .Lxchal_ofs_ + 32
282 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
283 xchal_sa_align \ptr, 0, 0, 8, 8
284 .set .Lxchal_ofs_, .Lxchal_ofs_ + 120
285 .endif
286 .endm // xchal_cp1_load
287
288#define XCHAL_CP1_NUM_ATMPS 1
289#define XCHAL_SA_NUM_ATMPS 1
290
291 /* Empty macros for unconfigured coprocessors: */
292 .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
293 .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
294 .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
295 .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
296 .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
297 .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
298 .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
299 .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
300 .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
301 .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
302 .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
303 .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
304 .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
305 .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
306
307#endif /*_XTENSA_CORE_TIE_ASM_H*/
308
diff --git a/arch/xtensa/variants/test_kc705_be/include/variant/tie.h b/arch/xtensa/variants/test_kc705_be/include/variant/tie.h
new file mode 100644
index 000000000000..4e1b4baac8e2
--- /dev/null
+++ b/arch/xtensa/variants/test_kc705_be/include/variant/tie.h
@@ -0,0 +1,182 @@
1/*
2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
3 *
4 * NOTE: This header file is not meant to be included directly.
5 */
6
7/* This header file describes this specific Xtensa processor's TIE extensions
8 that extend basic Xtensa core functionality. It is customized to this
9 Xtensa processor configuration.
10
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
12
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
15 "Software"), to deal in the Software without restriction, including
16 without limitation the rights to use, copy, modify, merge, publish,
17 distribute, sublicense, and/or sell copies of the Software, and to
18 permit persons to whom the Software is furnished to do so, subject to
19 the following conditions:
20
21 The above copyright notice and this permission notice shall be included
22 in all copies or substantial portions of the Software.
23
24 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
27 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
28 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
29 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
30 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
31
32#ifndef _XTENSA_CORE_TIE_H
33#define _XTENSA_CORE_TIE_H
34
35#define XCHAL_CP_NUM 2 /* number of coprocessors */
36#define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37#define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */
38#define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
39
40/* Basic parameters of each coprocessor: */
41#define XCHAL_CP1_NAME "AudioEngineLX"
42#define XCHAL_CP1_IDENT AudioEngineLX
43#define XCHAL_CP1_SA_SIZE 120 /* size of state save area */
44#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
45#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
46#define XCHAL_CP7_NAME "XTIOP"
47#define XCHAL_CP7_IDENT XTIOP
48#define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
49#define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
50#define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
51
52/* Filler info for unassigned coprocessors, to simplify arrays etc: */
53#define XCHAL_CP0_SA_SIZE 0
54#define XCHAL_CP0_SA_ALIGN 1
55#define XCHAL_CP2_SA_SIZE 0
56#define XCHAL_CP2_SA_ALIGN 1
57#define XCHAL_CP3_SA_SIZE 0
58#define XCHAL_CP3_SA_ALIGN 1
59#define XCHAL_CP4_SA_SIZE 0
60#define XCHAL_CP4_SA_ALIGN 1
61#define XCHAL_CP5_SA_SIZE 0
62#define XCHAL_CP5_SA_ALIGN 1
63#define XCHAL_CP6_SA_SIZE 0
64#define XCHAL_CP6_SA_ALIGN 1
65
66/* Save area for non-coprocessor optional and custom (TIE) state: */
67#define XCHAL_NCP_SA_SIZE 36
68#define XCHAL_NCP_SA_ALIGN 4
69
70/* Total save area for optional and custom state (NCP + CPn): */
71#define XCHAL_TOTAL_SA_SIZE 160 /* with 16-byte align padding */
72#define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */
73
74/*
75 * Detailed contents of save areas.
76 * NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
77 * before expanding the XCHAL_xxx_SA_LIST() macros.
78 *
79 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
80 * dbnum,base,regnum,bitsz,gapsz,reset,x...)
81 *
82 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
83 * ccused = set if used by compiler without special options or code
84 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
85 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
86 * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
87 * name = lowercase reg name (no quotes)
88 * galign = group byte alignment (power of 2) (galign >= align)
89 * align = register byte alignment (power of 2)
90 * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
91 * (not including any pad bytes required to galign this or next reg)
92 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
93 * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
94 * regnum = reg index in regfile, or special/TIE-user reg number
95 * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
96 * gapsz = intervening bits, if bitsz bits not stored contiguously
97 * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
98 * reset = register reset value (or 0 if undefined at reset)
99 * x = reserved for future use (0 until then)
100 *
101 * To filter out certain registers, e.g. to expand only the non-global
102 * registers used by the compiler, you can do something like this:
103 *
104 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
105 * #define SELCC0(p...)
106 * #define SELCC1(abikind,p...) SELAK##abikind(p)
107 * #define SELAK0(p...) REG(p)
108 * #define SELAK1(p...) REG(p)
109 * #define SELAK2(p...)
110 * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
111 * ...what you want to expand...
112 */
113
114#define XCHAL_NCP_SA_NUM 9
115#define XCHAL_NCP_SA_LIST(s) \
116 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
117 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
118 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
120 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
121 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
122 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
123 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
124 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0)
125
126#define XCHAL_CP0_SA_NUM 0
127#define XCHAL_CP0_SA_LIST(s) /* empty */
128
129#define XCHAL_CP1_SA_NUM 18
130#define XCHAL_CP1_SA_LIST(s) \
131 XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 8, 4, 4,0x03F0, ur,240, 7,0,0,0) \
132 XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \
133 XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \
134 XCHAL_SA_REG(s,0,0,1,0, ae_sd_no, 4, 4, 4,0x03F3, ur,243, 28,0,0,0) \
135 XCHAL_SA_REG(s,0,0,1,0, ae_cbegin0, 4, 4, 4,0x03F6, ur,246, 32,0,0,0) \
136 XCHAL_SA_REG(s,0,0,1,0, ae_cend0, 4, 4, 4,0x03F7, ur,247, 32,0,0,0) \
137 XCHAL_SA_REG(s,0,0,2,0, aep0, 8, 8, 8,0x0060, aep,0 , 48,0,0,0) \
138 XCHAL_SA_REG(s,0,0,2,0, aep1, 8, 8, 8,0x0061, aep,1 , 48,0,0,0) \
139 XCHAL_SA_REG(s,0,0,2,0, aep2, 8, 8, 8,0x0062, aep,2 , 48,0,0,0) \
140 XCHAL_SA_REG(s,0,0,2,0, aep3, 8, 8, 8,0x0063, aep,3 , 48,0,0,0) \
141 XCHAL_SA_REG(s,0,0,2,0, aep4, 8, 8, 8,0x0064, aep,4 , 48,0,0,0) \
142 XCHAL_SA_REG(s,0,0,2,0, aep5, 8, 8, 8,0x0065, aep,5 , 48,0,0,0) \
143 XCHAL_SA_REG(s,0,0,2,0, aep6, 8, 8, 8,0x0066, aep,6 , 48,0,0,0) \
144 XCHAL_SA_REG(s,0,0,2,0, aep7, 8, 8, 8,0x0067, aep,7 , 48,0,0,0) \
145 XCHAL_SA_REG(s,0,0,2,0, aeq0, 8, 8, 8,0x0068, aeq,0 , 56,0,0,0) \
146 XCHAL_SA_REG(s,0,0,2,0, aeq1, 8, 8, 8,0x0069, aeq,1 , 56,0,0,0) \
147 XCHAL_SA_REG(s,0,0,2,0, aeq2, 8, 8, 8,0x006A, aeq,2 , 56,0,0,0) \
148 XCHAL_SA_REG(s,0,0,2,0, aeq3, 8, 8, 8,0x006B, aeq,3 , 56,0,0,0)
149
150#define XCHAL_CP2_SA_NUM 0
151#define XCHAL_CP2_SA_LIST(s) /* empty */
152
153#define XCHAL_CP3_SA_NUM 0
154#define XCHAL_CP3_SA_LIST(s) /* empty */
155
156#define XCHAL_CP4_SA_NUM 0
157#define XCHAL_CP4_SA_LIST(s) /* empty */
158
159#define XCHAL_CP5_SA_NUM 0
160#define XCHAL_CP5_SA_LIST(s) /* empty */
161
162#define XCHAL_CP6_SA_NUM 0
163#define XCHAL_CP6_SA_LIST(s) /* empty */
164
165#define XCHAL_CP7_SA_NUM 0
166#define XCHAL_CP7_SA_LIST(s) /* empty */
167
168/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
169#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8
170/* Byte length of instruction from its first byte, per FLIX. */
171#define XCHAL_BYTE0_FORMAT_LENGTHS \
172 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,\
173 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,\
174 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,\
175 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,\
176 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2, 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,\
177 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2, 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,\
178 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2, 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,\
179 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8
180
181#endif /*_XTENSA_CORE_TIE_H*/
182
diff --git a/drivers/irqchip/irq-xtensa-mx.c b/drivers/irqchip/irq-xtensa-mx.c
index a15a9510c904..e539500752d4 100644
--- a/drivers/irqchip/irq-xtensa-mx.c
+++ b/drivers/irqchip/irq-xtensa-mx.c
@@ -98,14 +98,12 @@ static void xtensa_mx_irq_unmask(struct irq_data *d)
98 98
99static void xtensa_mx_irq_enable(struct irq_data *d) 99static void xtensa_mx_irq_enable(struct irq_data *d)
100{ 100{
101 variant_irq_enable(d->hwirq);
102 xtensa_mx_irq_unmask(d); 101 xtensa_mx_irq_unmask(d);
103} 102}
104 103
105static void xtensa_mx_irq_disable(struct irq_data *d) 104static void xtensa_mx_irq_disable(struct irq_data *d)
106{ 105{
107 xtensa_mx_irq_mask(d); 106 xtensa_mx_irq_mask(d);
108 variant_irq_disable(d->hwirq);
109} 107}
110 108
111static void xtensa_mx_irq_ack(struct irq_data *d) 109static void xtensa_mx_irq_ack(struct irq_data *d)
diff --git a/drivers/irqchip/irq-xtensa-pic.c b/drivers/irqchip/irq-xtensa-pic.c
index f728755fa292..000cb5462bcf 100644
--- a/drivers/irqchip/irq-xtensa-pic.c
+++ b/drivers/irqchip/irq-xtensa-pic.c
@@ -55,14 +55,12 @@ static void xtensa_irq_unmask(struct irq_data *d)
55 55
56static void xtensa_irq_enable(struct irq_data *d) 56static void xtensa_irq_enable(struct irq_data *d)
57{ 57{
58 variant_irq_enable(d->hwirq);
59 xtensa_irq_unmask(d); 58 xtensa_irq_unmask(d);
60} 59}
61 60
62static void xtensa_irq_disable(struct irq_data *d) 61static void xtensa_irq_disable(struct irq_data *d)
63{ 62{
64 xtensa_irq_mask(d); 63 xtensa_irq_mask(d);
65 variant_irq_disable(d->hwirq);
66} 64}
67 65
68static void xtensa_irq_ack(struct irq_data *d) 66static void xtensa_irq_ack(struct irq_data *d)
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 19:23:59 -0400