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authorTony Lindgren <tony@atomide.com>2014-05-28 13:14:48 -0400
committerTony Lindgren <tony@atomide.com>2014-05-28 13:14:48 -0400
commit43369f0fe81044427f6b1eedeb16bf8c74c86d48 (patch)
tree542d6bf069f0983daf52a994751ca63c1472d84f
parent99ffa6425f1b9ac39c5e9946c1c286f687b97c3e (diff)
parentbc797691de8556a1dd3b6d008eedc0798ee3b407 (diff)
Merge branch 'for-v3.16/clk-dt' of https://github.com/t-kristo/linux-pm into omap-for-v3.16/dt-v2
Diffstat
-rw-r--r--arch/arm/boot/dts/am33xx-clocks.dtsi30
-rw-r--r--arch/arm/boot/dts/am43xx-clocks.dtsi75
-rw-r--r--arch/arm/boot/dts/omap2420-clocks.dtsi270
-rw-r--r--arch/arm/boot/dts/omap2420.dtsi26
-rw-r--r--arch/arm/boot/dts/omap2430-clocks.dtsi344
-rw-r--r--arch/arm/boot/dts/omap2430.dtsi26
-rw-r--r--arch/arm/boot/dts/omap24xx-clocks.dtsi1244
-rw-r--r--arch/arm/boot/dts/omap36xx-clocks.dtsi2
-rw-r--r--arch/arm/boot/dts/omap3xxx-clocks.dtsi7
-rw-r--r--arch/arm/boot/dts/omap4.dtsi1
-rw-r--r--arch/arm/boot/dts/omap54xx-clocks.dtsi58
-rw-r--r--drivers/clk/ti/clk-43xx.c6
12 files changed, 2006 insertions, 83 deletions
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
index 9ccfe508dea2..712edce7d6fb 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -96,47 +96,29 @@
96 clock-div = <1>; 96 clock-div = <1>;
97 }; 97 };
98 98
99 ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk { 99 ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
100 #clock-cells = <0>; 100 #clock-cells = <0>;
101 compatible = "ti,composite-no-wait-gate-clock"; 101 compatible = "ti,gate-clock";
102 clocks = <&dpll_per_m2_ck>; 102 clocks = <&dpll_per_m2_ck>;
103 ti,bit-shift = <0>; 103 ti,bit-shift = <0>;
104 reg = <0x0664>; 104 reg = <0x0664>;
105 }; 105 };
106 106
107 ehrpwm0_tbclk: ehrpwm0_tbclk { 107 ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
108 #clock-cells = <0>;
109 compatible = "ti,composite-clock";
110 clocks = <&ehrpwm0_gate_tbclk>;
111 };
112
113 ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {
114 #clock-cells = <0>; 108 #clock-cells = <0>;
115 compatible = "ti,composite-no-wait-gate-clock"; 109 compatible = "ti,gate-clock";
116 clocks = <&dpll_per_m2_ck>; 110 clocks = <&dpll_per_m2_ck>;
117 ti,bit-shift = <1>; 111 ti,bit-shift = <1>;
118 reg = <0x0664>; 112 reg = <0x0664>;
119 }; 113 };
120 114
121 ehrpwm1_tbclk: ehrpwm1_tbclk { 115 ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
122 #clock-cells = <0>;
123 compatible = "ti,composite-clock";
124 clocks = <&ehrpwm1_gate_tbclk>;
125 };
126
127 ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {
128 #clock-cells = <0>; 116 #clock-cells = <0>;
129 compatible = "ti,composite-no-wait-gate-clock"; 117 compatible = "ti,gate-clock";
130 clocks = <&dpll_per_m2_ck>; 118 clocks = <&dpll_per_m2_ck>;
131 ti,bit-shift = <2>; 119 ti,bit-shift = <2>;
132 reg = <0x0664>; 120 reg = <0x0664>;
133 }; 121 };
134
135 ehrpwm2_tbclk: ehrpwm2_tbclk {
136 #clock-cells = <0>;
137 compatible = "ti,composite-clock";
138 clocks = <&ehrpwm2_gate_tbclk>;
139 };
140}; 122};
141&prcm_clocks { 123&prcm_clocks {
142 clk_32768_ck: clk_32768_ck { 124 clk_32768_ck: clk_32768_ck {
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index 775d5b103992..c7dc9dab93a4 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -11,6 +11,22 @@
11 sys_clkin_ck: sys_clkin_ck { 11 sys_clkin_ck: sys_clkin_ck {
12 #clock-cells = <0>; 12 #clock-cells = <0>;
13 compatible = "ti,mux-clock"; 13 compatible = "ti,mux-clock";
14 clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
15 ti,bit-shift = <31>;
16 reg = <0x0040>;
17 };
18
19 crystal_freq_sel_ck: crystal_freq_sel_ck {
20 #clock-cells = <0>;
21 compatible = "ti,mux-clock";
22 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
23 ti,bit-shift = <29>;
24 reg = <0x0040>;
25 };
26
27 sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 {
28 #clock-cells = <0>;
29 compatible = "ti,mux-clock";
14 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; 30 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
15 ti,bit-shift = <22>; 31 ti,bit-shift = <22>;
16 reg = <0x0040>; 32 reg = <0x0040>;
@@ -87,6 +103,54 @@
87 clock-mult = <1>; 103 clock-mult = <1>;
88 clock-div = <1>; 104 clock-div = <1>;
89 }; 105 };
106
107 ehrpwm0_tbclk: ehrpwm0_tbclk {
108 #clock-cells = <0>;
109 compatible = "ti,gate-clock";
110 clocks = <&dpll_per_m2_ck>;
111 ti,bit-shift = <0>;
112 reg = <0x0664>;
113 };
114
115 ehrpwm1_tbclk: ehrpwm1_tbclk {
116 #clock-cells = <0>;
117 compatible = "ti,gate-clock";
118 clocks = <&dpll_per_m2_ck>;
119 ti,bit-shift = <1>;
120 reg = <0x0664>;
121 };
122
123 ehrpwm2_tbclk: ehrpwm2_tbclk {
124 #clock-cells = <0>;
125 compatible = "ti,gate-clock";
126 clocks = <&dpll_per_m2_ck>;
127 ti,bit-shift = <2>;
128 reg = <0x0664>;
129 };
130
131 ehrpwm3_tbclk: ehrpwm3_tbclk {
132 #clock-cells = <0>;
133 compatible = "ti,gate-clock";
134 clocks = <&dpll_per_m2_ck>;
135 ti,bit-shift = <4>;
136 reg = <0x0664>;
137 };
138
139 ehrpwm4_tbclk: ehrpwm4_tbclk {
140 #clock-cells = <0>;
141 compatible = "ti,gate-clock";
142 clocks = <&dpll_per_m2_ck>;
143 ti,bit-shift = <5>;
144 reg = <0x0664>;
145 };
146
147 ehrpwm5_tbclk: ehrpwm5_tbclk {
148 #clock-cells = <0>;
149 compatible = "ti,gate-clock";
150 clocks = <&dpll_per_m2_ck>;
151 ti,bit-shift = <6>;
152 reg = <0x0664>;
153 };
90}; 154};
91&prcm_clocks { 155&prcm_clocks {
92 clk_32768_ck: clk_32768_ck { 156 clk_32768_ck: clk_32768_ck {
@@ -229,6 +293,7 @@
229 reg = <0x2e30>; 293 reg = <0x2e30>;
230 ti,index-starts-at-one; 294 ti,index-starts-at-one;
231 ti,invert-autoidle-bit; 295 ti,invert-autoidle-bit;
296 ti,set-rate-parent;
232 }; 297 };
233 298
234 dpll_per_ck: dpll_per_ck { 299 dpll_per_ck: dpll_per_ck {
@@ -511,6 +576,7 @@
511 compatible = "ti,mux-clock"; 576 compatible = "ti,mux-clock";
512 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; 577 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
513 reg = <0x4244>; 578 reg = <0x4244>;
579 ti,set-rate-parent;
514 }; 580 };
515 581
516 dpll_extdev_ck: dpll_extdev_ck { 582 dpll_extdev_ck: dpll_extdev_ck {
@@ -609,10 +675,13 @@
609 675
610 dpll_per_clkdcoldo: dpll_per_clkdcoldo { 676 dpll_per_clkdcoldo: dpll_per_clkdcoldo {
611 #clock-cells = <0>; 677 #clock-cells = <0>;
612 compatible = "fixed-factor-clock"; 678 compatible = "ti,fixed-factor-clock";
613 clocks = <&dpll_per_ck>; 679 clocks = <&dpll_per_ck>;
614 clock-mult = <1>; 680 ti,clock-mult = <1>;
615 clock-div = <1>; 681 ti,clock-div = <1>;
682 ti,autoidle-shift = <8>;
683 reg = <0x2e14>;
684 ti,invert-autoidle-bit;
616 }; 685 };
617 686
618 dll_aging_clk_div: dll_aging_clk_div { 687 dll_aging_clk_div: dll_aging_clk_div {
diff --git a/arch/arm/boot/dts/omap2420-clocks.dtsi b/arch/arm/boot/dts/omap2420-clocks.dtsi
new file mode 100644
index 000000000000..ce8c742d7e92
--- /dev/null
+++ b/arch/arm/boot/dts/omap2420-clocks.dtsi
@@ -0,0 +1,270 @@
1/*
2 * Device Tree Source for OMAP2420 clock data
3 *
4 * Copyright (C) 2014 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11&prcm_clocks {
12 sys_clkout2_src_gate: sys_clkout2_src_gate {
13 #clock-cells = <0>;
14 compatible = "ti,composite-no-wait-gate-clock";
15 clocks = <&core_ck>;
16 ti,bit-shift = <15>;
17 reg = <0x0070>;
18 };
19
20 sys_clkout2_src_mux: sys_clkout2_src_mux {
21 #clock-cells = <0>;
22 compatible = "ti,composite-mux-clock";
23 clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
24 ti,bit-shift = <8>;
25 reg = <0x0070>;
26 };
27
28 sys_clkout2_src: sys_clkout2_src {
29 #clock-cells = <0>;
30 compatible = "ti,composite-clock";
31 clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;
32 };
33
34 sys_clkout2: sys_clkout2 {
35 #clock-cells = <0>;
36 compatible = "ti,divider-clock";
37 clocks = <&sys_clkout2_src>;
38 ti,bit-shift = <11>;
39 ti,max-div = <64>;
40 reg = <0x0070>;
41 ti,index-power-of-two;
42 };
43
44 dsp_gate_ick: dsp_gate_ick {
45 #clock-cells = <0>;
46 compatible = "ti,composite-interface-clock";
47 clocks = <&dsp_fck>;
48 ti,bit-shift = <1>;
49 reg = <0x0810>;
50 };
51
52 dsp_div_ick: dsp_div_ick {
53 #clock-cells = <0>;
54 compatible = "ti,composite-divider-clock";
55 clocks = <&dsp_fck>;
56 ti,bit-shift = <5>;
57 ti,max-div = <3>;
58 reg = <0x0840>;
59 ti,index-starts-at-one;
60 };
61
62 dsp_ick: dsp_ick {
63 #clock-cells = <0>;
64 compatible = "ti,composite-clock";
65 clocks = <&dsp_gate_ick>, <&dsp_div_ick>;
66 };
67
68 iva1_gate_ifck: iva1_gate_ifck {
69 #clock-cells = <0>;
70 compatible = "ti,composite-gate-clock";
71 clocks = <&core_ck>;
72 ti,bit-shift = <10>;
73 reg = <0x0800>;
74 };
75
76 iva1_div_ifck: iva1_div_ifck {
77 #clock-cells = <0>;
78 compatible = "ti,composite-divider-clock";
79 clocks = <&core_ck>;
80 ti,bit-shift = <8>;
81 reg = <0x0840>;
82 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
83 };
84
85 iva1_ifck: iva1_ifck {
86 #clock-cells = <0>;
87 compatible = "ti,composite-clock";
88 clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>;
89 };
90
91 iva1_ifck_div: iva1_ifck_div {
92 #clock-cells = <0>;
93 compatible = "fixed-factor-clock";
94 clocks = <&iva1_ifck>;
95 clock-mult = <1>;
96 clock-div = <2>;
97 };
98
99 iva1_mpu_int_ifck: iva1_mpu_int_ifck {
100 #clock-cells = <0>;
101 compatible = "ti,wait-gate-clock";
102 clocks = <&iva1_ifck_div>;
103 ti,bit-shift = <8>;
104 reg = <0x0800>;
105 };
106
107 wdt3_ick: wdt3_ick {
108 #clock-cells = <0>;
109 compatible = "ti,omap3-interface-clock";
110 clocks = <&l4_ck>;
111 ti,bit-shift = <28>;
112 reg = <0x0210>;
113 };
114
115 wdt3_fck: wdt3_fck {
116 #clock-cells = <0>;
117 compatible = "ti,wait-gate-clock";
118 clocks = <&func_32k_ck>;
119 ti,bit-shift = <28>;
120 reg = <0x0200>;
121 };
122
123 mmc_ick: mmc_ick {
124 #clock-cells = <0>;
125 compatible = "ti,omap3-interface-clock";
126 clocks = <&l4_ck>;
127 ti,bit-shift = <26>;
128 reg = <0x0210>;
129 };
130
131 mmc_fck: mmc_fck {
132 #clock-cells = <0>;
133 compatible = "ti,wait-gate-clock";
134 clocks = <&func_96m_ck>;
135 ti,bit-shift = <26>;
136 reg = <0x0200>;
137 };
138
139 eac_ick: eac_ick {
140 #clock-cells = <0>;
141 compatible = "ti,omap3-interface-clock";
142 clocks = <&l4_ck>;
143 ti,bit-shift = <24>;
144 reg = <0x0210>;
145 };
146
147 eac_fck: eac_fck {
148 #clock-cells = <0>;
149 compatible = "ti,wait-gate-clock";
150 clocks = <&func_96m_ck>;
151 ti,bit-shift = <24>;
152 reg = <0x0200>;
153 };
154
155 i2c1_fck: i2c1_fck {
156 #clock-cells = <0>;
157 compatible = "ti,wait-gate-clock";
158 clocks = <&func_12m_ck>;
159 ti,bit-shift = <19>;
160 reg = <0x0200>;
161 };
162
163 i2c2_fck: i2c2_fck {
164 #clock-cells = <0>;
165 compatible = "ti,wait-gate-clock";
166 clocks = <&func_12m_ck>;
167 ti,bit-shift = <20>;
168 reg = <0x0200>;
169 };
170
171 vlynq_ick: vlynq_ick {
172 #clock-cells = <0>;
173 compatible = "ti,omap3-interface-clock";
174 clocks = <&core_l3_ck>;
175 ti,bit-shift = <3>;
176 reg = <0x0210>;
177 };
178
179 vlynq_gate_fck: vlynq_gate_fck {
180 #clock-cells = <0>;
181 compatible = "ti,composite-gate-clock";
182 clocks = <&core_ck>;
183 ti,bit-shift = <3>;
184 reg = <0x0200>;
185 };
186
187 core_d18_ck: core_d18_ck {
188 #clock-cells = <0>;
189 compatible = "fixed-factor-clock";
190 clocks = <&core_ck>;
191 clock-mult = <1>;
192 clock-div = <18>;
193 };
194
195 vlynq_mux_fck: vlynq_mux_fck {
196 #clock-cells = <0>;
197 compatible = "ti,composite-mux-clock";
198 clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>;
199 ti,bit-shift = <15>;
200 reg = <0x0240>;
201 };
202
203 vlynq_fck: vlynq_fck {
204 #clock-cells = <0>;
205 compatible = "ti,composite-clock";
206 clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>;
207 };
208};
209
210&prcm_clockdomains {
211 gfx_clkdm: gfx_clkdm {
212 compatible = "ti,clockdomain";
213 clocks = <&gfx_ick>;
214 };
215
216 core_l3_clkdm: core_l3_clkdm {
217 compatible = "ti,clockdomain";
218 clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>;
219 };
220
221 wkup_clkdm: wkup_clkdm {
222 compatible = "ti,clockdomain";
223 clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
224 <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
225 <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>;
226 };
227
228 iva1_clkdm: iva1_clkdm {
229 compatible = "ti,clockdomain";
230 clocks = <&iva1_mpu_int_ifck>;
231 };
232
233 dss_clkdm: dss_clkdm {
234 compatible = "ti,clockdomain";
235 clocks = <&dss_ick>, <&dss_54m_fck>;
236 };
237
238 core_l4_clkdm: core_l4_clkdm {
239 compatible = "ti,clockdomain";
240 clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
241 <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
242 <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
243 <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>,
244 <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
245 <&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>,
246 <&uart3_ick>, <&uart3_fck>, <&cam_ick>,
247 <&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>,
248 <&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>,
249 <&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>,
250 <&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>,
251 <&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>,
252 <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
253 <&pka_ick>;
254 };
255};
256
257&func_96m_ck {
258 compatible = "fixed-factor-clock";
259 clocks = <&apll96_ck>;
260 clock-mult = <1>;
261 clock-div = <1>;
262};
263
264&dsp_div_fck {
265 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
266};
267
268&ssi_ssr_sst_div_fck {
269 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
270};
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index 85b1fb014c43..db0f1293579c 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -14,6 +14,32 @@
14 compatible = "ti,omap2420", "ti,omap2"; 14 compatible = "ti,omap2420", "ti,omap2";
15 15
16 ocp { 16 ocp {
17 prcm: prcm@48008000 {
18 compatible = "ti,omap2-prcm";
19 reg = <0x48008000 0x1000>;
20
21 prcm_clocks: clocks {
22 #address-cells = <1>;
23 #size-cells = <0>;
24 };
25
26 prcm_clockdomains: clockdomains {
27 };
28 };
29
30 scrm: scrm@48000000 {
31 compatible = "ti,omap2-scrm";
32 reg = <0x48000000 0x1000>;
33
34 scrm_clocks: clocks {
35 #address-cells = <1>;
36 #size-cells = <0>;
37 };
38
39 scrm_clockdomains: clockdomains {
40 };
41 };
42
17 counter32k: counter@48004000 { 43 counter32k: counter@48004000 {
18 compatible = "ti,omap-counter32k"; 44 compatible = "ti,omap-counter32k";
19 reg = <0x48004000 0x20>; 45 reg = <0x48004000 0x20>;
diff --git a/arch/arm/boot/dts/omap2430-clocks.dtsi b/arch/arm/boot/dts/omap2430-clocks.dtsi
new file mode 100644
index 000000000000..805f75df1cf2
--- /dev/null
+++ b/arch/arm/boot/dts/omap2430-clocks.dtsi
@@ -0,0 +1,344 @@
1/*
2 * Device Tree Source for OMAP2430 clock data
3 *
4 * Copyright (C) 2014 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11&scrm_clocks {
12 mcbsp3_mux_fck: mcbsp3_mux_fck {
13 #clock-cells = <0>;
14 compatible = "ti,composite-mux-clock";
15 clocks = <&func_96m_ck>, <&mcbsp_clks>;
16 reg = <0x02e8>;
17 };
18
19 mcbsp3_fck: mcbsp3_fck {
20 #clock-cells = <0>;
21 compatible = "ti,composite-clock";
22 clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
23 };
24
25 mcbsp4_mux_fck: mcbsp4_mux_fck {
26 #clock-cells = <0>;
27 compatible = "ti,composite-mux-clock";
28 clocks = <&func_96m_ck>, <&mcbsp_clks>;
29 ti,bit-shift = <2>;
30 reg = <0x02e8>;
31 };
32
33 mcbsp4_fck: mcbsp4_fck {
34 #clock-cells = <0>;
35 compatible = "ti,composite-clock";
36 clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
37 };
38
39 mcbsp5_mux_fck: mcbsp5_mux_fck {
40 #clock-cells = <0>;
41 compatible = "ti,composite-mux-clock";
42 clocks = <&func_96m_ck>, <&mcbsp_clks>;
43 ti,bit-shift = <4>;
44 reg = <0x02e8>;
45 };
46
47 mcbsp5_fck: mcbsp5_fck {
48 #clock-cells = <0>;
49 compatible = "ti,composite-clock";
50 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
51 };
52};
53
54&prcm_clocks {
55 iva2_1_gate_ick: iva2_1_gate_ick {
56 #clock-cells = <0>;
57 compatible = "ti,composite-gate-clock";
58 clocks = <&dsp_fck>;
59 ti,bit-shift = <0>;
60 reg = <0x0800>;
61 };
62
63 iva2_1_div_ick: iva2_1_div_ick {
64 #clock-cells = <0>;
65 compatible = "ti,composite-divider-clock";
66 clocks = <&dsp_fck>;
67 ti,bit-shift = <5>;
68 ti,max-div = <3>;
69 reg = <0x0840>;
70 ti,index-starts-at-one;
71 };
72
73 iva2_1_ick: iva2_1_ick {
74 #clock-cells = <0>;
75 compatible = "ti,composite-clock";
76 clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
77 };
78
79 mdm_gate_ick: mdm_gate_ick {
80 #clock-cells = <0>;
81 compatible = "ti,composite-interface-clock";
82 clocks = <&core_ck>;
83 ti,bit-shift = <0>;
84 reg = <0x0c10>;
85 };
86
87 mdm_div_ick: mdm_div_ick {
88 #clock-cells = <0>;
89 compatible = "ti,composite-divider-clock";
90 clocks = <&core_ck>;
91 reg = <0x0c40>;
92 ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>;
93 };
94
95 mdm_ick: mdm_ick {
96 #clock-cells = <0>;
97 compatible = "ti,composite-clock";
98 clocks = <&mdm_gate_ick>, <&mdm_div_ick>;
99 };
100
101 mdm_osc_ck: mdm_osc_ck {
102 #clock-cells = <0>;
103 compatible = "ti,omap3-interface-clock";
104 clocks = <&osc_ck>;
105 ti,bit-shift = <1>;
106 reg = <0x0c00>;
107 };
108
109 mcbsp3_ick: mcbsp3_ick {
110 #clock-cells = <0>;
111 compatible = "ti,omap3-interface-clock";
112 clocks = <&l4_ck>;
113 ti,bit-shift = <3>;
114 reg = <0x0214>;
115 };
116
117 mcbsp3_gate_fck: mcbsp3_gate_fck {
118 #clock-cells = <0>;
119 compatible = "ti,composite-gate-clock";
120 clocks = <&mcbsp_clks>;
121 ti,bit-shift = <3>;
122 reg = <0x0204>;
123 };
124
125 mcbsp4_ick: mcbsp4_ick {
126 #clock-cells = <0>;
127 compatible = "ti,omap3-interface-clock";
128 clocks = <&l4_ck>;
129 ti,bit-shift = <4>;
130 reg = <0x0214>;
131 };
132
133 mcbsp4_gate_fck: mcbsp4_gate_fck {
134 #clock-cells = <0>;
135 compatible = "ti,composite-gate-clock";
136 clocks = <&mcbsp_clks>;
137 ti,bit-shift = <4>;
138 reg = <0x0204>;
139 };
140
141 mcbsp5_ick: mcbsp5_ick {
142 #clock-cells = <0>;
143 compatible = "ti,omap3-interface-clock";
144 clocks = <&l4_ck>;
145 ti,bit-shift = <5>;
146 reg = <0x0214>;
147 };
148
149 mcbsp5_gate_fck: mcbsp5_gate_fck {
150 #clock-cells = <0>;
151 compatible = "ti,composite-gate-clock";
152 clocks = <&mcbsp_clks>;
153 ti,bit-shift = <5>;
154 reg = <0x0204>;
155 };
156
157 mcspi3_ick: mcspi3_ick {
158 #clock-cells = <0>;
159 compatible = "ti,omap3-interface-clock";
160 clocks = <&l4_ck>;
161 ti,bit-shift = <9>;
162 reg = <0x0214>;
163 };
164
165 mcspi3_fck: mcspi3_fck {
166 #clock-cells = <0>;
167 compatible = "ti,wait-gate-clock";
168 clocks = <&func_48m_ck>;
169 ti,bit-shift = <9>;
170 reg = <0x0204>;
171 };
172
173 icr_ick: icr_ick {
174 #clock-cells = <0>;
175 compatible = "ti,omap3-interface-clock";
176 clocks = <&sys_ck>;
177 ti,bit-shift = <6>;
178 reg = <0x0410>;
179 };
180
181 i2chs1_fck: i2chs1_fck {
182 #clock-cells = <0>;
183 compatible = "ti,omap2430-interface-clock";
184 clocks = <&func_96m_ck>;
185 ti,bit-shift = <19>;
186 reg = <0x0204>;
187 };
188
189 i2chs2_fck: i2chs2_fck {
190 #clock-cells = <0>;
191 compatible = "ti,omap2430-interface-clock";
192 clocks = <&func_96m_ck>;
193 ti,bit-shift = <20>;
194 reg = <0x0204>;
195 };
196
197 usbhs_ick: usbhs_ick {
198 #clock-cells = <0>;
199 compatible = "ti,omap3-interface-clock";
200 clocks = <&core_l3_ck>;
201 ti,bit-shift = <6>;
202 reg = <0x0214>;
203 };
204
205 mmchs1_ick: mmchs1_ick {
206 #clock-cells = <0>;
207 compatible = "ti,omap3-interface-clock";
208 clocks = <&l4_ck>;
209 ti,bit-shift = <7>;
210 reg = <0x0214>;
211 };
212
213 mmchs1_fck: mmchs1_fck {
214 #clock-cells = <0>;
215 compatible = "ti,wait-gate-clock";
216 clocks = <&func_96m_ck>;
217 ti,bit-shift = <7>;
218 reg = <0x0204>;
219 };
220
221 mmchs2_ick: mmchs2_ick {
222 #clock-cells = <0>;
223 compatible = "ti,omap3-interface-clock";
224 clocks = <&l4_ck>;
225 ti,bit-shift = <8>;
226 reg = <0x0214>;
227 };
228
229 mmchs2_fck: mmchs2_fck {
230 #clock-cells = <0>;
231 compatible = "ti,wait-gate-clock";
232 clocks = <&func_96m_ck>;
233 ti,bit-shift = <8>;
234 reg = <0x0204>;
235 };
236
237 gpio5_ick: gpio5_ick {
238 #clock-cells = <0>;
239 compatible = "ti,omap3-interface-clock";
240 clocks = <&l4_ck>;
241 ti,bit-shift = <10>;
242 reg = <0x0214>;
243 };
244
245 gpio5_fck: gpio5_fck {
246 #clock-cells = <0>;
247 compatible = "ti,wait-gate-clock";
248 clocks = <&func_32k_ck>;
249 ti,bit-shift = <10>;
250 reg = <0x0204>;
251 };
252
253 mdm_intc_ick: mdm_intc_ick {
254 #clock-cells = <0>;
255 compatible = "ti,omap3-interface-clock";
256 clocks = <&l4_ck>;
257 ti,bit-shift = <11>;
258 reg = <0x0214>;
259 };
260
261 mmchsdb1_fck: mmchsdb1_fck {
262 #clock-cells = <0>;
263 compatible = "ti,wait-gate-clock";
264 clocks = <&func_32k_ck>;
265 ti,bit-shift = <16>;
266 reg = <0x0204>;
267 };
268
269 mmchsdb2_fck: mmchsdb2_fck {
270 #clock-cells = <0>;
271 compatible = "ti,wait-gate-clock";
272 clocks = <&func_32k_ck>;
273 ti,bit-shift = <17>;
274 reg = <0x0204>;
275 };
276};
277
278&prcm_clockdomains {
279 gfx_clkdm: gfx_clkdm {
280 compatible = "ti,clockdomain";
281 clocks = <&gfx_ick>;
282 };
283
284 core_l3_clkdm: core_l3_clkdm {
285 compatible = "ti,clockdomain";
286 clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>;
287 };
288
289 wkup_clkdm: wkup_clkdm {
290 compatible = "ti,clockdomain";
291 clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
292 <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
293 <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>,
294 <&icr_ick>;
295 };
296
297 dss_clkdm: dss_clkdm {
298 compatible = "ti,clockdomain";
299 clocks = <&dss_ick>, <&dss_54m_fck>;
300 };
301
302 core_l4_clkdm: core_l4_clkdm {
303 compatible = "ti,clockdomain";
304 clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
305 <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
306 <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
307 <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
308 <&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>,
309 <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
310 <&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>,
311 <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>,
312 <&uart3_fck>, <&cam_ick>, <&mailboxes_ick>,
313 <&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>,
314 <&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>,
315 <&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>,
316 <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
317 <&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>,
318 <&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>,
319 <&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>,
320 <&mmchsdb2_fck>;
321 };
322
323 mdm_clkdm: mdm_clkdm {
324 compatible = "ti,clockdomain";
325 clocks = <&mdm_osc_ck>;
326 };
327};
328
329&func_96m_ck {
330 compatible = "ti,mux-clock";
331 clocks = <&apll96_ck>, <&alt_ck>;
332 ti,bit-shift = <4>;
333 reg = <0x0540>;
334};
335
336&dsp_div_fck {
337 ti,max-div = <4>;
338 ti,index-starts-at-one;
339};
340
341&ssi_ssr_sst_div_fck {
342 ti,max-div = <5>;
343 ti,index-starts-at-one;
344};
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index d09697dab55e..8ff8d15184ad 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -14,6 +14,32 @@
14 compatible = "ti,omap2430", "ti,omap2"; 14 compatible = "ti,omap2430", "ti,omap2";
15 15
16 ocp { 16 ocp {
17 prcm: prcm@49006000 {
18 compatible = "ti,omap2-prcm";
19 reg = <0x49006000 0x1000>;
20
21 prcm_clocks: clocks {
22 #address-cells = <1>;
23 #size-cells = <0>;
24 };
25
26 prcm_clockdomains: clockdomains {
27 };
28 };
29
30 scrm: scrm@49002000 {
31 compatible = "ti,omap2-scrm";
32 reg = <0x49002000 0x1000>;
33
34 scrm_clocks: clocks {
35 #address-cells = <1>;
36 #size-cells = <0>;
37 };
38
39 scrm_clockdomains: clockdomains {
40 };
41 };
42
17 counter32k: counter@49020000 { 43 counter32k: counter@49020000 {
18 compatible = "ti,omap-counter32k"; 44 compatible = "ti,omap-counter32k";
19 reg = <0x49020000 0x20>; 45 reg = <0x49020000 0x20>;
diff --git a/arch/arm/boot/dts/omap24xx-clocks.dtsi b/arch/arm/boot/dts/omap24xx-clocks.dtsi
new file mode 100644
index 000000000000..a1365ca926eb
--- /dev/null
+++ b/arch/arm/boot/dts/omap24xx-clocks.dtsi
@@ -0,0 +1,1244 @@
1/*
2 * Device Tree Source for OMAP24xx clock data
3 *
4 * Copyright (C) 2014 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10&scrm_clocks {
11 mcbsp1_mux_fck: mcbsp1_mux_fck {
12 #clock-cells = <0>;
13 compatible = "ti,composite-mux-clock";
14 clocks = <&func_96m_ck>, <&mcbsp_clks>;
15 ti,bit-shift = <2>;
16 reg = <0x0274>;
17 };
18
19 mcbsp1_fck: mcbsp1_fck {
20 #clock-cells = <0>;
21 compatible = "ti,composite-clock";
22 clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
23 };
24
25 mcbsp2_mux_fck: mcbsp2_mux_fck {
26 #clock-cells = <0>;
27 compatible = "ti,composite-mux-clock";
28 clocks = <&func_96m_ck>, <&mcbsp_clks>;
29 ti,bit-shift = <6>;
30 reg = <0x0274>;
31 };
32
33 mcbsp2_fck: mcbsp2_fck {
34 #clock-cells = <0>;
35 compatible = "ti,composite-clock";
36 clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
37 };
38};
39
40&prcm_clocks {
41 func_32k_ck: func_32k_ck {
42 #clock-cells = <0>;
43 compatible = "fixed-clock";
44 clock-frequency = <32768>;
45 };
46
47 secure_32k_ck: secure_32k_ck {
48 #clock-cells = <0>;
49 compatible = "fixed-clock";
50 clock-frequency = <32768>;
51 };
52
53 virt_12m_ck: virt_12m_ck {
54 #clock-cells = <0>;
55 compatible = "fixed-clock";
56 clock-frequency = <12000000>;
57 };
58
59 virt_13m_ck: virt_13m_ck {
60 #clock-cells = <0>;
61 compatible = "fixed-clock";
62 clock-frequency = <13000000>;
63 };
64
65 virt_19200000_ck: virt_19200000_ck {
66 #clock-cells = <0>;
67 compatible = "fixed-clock";
68 clock-frequency = <19200000>;
69 };
70
71 virt_26m_ck: virt_26m_ck {
72 #clock-cells = <0>;
73 compatible = "fixed-clock";
74 clock-frequency = <26000000>;
75 };
76
77 aplls_clkin_ck: aplls_clkin_ck {
78 #clock-cells = <0>;
79 compatible = "ti,mux-clock";
80 clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>;
81 ti,bit-shift = <23>;
82 reg = <0x0540>;
83 };
84
85 aplls_clkin_x2_ck: aplls_clkin_x2_ck {
86 #clock-cells = <0>;
87 compatible = "fixed-factor-clock";
88 clocks = <&aplls_clkin_ck>;
89 clock-mult = <2>;
90 clock-div = <1>;
91 };
92
93 osc_ck: osc_ck {
94 #clock-cells = <0>;
95 compatible = "ti,mux-clock";
96 clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>;
97 ti,bit-shift = <6>;
98 reg = <0x0060>;
99 ti,index-starts-at-one;
100 };
101
102 sys_ck: sys_ck {
103 #clock-cells = <0>;
104 compatible = "ti,divider-clock";
105 clocks = <&osc_ck>;
106 ti,bit-shift = <6>;
107 ti,max-div = <3>;
108 reg = <0x0060>;
109 ti,index-starts-at-one;
110 };
111
112 alt_ck: alt_ck {
113 #clock-cells = <0>;
114 compatible = "fixed-clock";
115 clock-frequency = <54000000>;
116 };
117
118 mcbsp_clks: mcbsp_clks {
119 #clock-cells = <0>;
120 compatible = "fixed-clock";
121 clock-frequency = <0x0>;
122 };
123
124 dpll_ck: dpll_ck {
125 #clock-cells = <0>;
126 compatible = "ti,omap2-dpll-core-clock";
127 clocks = <&sys_ck>, <&sys_ck>;
128 reg = <0x0500>, <0x0540>;
129 };
130
131 apll96_ck: apll96_ck {
132 #clock-cells = <0>;
133 compatible = "ti,omap2-apll-clock";
134 clocks = <&sys_ck>;
135 ti,bit-shift = <2>;
136 ti,idlest-shift = <8>;
137 ti,clock-frequency = <96000000>;
138 reg = <0x0500>, <0x0530>, <0x0520>;
139 };
140
141 apll54_ck: apll54_ck {
142 #clock-cells = <0>;
143 compatible = "ti,omap2-apll-clock";
144 clocks = <&sys_ck>;
145 ti,bit-shift = <6>;
146 ti,idlest-shift = <9>;
147 ti,clock-frequency = <54000000>;
148 reg = <0x0500>, <0x0530>, <0x0520>;
149 };
150
151 func_54m_ck: func_54m_ck {
152 #clock-cells = <0>;
153 compatible = "ti,mux-clock";
154 clocks = <&apll54_ck>, <&alt_ck>;
155 ti,bit-shift = <5>;
156 reg = <0x0540>;
157 };
158
159 core_ck: core_ck {
160 #clock-cells = <0>;
161 compatible = "fixed-factor-clock";
162 clocks = <&dpll_ck>;
163 clock-mult = <1>;
164 clock-div = <1>;
165 };
166
167 func_96m_ck: func_96m_ck {
168 #clock-cells = <0>;
169 };
170
171 apll96_d2_ck: apll96_d2_ck {
172 #clock-cells = <0>;
173 compatible = "fixed-factor-clock";
174 clocks = <&apll96_ck>;
175 clock-mult = <1>;
176 clock-div = <2>;
177 };
178
179 func_48m_ck: func_48m_ck {
180 #clock-cells = <0>;
181 compatible = "ti,mux-clock";
182 clocks = <&apll96_d2_ck>, <&alt_ck>;
183 ti,bit-shift = <3>;
184 reg = <0x0540>;
185 };
186
187 func_12m_ck: func_12m_ck {
188 #clock-cells = <0>;
189 compatible = "fixed-factor-clock";
190 clocks = <&func_48m_ck>;
191 clock-mult = <1>;
192 clock-div = <4>;
193 };
194
195 sys_clkout_src_gate: sys_clkout_src_gate {
196 #clock-cells = <0>;
197 compatible = "ti,composite-no-wait-gate-clock";
198 clocks = <&core_ck>;
199 ti,bit-shift = <7>;
200 reg = <0x0070>;
201 };
202
203 sys_clkout_src_mux: sys_clkout_src_mux {
204 #clock-cells = <0>;
205 compatible = "ti,composite-mux-clock";
206 clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
207 reg = <0x0070>;
208 };
209
210 sys_clkout_src: sys_clkout_src {
211 #clock-cells = <0>;
212 compatible = "ti,composite-clock";
213 clocks = <&sys_clkout_src_gate>, <&sys_clkout_src_mux>;
214 };
215
216 sys_clkout: sys_clkout {
217 #clock-cells = <0>;
218 compatible = "ti,divider-clock";
219 clocks = <&sys_clkout_src>;
220 ti,bit-shift = <3>;
221 ti,max-div = <64>;
222 reg = <0x0070>;
223 ti,index-power-of-two;
224 };
225
226 emul_ck: emul_ck {
227 #clock-cells = <0>;
228 compatible = "ti,gate-clock";
229 clocks = <&func_54m_ck>;
230 ti,bit-shift = <0>;
231 reg = <0x0078>;
232 };
233
234 mpu_ck: mpu_ck {
235 #clock-cells = <0>;
236 compatible = "ti,divider-clock";
237 clocks = <&core_ck>;
238 ti,max-div = <31>;
239 reg = <0x0140>;
240 ti,index-starts-at-one;
241 };
242
243 dsp_gate_fck: dsp_gate_fck {
244 #clock-cells = <0>;
245 compatible = "ti,composite-gate-clock";
246 clocks = <&core_ck>;
247 ti,bit-shift = <0>;
248 reg = <0x0800>;
249 };
250
251 dsp_div_fck: dsp_div_fck {
252 #clock-cells = <0>;
253 compatible = "ti,composite-divider-clock";
254 clocks = <&core_ck>;
255 reg = <0x0840>;
256 };
257
258 dsp_fck: dsp_fck {
259 #clock-cells = <0>;
260 compatible = "ti,composite-clock";
261 clocks = <&dsp_gate_fck>, <&dsp_div_fck>;
262 };
263
264 core_l3_ck: core_l3_ck {
265 #clock-cells = <0>;
266 compatible = "ti,divider-clock";
267 clocks = <&core_ck>;
268 ti,max-div = <31>;
269 reg = <0x0240>;
270 ti,index-starts-at-one;
271 };
272
273 gfx_3d_gate_fck: gfx_3d_gate_fck {
274 #clock-cells = <0>;
275 compatible = "ti,composite-gate-clock";
276 clocks = <&core_l3_ck>;
277 ti,bit-shift = <2>;
278 reg = <0x0300>;
279 };
280
281 gfx_3d_div_fck: gfx_3d_div_fck {
282 #clock-cells = <0>;
283 compatible = "ti,composite-divider-clock";
284 clocks = <&core_l3_ck>;
285 ti,max-div = <4>;
286 reg = <0x0340>;
287 ti,index-starts-at-one;
288 };
289
290 gfx_3d_fck: gfx_3d_fck {
291 #clock-cells = <0>;
292 compatible = "ti,composite-clock";
293 clocks = <&gfx_3d_gate_fck>, <&gfx_3d_div_fck>;
294 };
295
296 gfx_2d_gate_fck: gfx_2d_gate_fck {
297 #clock-cells = <0>;
298 compatible = "ti,composite-gate-clock";
299 clocks = <&core_l3_ck>;
300 ti,bit-shift = <1>;
301 reg = <0x0300>;
302 };
303
304 gfx_2d_div_fck: gfx_2d_div_fck {
305 #clock-cells = <0>;
306 compatible = "ti,composite-divider-clock";
307 clocks = <&core_l3_ck>;
308 ti,max-div = <4>;
309 reg = <0x0340>;
310 ti,index-starts-at-one;
311 };
312
313 gfx_2d_fck: gfx_2d_fck {
314 #clock-cells = <0>;
315 compatible = "ti,composite-clock";
316 clocks = <&gfx_2d_gate_fck>, <&gfx_2d_div_fck>;
317 };
318
319 gfx_ick: gfx_ick {
320 #clock-cells = <0>;
321 compatible = "ti,wait-gate-clock";
322 clocks = <&core_l3_ck>;
323 ti,bit-shift = <0>;
324 reg = <0x0310>;
325 };
326
327 l4_ck: l4_ck {
328 #clock-cells = <0>;
329 compatible = "ti,divider-clock";
330 clocks = <&core_l3_ck>;
331 ti,bit-shift = <5>;
332 ti,max-div = <3>;
333 reg = <0x0240>;
334 ti,index-starts-at-one;
335 };
336
337 dss_ick: dss_ick {
338 #clock-cells = <0>;
339 compatible = "ti,omap3-no-wait-interface-clock";
340 clocks = <&l4_ck>;
341 ti,bit-shift = <0>;
342 reg = <0x0210>;
343 };
344
345 dss1_gate_fck: dss1_gate_fck {
346 #clock-cells = <0>;
347 compatible = "ti,composite-no-wait-gate-clock";
348 clocks = <&core_ck>;
349 ti,bit-shift = <0>;
350 reg = <0x0200>;
351 };
352
353 core_d2_ck: core_d2_ck {
354 #clock-cells = <0>;
355 compatible = "fixed-factor-clock";
356 clocks = <&core_ck>;
357 clock-mult = <1>;
358 clock-div = <2>;
359 };
360
361 core_d3_ck: core_d3_ck {
362 #clock-cells = <0>;
363 compatible = "fixed-factor-clock";
364 clocks = <&core_ck>;
365 clock-mult = <1>;
366 clock-div = <3>;
367 };
368
369 core_d4_ck: core_d4_ck {
370 #clock-cells = <0>;
371 compatible = "fixed-factor-clock";
372 clocks = <&core_ck>;
373 clock-mult = <1>;
374 clock-div = <4>;
375 };
376
377 core_d5_ck: core_d5_ck {
378 #clock-cells = <0>;
379 compatible = "fixed-factor-clock";
380 clocks = <&core_ck>;
381 clock-mult = <1>;
382 clock-div = <5>;
383 };
384
385 core_d6_ck: core_d6_ck {
386 #clock-cells = <0>;
387 compatible = "fixed-factor-clock";
388 clocks = <&core_ck>;
389 clock-mult = <1>;
390 clock-div = <6>;
391 };
392
393 dummy_ck: dummy_ck {
394 #clock-cells = <0>;
395 compatible = "fixed-clock";
396 clock-frequency = <0>;
397 };
398
399 core_d8_ck: core_d8_ck {
400 #clock-cells = <0>;
401 compatible = "fixed-factor-clock";
402 clocks = <&core_ck>;
403 clock-mult = <1>;
404 clock-div = <8>;
405 };
406
407 core_d9_ck: core_d9_ck {
408 #clock-cells = <0>;
409 compatible = "fixed-factor-clock";
410 clocks = <&core_ck>;
411 clock-mult = <1>;
412 clock-div = <9>;
413 };
414
415 core_d12_ck: core_d12_ck {
416 #clock-cells = <0>;
417 compatible = "fixed-factor-clock";
418 clocks = <&core_ck>;
419 clock-mult = <1>;
420 clock-div = <12>;
421 };
422
423 core_d16_ck: core_d16_ck {
424 #clock-cells = <0>;
425 compatible = "fixed-factor-clock";
426 clocks = <&core_ck>;
427 clock-mult = <1>;
428 clock-div = <16>;
429 };
430
431 dss1_mux_fck: dss1_mux_fck {
432 #clock-cells = <0>;
433 compatible = "ti,composite-mux-clock";
434 clocks = <&sys_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d5_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>;
435 ti,bit-shift = <8>;
436 reg = <0x0240>;
437 };
438
439 dss1_fck: dss1_fck {
440 #clock-cells = <0>;
441 compatible = "ti,composite-clock";
442 clocks = <&dss1_gate_fck>, <&dss1_mux_fck>;
443 };
444
445 dss2_gate_fck: dss2_gate_fck {
446 #clock-cells = <0>;
447 compatible = "ti,composite-no-wait-gate-clock";
448 clocks = <&func_48m_ck>;
449 ti,bit-shift = <1>;
450 reg = <0x0200>;
451 };
452
453 dss2_mux_fck: dss2_mux_fck {
454 #clock-cells = <0>;
455 compatible = "ti,composite-mux-clock";
456 clocks = <&sys_ck>, <&func_48m_ck>;
457 ti,bit-shift = <13>;
458 reg = <0x0240>;
459 };
460
461 dss2_fck: dss2_fck {
462 #clock-cells = <0>;
463 compatible = "ti,composite-clock";
464 clocks = <&dss2_gate_fck>, <&dss2_mux_fck>;
465 };
466
467 dss_54m_fck: dss_54m_fck {
468 #clock-cells = <0>;
469 compatible = "ti,wait-gate-clock";
470 clocks = <&func_54m_ck>;
471 ti,bit-shift = <2>;
472 reg = <0x0200>;
473 };
474
475 ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck {
476 #clock-cells = <0>;
477 compatible = "ti,composite-gate-clock";
478 clocks = <&core_ck>;
479 ti,bit-shift = <1>;
480 reg = <0x0204>;
481 };
482
483 ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck {
484 #clock-cells = <0>;
485 compatible = "ti,composite-divider-clock";
486 clocks = <&core_ck>;
487 ti,bit-shift = <20>;
488 reg = <0x0240>;
489 };
490
491 ssi_ssr_sst_fck: ssi_ssr_sst_fck {
492 #clock-cells = <0>;
493 compatible = "ti,composite-clock";
494 clocks = <&ssi_ssr_sst_gate_fck>, <&ssi_ssr_sst_div_fck>;
495 };
496
497 usb_l4_gate_ick: usb_l4_gate_ick {
498 #clock-cells = <0>;
499 compatible = "ti,composite-interface-clock";
500 clocks = <&core_l3_ck>;
501 ti,bit-shift = <0>;
502 reg = <0x0214>;
503 };
504
505 usb_l4_div_ick: usb_l4_div_ick {
506 #clock-cells = <0>;
507 compatible = "ti,composite-divider-clock";
508 clocks = <&core_l3_ck>;
509 ti,bit-shift = <25>;
510 reg = <0x0240>;
511 ti,dividers = <0>, <1>, <2>, <0>, <4>;
512 };
513
514 usb_l4_ick: usb_l4_ick {
515 #clock-cells = <0>;
516 compatible = "ti,composite-clock";
517 clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
518 };
519
520 ssi_l4_ick: ssi_l4_ick {
521 #clock-cells = <0>;
522 compatible = "ti,omap3-interface-clock";
523 clocks = <&l4_ck>;
524 ti,bit-shift = <1>;
525 reg = <0x0214>;
526 };
527
528 gpt1_ick: gpt1_ick {
529 #clock-cells = <0>;
530 compatible = "ti,omap3-interface-clock";
531 clocks = <&sys_ck>;
532 ti,bit-shift = <0>;
533 reg = <0x0410>;
534 };
535
536 gpt1_gate_fck: gpt1_gate_fck {
537 #clock-cells = <0>;
538 compatible = "ti,composite-gate-clock";
539 clocks = <&func_32k_ck>;
540 ti,bit-shift = <0>;
541 reg = <0x0400>;
542 };
543
544 gpt1_mux_fck: gpt1_mux_fck {
545 #clock-cells = <0>;
546 compatible = "ti,composite-mux-clock";
547 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
548 reg = <0x0440>;
549 };
550
551 gpt1_fck: gpt1_fck {
552 #clock-cells = <0>;
553 compatible = "ti,composite-clock";
554 clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
555 };
556
557 gpt2_ick: gpt2_ick {
558 #clock-cells = <0>;
559 compatible = "ti,omap3-interface-clock";
560 clocks = <&l4_ck>;
561 ti,bit-shift = <4>;
562 reg = <0x0210>;
563 };
564
565 gpt2_gate_fck: gpt2_gate_fck {
566 #clock-cells = <0>;
567 compatible = "ti,composite-gate-clock";
568 clocks = <&func_32k_ck>;
569 ti,bit-shift = <4>;
570 reg = <0x0200>;
571 };
572
573 gpt2_mux_fck: gpt2_mux_fck {
574 #clock-cells = <0>;
575 compatible = "ti,composite-mux-clock";
576 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
577 ti,bit-shift = <2>;
578 reg = <0x0244>;
579 };
580
581 gpt2_fck: gpt2_fck {
582 #clock-cells = <0>;
583 compatible = "ti,composite-clock";
584 clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
585 };
586
587 gpt3_ick: gpt3_ick {
588 #clock-cells = <0>;
589 compatible = "ti,omap3-interface-clock";
590 clocks = <&l4_ck>;
591 ti,bit-shift = <5>;
592 reg = <0x0210>;
593 };
594
595 gpt3_gate_fck: gpt3_gate_fck {
596 #clock-cells = <0>;
597 compatible = "ti,composite-gate-clock";
598 clocks = <&func_32k_ck>;
599 ti,bit-shift = <5>;
600 reg = <0x0200>;
601 };
602
603 gpt3_mux_fck: gpt3_mux_fck {
604 #clock-cells = <0>;
605 compatible = "ti,composite-mux-clock";
606 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
607 ti,bit-shift = <4>;
608 reg = <0x0244>;
609 };
610
611 gpt3_fck: gpt3_fck {
612 #clock-cells = <0>;
613 compatible = "ti,composite-clock";
614 clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
615 };
616
617 gpt4_ick: gpt4_ick {
618 #clock-cells = <0>;
619 compatible = "ti,omap3-interface-clock";
620 clocks = <&l4_ck>;
621 ti,bit-shift = <6>;
622 reg = <0x0210>;
623 };
624
625 gpt4_gate_fck: gpt4_gate_fck {
626 #clock-cells = <0>;
627 compatible = "ti,composite-gate-clock";
628 clocks = <&func_32k_ck>;
629 ti,bit-shift = <6>;
630 reg = <0x0200>;
631 };
632
633 gpt4_mux_fck: gpt4_mux_fck {
634 #clock-cells = <0>;
635 compatible = "ti,composite-mux-clock";
636 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
637 ti,bit-shift = <6>;
638 reg = <0x0244>;
639 };
640
641 gpt4_fck: gpt4_fck {
642 #clock-cells = <0>;
643 compatible = "ti,composite-clock";
644 clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
645 };
646
647 gpt5_ick: gpt5_ick {
648 #clock-cells = <0>;
649 compatible = "ti,omap3-interface-clock";
650 clocks = <&l4_ck>;
651 ti,bit-shift = <7>;
652 reg = <0x0210>;
653 };
654
655 gpt5_gate_fck: gpt5_gate_fck {
656 #clock-cells = <0>;
657 compatible = "ti,composite-gate-clock";
658 clocks = <&func_32k_ck>;
659 ti,bit-shift = <7>;
660 reg = <0x0200>;
661 };
662
663 gpt5_mux_fck: gpt5_mux_fck {
664 #clock-cells = <0>;
665 compatible = "ti,composite-mux-clock";
666 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
667 ti,bit-shift = <8>;
668 reg = <0x0244>;
669 };
670
671 gpt5_fck: gpt5_fck {
672 #clock-cells = <0>;
673 compatible = "ti,composite-clock";
674 clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
675 };
676
677 gpt6_ick: gpt6_ick {
678 #clock-cells = <0>;
679 compatible = "ti,omap3-interface-clock";
680 clocks = <&l4_ck>;
681 ti,bit-shift = <8>;
682 reg = <0x0210>;
683 };
684
685 gpt6_gate_fck: gpt6_gate_fck {
686 #clock-cells = <0>;
687 compatible = "ti,composite-gate-clock";
688 clocks = <&func_32k_ck>;
689 ti,bit-shift = <8>;
690 reg = <0x0200>;
691 };
692
693 gpt6_mux_fck: gpt6_mux_fck {
694 #clock-cells = <0>;
695 compatible = "ti,composite-mux-clock";
696 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
697 ti,bit-shift = <10>;
698 reg = <0x0244>;
699 };
700
701 gpt6_fck: gpt6_fck {
702 #clock-cells = <0>;
703 compatible = "ti,composite-clock";
704 clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
705 };
706
707 gpt7_ick: gpt7_ick {
708 #clock-cells = <0>;
709 compatible = "ti,omap3-interface-clock";
710 clocks = <&l4_ck>;
711 ti,bit-shift = <9>;
712 reg = <0x0210>;
713 };
714
715 gpt7_gate_fck: gpt7_gate_fck {
716 #clock-cells = <0>;
717 compatible = "ti,composite-gate-clock";
718 clocks = <&func_32k_ck>;
719 ti,bit-shift = <9>;
720 reg = <0x0200>;
721 };
722
723 gpt7_mux_fck: gpt7_mux_fck {
724 #clock-cells = <0>;
725 compatible = "ti,composite-mux-clock";
726 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
727 ti,bit-shift = <12>;
728 reg = <0x0244>;
729 };
730
731 gpt7_fck: gpt7_fck {
732 #clock-cells = <0>;
733 compatible = "ti,composite-clock";
734 clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
735 };
736
737 gpt8_ick: gpt8_ick {
738 #clock-cells = <0>;
739 compatible = "ti,omap3-interface-clock";
740 clocks = <&l4_ck>;
741 ti,bit-shift = <10>;
742 reg = <0x0210>;
743 };
744
745 gpt8_gate_fck: gpt8_gate_fck {
746 #clock-cells = <0>;
747 compatible = "ti,composite-gate-clock";
748 clocks = <&func_32k_ck>;
749 ti,bit-shift = <10>;
750 reg = <0x0200>;
751 };
752
753 gpt8_mux_fck: gpt8_mux_fck {
754 #clock-cells = <0>;
755 compatible = "ti,composite-mux-clock";
756 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
757 ti,bit-shift = <14>;
758 reg = <0x0244>;
759 };
760
761 gpt8_fck: gpt8_fck {
762 #clock-cells = <0>;
763 compatible = "ti,composite-clock";
764 clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
765 };
766
767 gpt9_ick: gpt9_ick {
768 #clock-cells = <0>;
769 compatible = "ti,omap3-interface-clock";
770 clocks = <&l4_ck>;
771 ti,bit-shift = <11>;
772 reg = <0x0210>;
773 };
774
775 gpt9_gate_fck: gpt9_gate_fck {
776 #clock-cells = <0>;
777 compatible = "ti,composite-gate-clock";
778 clocks = <&func_32k_ck>;
779 ti,bit-shift = <11>;
780 reg = <0x0200>;
781 };
782
783 gpt9_mux_fck: gpt9_mux_fck {
784 #clock-cells = <0>;
785 compatible = "ti,composite-mux-clock";
786 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
787 ti,bit-shift = <16>;
788 reg = <0x0244>;
789 };
790
791 gpt9_fck: gpt9_fck {
792 #clock-cells = <0>;
793 compatible = "ti,composite-clock";
794 clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
795 };
796
797 gpt10_ick: gpt10_ick {
798 #clock-cells = <0>;
799 compatible = "ti,omap3-interface-clock";
800 clocks = <&l4_ck>;
801 ti,bit-shift = <12>;
802 reg = <0x0210>;
803 };
804
805 gpt10_gate_fck: gpt10_gate_fck {
806 #clock-cells = <0>;
807 compatible = "ti,composite-gate-clock";
808 clocks = <&func_32k_ck>;
809 ti,bit-shift = <12>;
810 reg = <0x0200>;
811 };
812
813 gpt10_mux_fck: gpt10_mux_fck {
814 #clock-cells = <0>;
815 compatible = "ti,composite-mux-clock";
816 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
817 ti,bit-shift = <18>;
818 reg = <0x0244>;
819 };
820
821 gpt10_fck: gpt10_fck {
822 #clock-cells = <0>;
823 compatible = "ti,composite-clock";
824 clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
825 };
826
827 gpt11_ick: gpt11_ick {
828 #clock-cells = <0>;
829 compatible = "ti,omap3-interface-clock";
830 clocks = <&l4_ck>;
831 ti,bit-shift = <13>;
832 reg = <0x0210>;
833 };
834
835 gpt11_gate_fck: gpt11_gate_fck {
836 #clock-cells = <0>;
837 compatible = "ti,composite-gate-clock";
838 clocks = <&func_32k_ck>;
839 ti,bit-shift = <13>;
840 reg = <0x0200>;
841 };
842
843 gpt11_mux_fck: gpt11_mux_fck {
844 #clock-cells = <0>;
845 compatible = "ti,composite-mux-clock";
846 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
847 ti,bit-shift = <20>;
848 reg = <0x0244>;
849 };
850
851 gpt11_fck: gpt11_fck {
852 #clock-cells = <0>;
853 compatible = "ti,composite-clock";
854 clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
855 };
856
857 gpt12_ick: gpt12_ick {
858 #clock-cells = <0>;
859 compatible = "ti,omap3-interface-clock";
860 clocks = <&l4_ck>;
861 ti,bit-shift = <14>;
862 reg = <0x0210>;
863 };
864
865 gpt12_gate_fck: gpt12_gate_fck {
866 #clock-cells = <0>;
867 compatible = "ti,composite-gate-clock";
868 clocks = <&func_32k_ck>;
869 ti,bit-shift = <14>;
870 reg = <0x0200>;
871 };
872
873 gpt12_mux_fck: gpt12_mux_fck {
874 #clock-cells = <0>;
875 compatible = "ti,composite-mux-clock";
876 clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
877 ti,bit-shift = <22>;
878 reg = <0x0244>;
879 };
880
881 gpt12_fck: gpt12_fck {
882 #clock-cells = <0>;
883 compatible = "ti,composite-clock";
884 clocks = <&gpt12_gate_fck>, <&gpt12_mux_fck>;
885 };
886
887 mcbsp1_ick: mcbsp1_ick {
888 #clock-cells = <0>;
889 compatible = "ti,omap3-interface-clock";
890 clocks = <&l4_ck>;
891 ti,bit-shift = <15>;
892 reg = <0x0210>;
893 };
894
895 mcbsp1_gate_fck: mcbsp1_gate_fck {
896 #clock-cells = <0>;
897 compatible = "ti,composite-gate-clock";
898 clocks = <&mcbsp_clks>;
899 ti,bit-shift = <15>;
900 reg = <0x0200>;
901 };
902
903 mcbsp2_ick: mcbsp2_ick {
904 #clock-cells = <0>;
905 compatible = "ti,omap3-interface-clock";
906 clocks = <&l4_ck>;
907 ti,bit-shift = <16>;
908 reg = <0x0210>;
909 };
910
911 mcbsp2_gate_fck: mcbsp2_gate_fck {
912 #clock-cells = <0>;
913 compatible = "ti,composite-gate-clock";
914 clocks = <&mcbsp_clks>;
915 ti,bit-shift = <16>;
916 reg = <0x0200>;
917 };
918
919 mcspi1_ick: mcspi1_ick {
920 #clock-cells = <0>;
921 compatible = "ti,omap3-interface-clock";
922 clocks = <&l4_ck>;
923 ti,bit-shift = <17>;
924 reg = <0x0210>;
925 };
926
927 mcspi1_fck: mcspi1_fck {
928 #clock-cells = <0>;
929 compatible = "ti,wait-gate-clock";
930 clocks = <&func_48m_ck>;
931 ti,bit-shift = <17>;
932 reg = <0x0200>;
933 };
934
935 mcspi2_ick: mcspi2_ick {
936 #clock-cells = <0>;
937 compatible = "ti,omap3-interface-clock";
938 clocks = <&l4_ck>;
939 ti,bit-shift = <18>;
940 reg = <0x0210>;
941 };
942
943 mcspi2_fck: mcspi2_fck {
944 #clock-cells = <0>;
945 compatible = "ti,wait-gate-clock";
946 clocks = <&func_48m_ck>;
947 ti,bit-shift = <18>;
948 reg = <0x0200>;
949 };
950
951 uart1_ick: uart1_ick {
952 #clock-cells = <0>;
953 compatible = "ti,omap3-interface-clock";
954 clocks = <&l4_ck>;
955 ti,bit-shift = <21>;
956 reg = <0x0210>;
957 };
958
959 uart1_fck: uart1_fck {
960 #clock-cells = <0>;
961 compatible = "ti,wait-gate-clock";
962 clocks = <&func_48m_ck>;
963 ti,bit-shift = <21>;
964 reg = <0x0200>;
965 };
966
967 uart2_ick: uart2_ick {
968 #clock-cells = <0>;
969 compatible = "ti,omap3-interface-clock";
970 clocks = <&l4_ck>;
971 ti,bit-shift = <22>;
972 reg = <0x0210>;
973 };
974
975 uart2_fck: uart2_fck {
976 #clock-cells = <0>;
977 compatible = "ti,wait-gate-clock";
978 clocks = <&func_48m_ck>;
979 ti,bit-shift = <22>;
980 reg = <0x0200>;
981 };
982
983 uart3_ick: uart3_ick {
984 #clock-cells = <0>;
985 compatible = "ti,omap3-interface-clock";
986 clocks = <&l4_ck>;
987 ti,bit-shift = <2>;
988 reg = <0x0214>;
989 };
990
991 uart3_fck: uart3_fck {
992 #clock-cells = <0>;
993 compatible = "ti,wait-gate-clock";
994 clocks = <&func_48m_ck>;
995 ti,bit-shift = <2>;
996 reg = <0x0204>;
997 };
998
999 gpios_ick: gpios_ick {
1000 #clock-cells = <0>;
1001 compatible = "ti,omap3-interface-clock";
1002 clocks = <&sys_ck>;
1003 ti,bit-shift = <2>;
1004 reg = <0x0410>;
1005 };
1006
1007 gpios_fck: gpios_fck {
1008 #clock-cells = <0>;
1009 compatible = "ti,wait-gate-clock";
1010 clocks = <&func_32k_ck>;
1011 ti,bit-shift = <2>;
1012 reg = <0x0400>;
1013 };
1014
1015 mpu_wdt_ick: mpu_wdt_ick {
1016 #clock-cells = <0>;
1017 compatible = "ti,omap3-interface-clock";
1018 clocks = <&sys_ck>;
1019 ti,bit-shift = <3>;
1020 reg = <0x0410>;
1021 };
1022
1023 mpu_wdt_fck: mpu_wdt_fck {
1024 #clock-cells = <0>;
1025 compatible = "ti,wait-gate-clock";
1026 clocks = <&func_32k_ck>;
1027 ti,bit-shift = <3>;
1028 reg = <0x0400>;
1029 };
1030
1031 sync_32k_ick: sync_32k_ick {
1032 #clock-cells = <0>;
1033 compatible = "ti,omap3-interface-clock";
1034 clocks = <&sys_ck>;
1035 ti,bit-shift = <1>;
1036 reg = <0x0410>;
1037 };
1038
1039 wdt1_ick: wdt1_ick {
1040 #clock-cells = <0>;
1041 compatible = "ti,omap3-interface-clock";
1042 clocks = <&sys_ck>;
1043 ti,bit-shift = <4>;
1044 reg = <0x0410>;
1045 };
1046
1047 omapctrl_ick: omapctrl_ick {
1048 #clock-cells = <0>;
1049 compatible = "ti,omap3-interface-clock";
1050 clocks = <&sys_ck>;
1051 ti,bit-shift = <5>;
1052 reg = <0x0410>;
1053 };
1054
1055 cam_fck: cam_fck {
1056 #clock-cells = <0>;
1057 compatible = "ti,gate-clock";
1058 clocks = <&func_96m_ck>;
1059 ti,bit-shift = <31>;
1060 reg = <0x0200>;
1061 };
1062
1063 cam_ick: cam_ick {
1064 #clock-cells = <0>;
1065 compatible = "ti,omap3-no-wait-interface-clock";
1066 clocks = <&l4_ck>;
1067 ti,bit-shift = <31>;
1068 reg = <0x0210>;
1069 };
1070
1071 mailboxes_ick: mailboxes_ick {
1072 #clock-cells = <0>;
1073 compatible = "ti,omap3-interface-clock";
1074 clocks = <&l4_ck>;
1075 ti,bit-shift = <30>;
1076 reg = <0x0210>;
1077 };
1078
1079 wdt4_ick: wdt4_ick {
1080 #clock-cells = <0>;
1081 compatible = "ti,omap3-interface-clock";
1082 clocks = <&l4_ck>;
1083 ti,bit-shift = <29>;
1084 reg = <0x0210>;
1085 };
1086
1087 wdt4_fck: wdt4_fck {
1088 #clock-cells = <0>;
1089 compatible = "ti,wait-gate-clock";
1090 clocks = <&func_32k_ck>;
1091 ti,bit-shift = <29>;
1092 reg = <0x0200>;
1093 };
1094
1095 mspro_ick: mspro_ick {
1096 #clock-cells = <0>;
1097 compatible = "ti,omap3-interface-clock";
1098 clocks = <&l4_ck>;
1099 ti,bit-shift = <27>;
1100 reg = <0x0210>;
1101 };
1102
1103 mspro_fck: mspro_fck {
1104 #clock-cells = <0>;
1105 compatible = "ti,wait-gate-clock";
1106 clocks = <&func_96m_ck>;
1107 ti,bit-shift = <27>;
1108 reg = <0x0200>;
1109 };
1110
1111 fac_ick: fac_ick {
1112 #clock-cells = <0>;
1113 compatible = "ti,omap3-interface-clock";
1114 clocks = <&l4_ck>;
1115 ti,bit-shift = <25>;
1116 reg = <0x0210>;
1117 };
1118
1119 fac_fck: fac_fck {
1120 #clock-cells = <0>;
1121 compatible = "ti,wait-gate-clock";
1122 clocks = <&func_12m_ck>;
1123 ti,bit-shift = <25>;
1124 reg = <0x0200>;
1125 };
1126
1127 hdq_ick: hdq_ick {
1128 #clock-cells = <0>;
1129 compatible = "ti,omap3-interface-clock";
1130 clocks = <&l4_ck>;
1131 ti,bit-shift = <23>;
1132 reg = <0x0210>;
1133 };
1134
1135 hdq_fck: hdq_fck {
1136 #clock-cells = <0>;
1137 compatible = "ti,wait-gate-clock";
1138 clocks = <&func_12m_ck>;
1139 ti,bit-shift = <23>;
1140 reg = <0x0200>;
1141 };
1142
1143 i2c1_ick: i2c1_ick {
1144 #clock-cells = <0>;
1145 compatible = "ti,omap3-interface-clock";
1146 clocks = <&l4_ck>;
1147 ti,bit-shift = <19>;
1148 reg = <0x0210>;
1149 };
1150
1151 i2c2_ick: i2c2_ick {
1152 #clock-cells = <0>;
1153 compatible = "ti,omap3-interface-clock";
1154 clocks = <&l4_ck>;
1155 ti,bit-shift = <20>;
1156 reg = <0x0210>;
1157 };
1158
1159 gpmc_fck: gpmc_fck {
1160 #clock-cells = <0>;
1161 compatible = "ti,fixed-factor-clock";
1162 clocks = <&core_l3_ck>;
1163 ti,clock-div = <1>;
1164 ti,autoidle-shift = <1>;
1165 reg = <0x0238>;
1166 ti,clock-mult = <1>;
1167 };
1168
1169 sdma_fck: sdma_fck {
1170 #clock-cells = <0>;
1171 compatible = "fixed-factor-clock";
1172 clocks = <&core_l3_ck>;
1173 clock-mult = <1>;
1174 clock-div = <1>;
1175 };
1176
1177 sdma_ick: sdma_ick {
1178 #clock-cells = <0>;
1179 compatible = "ti,fixed-factor-clock";
1180 clocks = <&core_l3_ck>;
1181 ti,clock-div = <1>;
1182 ti,autoidle-shift = <0>;
1183 reg = <0x0238>;
1184 ti,clock-mult = <1>;
1185 };
1186
1187 sdrc_ick: sdrc_ick {
1188 #clock-cells = <0>;
1189 compatible = "ti,fixed-factor-clock";
1190 clocks = <&core_l3_ck>;
1191 ti,clock-div = <1>;
1192 ti,autoidle-shift = <2>;
1193 reg = <0x0238>;
1194 ti,clock-mult = <1>;
1195 };
1196
1197 des_ick: des_ick {
1198 #clock-cells = <0>;
1199 compatible = "ti,omap3-interface-clock";
1200 clocks = <&l4_ck>;
1201 ti,bit-shift = <0>;
1202 reg = <0x021c>;
1203 };
1204
1205 sha_ick: sha_ick {
1206 #clock-cells = <0>;
1207 compatible = "ti,omap3-interface-clock";
1208 clocks = <&l4_ck>;
1209 ti,bit-shift = <1>;
1210 reg = <0x021c>;
1211 };
1212
1213 rng_ick: rng_ick {
1214 #clock-cells = <0>;
1215 compatible = "ti,omap3-interface-clock";
1216 clocks = <&l4_ck>;
1217 ti,bit-shift = <2>;
1218 reg = <0x021c>;
1219 };
1220
1221 aes_ick: aes_ick {
1222 #clock-cells = <0>;
1223 compatible = "ti,omap3-interface-clock";
1224 clocks = <&l4_ck>;
1225 ti,bit-shift = <3>;
1226 reg = <0x021c>;
1227 };
1228
1229 pka_ick: pka_ick {
1230 #clock-cells = <0>;
1231 compatible = "ti,omap3-interface-clock";
1232 clocks = <&l4_ck>;
1233 ti,bit-shift = <4>;
1234 reg = <0x021c>;
1235 };
1236
1237 usb_fck: usb_fck {
1238 #clock-cells = <0>;
1239 compatible = "ti,wait-gate-clock";
1240 clocks = <&func_48m_ck>;
1241 ti,bit-shift = <0>;
1242 reg = <0x0204>;
1243 };
1244};
diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi
index 6b5280d04a0e..200ae3a5cbbb 100644
--- a/arch/arm/boot/dts/omap36xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi
@@ -83,7 +83,7 @@
83}; 83};
84 84
85&dpll4_m5x2_mul_ck { 85&dpll4_m5x2_mul_ck {
86 clock-mult = <1>; 86 ti,clock-mult = <1>;
87}; 87};
88 88
89&dpll4_m6x2_mul_ck { 89&dpll4_m6x2_mul_ck {
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
index 12be2b35dae9..e47ff69dcf70 100644
--- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -453,10 +453,11 @@
453 453
454 dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck { 454 dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
455 #clock-cells = <0>; 455 #clock-cells = <0>;
456 compatible = "fixed-factor-clock"; 456 compatible = "ti,fixed-factor-clock";
457 clocks = <&dpll4_m5_ck>; 457 clocks = <&dpll4_m5_ck>;
458 clock-mult = <2>; 458 ti,clock-mult = <2>;
459 clock-div = <1>; 459 ti,clock-div = <1>;
460 ti,set-rate-parent;
460 }; 461 };
461 462
462 dpll4_m5x2_ck: dpll4_m5x2_ck { 463 dpll4_m5x2_ck: dpll4_m5x2_ck {
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index f866de954c29..203131ebb581 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -67,6 +67,7 @@
67 67
68 local-timer@48240600 { 68 local-timer@48240600 {
69 compatible = "arm,cortex-a9-twd-timer"; 69 compatible = "arm,cortex-a9-twd-timer";
70 clocks = <&mpu_periphclk>;
70 reg = <0x48240600 0x20>; 71 reg = <0x48240600 0x20>;
71 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; 72 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
72 }; 73 };
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index d487fdab3921..aeb142ce8e9d 100644
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -120,10 +120,8 @@
120 compatible = "ti,divider-clock"; 120 compatible = "ti,divider-clock";
121 clocks = <&dpll_abe_x2_ck>; 121 clocks = <&dpll_abe_x2_ck>;
122 ti,max-div = <31>; 122 ti,max-div = <31>;
123 ti,autoidle-shift = <8>;
124 reg = <0x01f0>; 123 reg = <0x01f0>;
125 ti,index-starts-at-one; 124 ti,index-starts-at-one;
126 ti,invert-autoidle-bit;
127 }; 125 };
128 126
129 abe_24m_fclk: abe_24m_fclk { 127 abe_24m_fclk: abe_24m_fclk {
@@ -145,10 +143,11 @@
145 143
146 abe_iclk: abe_iclk { 144 abe_iclk: abe_iclk {
147 #clock-cells = <0>; 145 #clock-cells = <0>;
148 compatible = "fixed-factor-clock"; 146 compatible = "ti,divider-clock";
149 clocks = <&abe_clk>; 147 clocks = <&aess_fclk>;
150 clock-mult = <1>; 148 ti,bit-shift = <24>;
151 clock-div = <2>; 149 reg = <0x0528>;
150 ti,dividers = <2>, <1>;
152 }; 151 };
153 152
154 abe_lp_clk_div: abe_lp_clk_div { 153 abe_lp_clk_div: abe_lp_clk_div {
@@ -164,10 +163,8 @@
164 compatible = "ti,divider-clock"; 163 compatible = "ti,divider-clock";
165 clocks = <&dpll_abe_x2_ck>; 164 clocks = <&dpll_abe_x2_ck>;
166 ti,max-div = <31>; 165 ti,max-div = <31>;
167 ti,autoidle-shift = <8>;
168 reg = <0x01f4>; 166 reg = <0x01f4>;
169 ti,index-starts-at-one; 167 ti,index-starts-at-one;
170 ti,invert-autoidle-bit;
171 }; 168 };
172 169
173 dpll_core_ck: dpll_core_ck { 170 dpll_core_ck: dpll_core_ck {
@@ -188,10 +185,8 @@
188 compatible = "ti,divider-clock"; 185 compatible = "ti,divider-clock";
189 clocks = <&dpll_core_x2_ck>; 186 clocks = <&dpll_core_x2_ck>;
190 ti,max-div = <63>; 187 ti,max-div = <63>;
191 ti,autoidle-shift = <8>;
192 reg = <0x0150>; 188 reg = <0x0150>;
193 ti,index-starts-at-one; 189 ti,index-starts-at-one;
194 ti,invert-autoidle-bit;
195 }; 190 };
196 191
197 c2c_fclk: c2c_fclk { 192 c2c_fclk: c2c_fclk {
@@ -215,10 +210,8 @@
215 compatible = "ti,divider-clock"; 210 compatible = "ti,divider-clock";
216 clocks = <&dpll_core_x2_ck>; 211 clocks = <&dpll_core_x2_ck>;
217 ti,max-div = <63>; 212 ti,max-div = <63>;
218 ti,autoidle-shift = <8>;
219 reg = <0x0138>; 213 reg = <0x0138>;
220 ti,index-starts-at-one; 214 ti,index-starts-at-one;
221 ti,invert-autoidle-bit;
222 }; 215 };
223 216
224 dpll_core_h12x2_ck: dpll_core_h12x2_ck { 217 dpll_core_h12x2_ck: dpll_core_h12x2_ck {
@@ -226,10 +219,8 @@
226 compatible = "ti,divider-clock"; 219 compatible = "ti,divider-clock";
227 clocks = <&dpll_core_x2_ck>; 220 clocks = <&dpll_core_x2_ck>;
228 ti,max-div = <63>; 221 ti,max-div = <63>;
229 ti,autoidle-shift = <8>;
230 reg = <0x013c>; 222 reg = <0x013c>;
231 ti,index-starts-at-one; 223 ti,index-starts-at-one;
232 ti,invert-autoidle-bit;
233 }; 224 };
234 225
235 dpll_core_h13x2_ck: dpll_core_h13x2_ck { 226 dpll_core_h13x2_ck: dpll_core_h13x2_ck {
@@ -237,10 +228,8 @@
237 compatible = "ti,divider-clock"; 228 compatible = "ti,divider-clock";
238 clocks = <&dpll_core_x2_ck>; 229 clocks = <&dpll_core_x2_ck>;
239 ti,max-div = <63>; 230 ti,max-div = <63>;
240 ti,autoidle-shift = <8>;
241 reg = <0x0140>; 231 reg = <0x0140>;
242 ti,index-starts-at-one; 232 ti,index-starts-at-one;
243 ti,invert-autoidle-bit;
244 }; 233 };
245 234
246 dpll_core_h14x2_ck: dpll_core_h14x2_ck { 235 dpll_core_h14x2_ck: dpll_core_h14x2_ck {
@@ -248,10 +237,8 @@
248 compatible = "ti,divider-clock"; 237 compatible = "ti,divider-clock";
249 clocks = <&dpll_core_x2_ck>; 238 clocks = <&dpll_core_x2_ck>;
250 ti,max-div = <63>; 239 ti,max-div = <63>;
251 ti,autoidle-shift = <8>;
252 reg = <0x0144>; 240 reg = <0x0144>;
253 ti,index-starts-at-one; 241 ti,index-starts-at-one;
254 ti,invert-autoidle-bit;
255 }; 242 };
256 243
257 dpll_core_h22x2_ck: dpll_core_h22x2_ck { 244 dpll_core_h22x2_ck: dpll_core_h22x2_ck {
@@ -259,10 +246,8 @@
259 compatible = "ti,divider-clock"; 246 compatible = "ti,divider-clock";
260 clocks = <&dpll_core_x2_ck>; 247 clocks = <&dpll_core_x2_ck>;
261 ti,max-div = <63>; 248 ti,max-div = <63>;
262 ti,autoidle-shift = <8>;
263 reg = <0x0154>; 249 reg = <0x0154>;
264 ti,index-starts-at-one; 250 ti,index-starts-at-one;
265 ti,invert-autoidle-bit;
266 }; 251 };
267 252
268 dpll_core_h23x2_ck: dpll_core_h23x2_ck { 253 dpll_core_h23x2_ck: dpll_core_h23x2_ck {
@@ -270,10 +255,8 @@
270 compatible = "ti,divider-clock"; 255 compatible = "ti,divider-clock";
271 clocks = <&dpll_core_x2_ck>; 256 clocks = <&dpll_core_x2_ck>;
272 ti,max-div = <63>; 257 ti,max-div = <63>;
273 ti,autoidle-shift = <8>;
274 reg = <0x0158>; 258 reg = <0x0158>;
275 ti,index-starts-at-one; 259 ti,index-starts-at-one;
276 ti,invert-autoidle-bit;
277 }; 260 };
278 261
279 dpll_core_h24x2_ck: dpll_core_h24x2_ck { 262 dpll_core_h24x2_ck: dpll_core_h24x2_ck {
@@ -281,10 +264,8 @@
281 compatible = "ti,divider-clock"; 264 compatible = "ti,divider-clock";
282 clocks = <&dpll_core_x2_ck>; 265 clocks = <&dpll_core_x2_ck>;
283 ti,max-div = <63>; 266 ti,max-div = <63>;
284 ti,autoidle-shift = <8>;
285 reg = <0x015c>; 267 reg = <0x015c>;
286 ti,index-starts-at-one; 268 ti,index-starts-at-one;
287 ti,invert-autoidle-bit;
288 }; 269 };
289 270
290 dpll_core_m2_ck: dpll_core_m2_ck { 271 dpll_core_m2_ck: dpll_core_m2_ck {
@@ -292,10 +273,8 @@
292 compatible = "ti,divider-clock"; 273 compatible = "ti,divider-clock";
293 clocks = <&dpll_core_ck>; 274 clocks = <&dpll_core_ck>;
294 ti,max-div = <31>; 275 ti,max-div = <31>;
295 ti,autoidle-shift = <8>;
296 reg = <0x0130>; 276 reg = <0x0130>;
297 ti,index-starts-at-one; 277 ti,index-starts-at-one;
298 ti,invert-autoidle-bit;
299 }; 278 };
300 279
301 dpll_core_m3x2_ck: dpll_core_m3x2_ck { 280 dpll_core_m3x2_ck: dpll_core_m3x2_ck {
@@ -303,10 +282,8 @@
303 compatible = "ti,divider-clock"; 282 compatible = "ti,divider-clock";
304 clocks = <&dpll_core_x2_ck>; 283 clocks = <&dpll_core_x2_ck>;
305 ti,max-div = <31>; 284 ti,max-div = <31>;
306 ti,autoidle-shift = <8>;
307 reg = <0x0134>; 285 reg = <0x0134>;
308 ti,index-starts-at-one; 286 ti,index-starts-at-one;
309 ti,invert-autoidle-bit;
310 }; 287 };
311 288
312 iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { 289 iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
@@ -335,10 +312,8 @@
335 compatible = "ti,divider-clock"; 312 compatible = "ti,divider-clock";
336 clocks = <&dpll_iva_x2_ck>; 313 clocks = <&dpll_iva_x2_ck>;
337 ti,max-div = <63>; 314 ti,max-div = <63>;
338 ti,autoidle-shift = <8>;
339 reg = <0x01b8>; 315 reg = <0x01b8>;
340 ti,index-starts-at-one; 316 ti,index-starts-at-one;
341 ti,invert-autoidle-bit;
342 }; 317 };
343 318
344 dpll_iva_h12x2_ck: dpll_iva_h12x2_ck { 319 dpll_iva_h12x2_ck: dpll_iva_h12x2_ck {
@@ -346,10 +321,8 @@
346 compatible = "ti,divider-clock"; 321 compatible = "ti,divider-clock";
347 clocks = <&dpll_iva_x2_ck>; 322 clocks = <&dpll_iva_x2_ck>;
348 ti,max-div = <63>; 323 ti,max-div = <63>;
349 ti,autoidle-shift = <8>;
350 reg = <0x01bc>; 324 reg = <0x01bc>;
351 ti,index-starts-at-one; 325 ti,index-starts-at-one;
352 ti,invert-autoidle-bit;
353 }; 326 };
354 327
355 mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { 328 mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
@@ -372,10 +345,8 @@
372 compatible = "ti,divider-clock"; 345 compatible = "ti,divider-clock";
373 clocks = <&dpll_mpu_ck>; 346 clocks = <&dpll_mpu_ck>;
374 ti,max-div = <31>; 347 ti,max-div = <31>;
375 ti,autoidle-shift = <8>;
376 reg = <0x0170>; 348 reg = <0x0170>;
377 ti,index-starts-at-one; 349 ti,index-starts-at-one;
378 ti,invert-autoidle-bit;
379 }; 350 };
380 351
381 per_dpll_hs_clk_div: per_dpll_hs_clk_div { 352 per_dpll_hs_clk_div: per_dpll_hs_clk_div {
@@ -642,10 +613,8 @@
642 compatible = "ti,divider-clock"; 613 compatible = "ti,divider-clock";
643 clocks = <&dpll_per_x2_ck>; 614 clocks = <&dpll_per_x2_ck>;
644 ti,max-div = <63>; 615 ti,max-div = <63>;
645 ti,autoidle-shift = <8>;
646 reg = <0x0158>; 616 reg = <0x0158>;
647 ti,index-starts-at-one; 617 ti,index-starts-at-one;
648 ti,invert-autoidle-bit;
649 }; 618 };
650 619
651 dpll_per_h12x2_ck: dpll_per_h12x2_ck { 620 dpll_per_h12x2_ck: dpll_per_h12x2_ck {
@@ -653,10 +622,8 @@
653 compatible = "ti,divider-clock"; 622 compatible = "ti,divider-clock";
654 clocks = <&dpll_per_x2_ck>; 623 clocks = <&dpll_per_x2_ck>;
655 ti,max-div = <63>; 624 ti,max-div = <63>;
656 ti,autoidle-shift = <8>;
657 reg = <0x015c>; 625 reg = <0x015c>;
658 ti,index-starts-at-one; 626 ti,index-starts-at-one;
659 ti,invert-autoidle-bit;
660 }; 627 };
661 628
662 dpll_per_h14x2_ck: dpll_per_h14x2_ck { 629 dpll_per_h14x2_ck: dpll_per_h14x2_ck {
@@ -664,10 +631,8 @@
664 compatible = "ti,divider-clock"; 631 compatible = "ti,divider-clock";
665 clocks = <&dpll_per_x2_ck>; 632 clocks = <&dpll_per_x2_ck>;
666 ti,max-div = <63>; 633 ti,max-div = <63>;
667 ti,autoidle-shift = <8>;
668 reg = <0x0164>; 634 reg = <0x0164>;
669 ti,index-starts-at-one; 635 ti,index-starts-at-one;
670 ti,invert-autoidle-bit;
671 }; 636 };
672 637
673 dpll_per_m2_ck: dpll_per_m2_ck { 638 dpll_per_m2_ck: dpll_per_m2_ck {
@@ -675,10 +640,8 @@
675 compatible = "ti,divider-clock"; 640 compatible = "ti,divider-clock";
676 clocks = <&dpll_per_ck>; 641 clocks = <&dpll_per_ck>;
677 ti,max-div = <31>; 642 ti,max-div = <31>;
678 ti,autoidle-shift = <8>;
679 reg = <0x0150>; 643 reg = <0x0150>;
680 ti,index-starts-at-one; 644 ti,index-starts-at-one;
681 ti,invert-autoidle-bit;
682 }; 645 };
683 646
684 dpll_per_m2x2_ck: dpll_per_m2x2_ck { 647 dpll_per_m2x2_ck: dpll_per_m2x2_ck {
@@ -686,10 +649,8 @@
686 compatible = "ti,divider-clock"; 649 compatible = "ti,divider-clock";
687 clocks = <&dpll_per_x2_ck>; 650 clocks = <&dpll_per_x2_ck>;
688 ti,max-div = <31>; 651 ti,max-div = <31>;
689 ti,autoidle-shift = <8>;
690 reg = <0x0150>; 652 reg = <0x0150>;
691 ti,index-starts-at-one; 653 ti,index-starts-at-one;
692 ti,invert-autoidle-bit;
693 }; 654 };
694 655
695 dpll_per_m3x2_ck: dpll_per_m3x2_ck { 656 dpll_per_m3x2_ck: dpll_per_m3x2_ck {
@@ -697,10 +658,8 @@
697 compatible = "ti,divider-clock"; 658 compatible = "ti,divider-clock";
698 clocks = <&dpll_per_x2_ck>; 659 clocks = <&dpll_per_x2_ck>;
699 ti,max-div = <31>; 660 ti,max-div = <31>;
700 ti,autoidle-shift = <8>;
701 reg = <0x0154>; 661 reg = <0x0154>;
702 ti,index-starts-at-one; 662 ti,index-starts-at-one;
703 ti,invert-autoidle-bit;
704 }; 663 };
705 664
706 dpll_unipro1_ck: dpll_unipro1_ck { 665 dpll_unipro1_ck: dpll_unipro1_ck {
@@ -723,10 +682,8 @@
723 compatible = "ti,divider-clock"; 682 compatible = "ti,divider-clock";
724 clocks = <&dpll_unipro1_ck>; 683 clocks = <&dpll_unipro1_ck>;
725 ti,max-div = <127>; 684 ti,max-div = <127>;
726 ti,autoidle-shift = <8>;
727 reg = <0x0210>; 685 reg = <0x0210>;
728 ti,index-starts-at-one; 686 ti,index-starts-at-one;
729 ti,invert-autoidle-bit;
730 }; 687 };
731 688
732 dpll_unipro2_ck: dpll_unipro2_ck { 689 dpll_unipro2_ck: dpll_unipro2_ck {
@@ -749,10 +706,8 @@
749 compatible = "ti,divider-clock"; 706 compatible = "ti,divider-clock";
750 clocks = <&dpll_unipro2_ck>; 707 clocks = <&dpll_unipro2_ck>;
751 ti,max-div = <127>; 708 ti,max-div = <127>;
752 ti,autoidle-shift = <8>;
753 reg = <0x01d0>; 709 reg = <0x01d0>;
754 ti,index-starts-at-one; 710 ti,index-starts-at-one;
755 ti,invert-autoidle-bit;
756 }; 711 };
757 712
758 dpll_usb_ck: dpll_usb_ck { 713 dpll_usb_ck: dpll_usb_ck {
@@ -775,10 +730,8 @@
775 compatible = "ti,divider-clock"; 730 compatible = "ti,divider-clock";
776 clocks = <&dpll_usb_ck>; 731 clocks = <&dpll_usb_ck>;
777 ti,max-div = <127>; 732 ti,max-div = <127>;
778 ti,autoidle-shift = <8>;
779 reg = <0x0190>; 733 reg = <0x0190>;
780 ti,index-starts-at-one; 734 ti,index-starts-at-one;
781 ti,invert-autoidle-bit;
782 }; 735 };
783 736
784 func_128m_clk: func_128m_clk { 737 func_128m_clk: func_128m_clk {
@@ -851,6 +804,7 @@
851 clocks = <&dpll_per_h12x2_ck>; 804 clocks = <&dpll_per_h12x2_ck>;
852 ti,bit-shift = <8>; 805 ti,bit-shift = <8>;
853 reg = <0x1420>; 806 reg = <0x1420>;
807 ti,set-rate-parent;
854 }; 808 };
855 809
856 dss_sys_clk: dss_sys_clk { 810 dss_sys_clk: dss_sys_clk {
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index 67c8de572c50..527a43da3d33 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -105,6 +105,12 @@ static struct ti_dt_clk am43xx_clks[] = {
105 DT_CLK(NULL, "func_12m_clk", "func_12m_clk"), 105 DT_CLK(NULL, "func_12m_clk", "func_12m_clk"),
106 DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"), 106 DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"),
107 DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"), 107 DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"),
108 DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
109 DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
110 DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
111 DT_CLK("48306200.ehrpwm", "tbclk", "ehrpwm3_tbclk"),
112 DT_CLK("48308200.ehrpwm", "tbclk", "ehrpwm4_tbclk"),
113 DT_CLK("4830a200.ehrpwm", "tbclk", "ehrpwm5_tbclk"),
108 { .node_name = NULL }, 114 { .node_name = NULL },
109}; 115};
110 116
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-15 02:06:36 -0400