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authorOlof Johansson <olof@lixom.net>2018-09-23 09:37:47 -0400
committerOlof Johansson <olof@lixom.net>2018-09-23 09:37:47 -0400
commit42724dd8930f4a60d57899bc4d1bf467b4eab760 (patch)
tree483572c92a161171845f89762c38ecba60c1d170
parent45351fa32d1ca65f8bca637c055aff0158bfb7a0 (diff)
parent5510ee99c0deb0c0235acee6498a6745c8317df1 (diff)
Merge tag 'hisi-arm64-dt-for-4.20' of git://github.com/hisilicon/linux-hisi into next/dt
ARM64: DT: Hisilicon SoC DT updates for 4.20 - Add missing clocks for Hi6220 - Switch to updated coresight bindings for Hi6220 - Add DT bindings and support for Hi3670 SoC and HiKey970 board * tag 'hisi-arm64-dt-for-4.20' of git://github.com/hisilicon/linux-hisi: arm64: dts: Add devicetree support for HiKey970 board dt-bindings: arm: hisilicon: Add binding for HiKey970 board arm64: dts: Add devicetree for Hisilicon Hi3670 SoC dt-bindings: arm: hisilicon: Add binding for Hi3670 SoC arm64: dts: hi6220: Update coresight bindings for hardware ports arm64: dts: hisilicon: Add missing clocks property for CPUs Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt8
-rw-r--r--arch/arm64/boot/dts/hisilicon/Makefile1
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts35
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi3670.dtsi162
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi181
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi6220.dtsi7
6 files changed, 299 insertions, 95 deletions
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 199cd36fe1ba..a97f643e7d1c 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -8,6 +8,14 @@ HiKey960 Board
8Required root node properties: 8Required root node properties:
9 - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; 9 - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
10 10
11Hi3670 SoC
12Required root node properties:
13 - compatible = "hisilicon,hi3670";
14
15HiKey970 Board
16Required root node properties:
17 - compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
18
11Hi3798cv200 SoC 19Hi3798cv200 SoC
12Required root node properties: 20Required root node properties:
13 - compatible = "hisilicon,hi3798cv200"; 21 - compatible = "hisilicon,hi3798cv200";
diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile
index 03d93f8ef8a9..f4d68caeba83 100644
--- a/arch/arm64/boot/dts/hisilicon/Makefile
+++ b/arch/arm64/boot/dts/hisilicon/Makefile
@@ -1,5 +1,6 @@
1# SPDX-License-Identifier: GPL-2.0 1# SPDX-License-Identifier: GPL-2.0
2dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb 2dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb
3dtb-$(CONFIG_ARCH_HISI) += hi3670-hikey970.dtb
3dtb-$(CONFIG_ARCH_HISI) += hi3798cv200-poplar.dtb 4dtb-$(CONFIG_ARCH_HISI) += hi3798cv200-poplar.dtb
4dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb 5dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
5dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb 6dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
new file mode 100644
index 000000000000..4f5118642024
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
@@ -0,0 +1,35 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Hisilicon HiKey970 Development Board
4 *
5 * Copyright (C) 2016, Hisilicon Ltd.
6 * Copyright (C) 2018, Linaro Ltd.
7 *
8 */
9
10/dts-v1/;
11
12#include "hi3670.dtsi"
13
14/ {
15 model = "HiKey970";
16 compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
17
18 aliases {
19 serial6 = &uart6; /* console UART */
20 };
21
22 chosen {
23 stdout-path = "serial6:115200n8";
24 };
25
26 memory@0 {
27 device_type = "memory";
28 /* expect bootloader to fill in this region */
29 reg = <0x0 0x0 0x0 0x0>;
30 };
31};
32
33&uart6 {
34 status = "okay";
35};
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
new file mode 100644
index 000000000000..c90e6f6a34ec
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -0,0 +1,162 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Hisilicon Hi3670 SoC
4 *
5 * Copyright (C) 2016, Hisilicon Ltd.
6 * Copyright (C) 2018, Linaro Ltd.
7 */
8
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12 compatible = "hisilicon,hi3670";
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 psci {
18 compatible = "arm,psci-0.2";
19 method = "smc";
20 };
21
22 cpus {
23 #address-cells = <2>;
24 #size-cells = <0>;
25
26 cpu-map {
27 cluster0 {
28 core0 {
29 cpu = <&cpu0>;
30 };
31 core1 {
32 cpu = <&cpu1>;
33 };
34 core2 {
35 cpu = <&cpu2>;
36 };
37 core3 {
38 cpu = <&cpu3>;
39 };
40 };
41 cluster1 {
42 core0 {
43 cpu = <&cpu4>;
44 };
45 core1 {
46 cpu = <&cpu5>;
47 };
48 core2 {
49 cpu = <&cpu6>;
50 };
51 core3 {
52 cpu = <&cpu7>;
53 };
54 };
55 };
56
57 cpu0: cpu@0 {
58 compatible = "arm,cortex-a53", "arm,armv8";
59 device_type = "cpu";
60 reg = <0x0 0x0>;
61 enable-method = "psci";
62 };
63
64 cpu1: cpu@1 {
65 compatible = "arm,cortex-a53", "arm,armv8";
66 device_type = "cpu";
67 reg = <0x0 0x1>;
68 enable-method = "psci";
69 };
70
71 cpu2: cpu@2 {
72 compatible = "arm,cortex-a53", "arm,armv8";
73 device_type = "cpu";
74 reg = <0x0 0x2>;
75 enable-method = "psci";
76 };
77
78 cpu3: cpu@3 {
79 compatible = "arm,cortex-a53", "arm,armv8";
80 device_type = "cpu";
81 reg = <0x0 0x3>;
82 enable-method = "psci";
83 };
84
85 cpu4: cpu@100 {
86 compatible = "arm,cortex-a73", "arm,armv8";
87 device_type = "cpu";
88 reg = <0x0 0x100>;
89 enable-method = "psci";
90 };
91
92 cpu5: cpu@101 {
93 compatible = "arm,cortex-a73", "arm,armv8";
94 device_type = "cpu";
95 reg = <0x0 0x101>;
96 enable-method = "psci";
97 };
98
99 cpu6: cpu@102 {
100 compatible = "arm,cortex-a73", "arm,armv8";
101 device_type = "cpu";
102 reg = <0x0 0x102>;
103 enable-method = "psci";
104 };
105
106 cpu7: cpu@103 {
107 compatible = "arm,cortex-a73", "arm,armv8";
108 device_type = "cpu";
109 reg = <0x0 0x103>;
110 enable-method = "psci";
111 };
112 };
113
114 gic: interrupt-controller@e82b0000 {
115 compatible = "arm,gic-400";
116 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
117 <0x0 0xe82b2000 0 0x2000>, /* GICC */
118 <0x0 0xe82b4000 0 0x2000>, /* GICH */
119 <0x0 0xe82b6000 0 0x2000>; /* GICV */
120 #interrupt-cells = <3>;
121 #address-cells = <0>;
122 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
123 IRQ_TYPE_LEVEL_HIGH)>;
124 interrupt-controller;
125 };
126
127 timer {
128 compatible = "arm,armv8-timer";
129 interrupt-parent = <&gic>;
130 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
131 IRQ_TYPE_LEVEL_LOW)>,
132 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
133 IRQ_TYPE_LEVEL_LOW)>,
134 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
135 IRQ_TYPE_LEVEL_LOW)>,
136 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
137 IRQ_TYPE_LEVEL_LOW)>;
138 clock-frequency = <1920000>;
139 };
140
141 soc {
142 compatible = "simple-bus";
143 #address-cells = <2>;
144 #size-cells = <2>;
145 ranges;
146
147 uart6_clk: clk_19_2M {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <19200000>;
151 };
152
153 uart6: serial@fff32000 {
154 compatible = "arm,pl011", "arm,primecell";
155 reg = <0x0 0xfff32000 0x0 0x1000>;
156 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&uart6_clk &uart6_clk>;
158 clock-names = "uartclk", "apb_pclk";
159 status = "disabled";
160 };
161 };
162};
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
index 7afee5d5087b..68c52f1149be 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
@@ -20,22 +20,18 @@
20 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; 20 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
21 clock-names = "apb_pclk"; 21 clock-names = "apb_pclk";
22 22
23 ports { 23 out-ports {
24 #address-cells = <1>; 24 port {
25 #size-cells = <0>;
26
27 port@0 {
28 reg = <0>;
29 soc_funnel_out: endpoint { 25 soc_funnel_out: endpoint {
30 remote-endpoint = 26 remote-endpoint =
31 <&etf_in>; 27 <&etf_in>;
32 }; 28 };
33 }; 29 };
30 };
34 31
35 port@1 { 32 in-ports {
36 reg = <0>; 33 port {
37 soc_funnel_in: endpoint { 34 soc_funnel_in: endpoint {
38 slave-mode;
39 remote-endpoint = 35 remote-endpoint =
40 <&acpu_funnel_out>; 36 <&acpu_funnel_out>;
41 }; 37 };
@@ -49,21 +45,17 @@
49 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; 45 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
50 clock-names = "apb_pclk"; 46 clock-names = "apb_pclk";
51 47
52 ports { 48 in-ports {
53 #address-cells = <1>; 49 port {
54 #size-cells = <0>;
55
56 port@0 {
57 reg = <0>;
58 etf_in: endpoint { 50 etf_in: endpoint {
59 slave-mode;
60 remote-endpoint = 51 remote-endpoint =
61 <&soc_funnel_out>; 52 <&soc_funnel_out>;
62 }; 53 };
63 }; 54 };
55 };
64 56
65 port@1 { 57 out-ports {
66 reg = <0>; 58 port {
67 etf_out: endpoint { 59 etf_out: endpoint {
68 remote-endpoint = 60 remote-endpoint =
69 <&replicator_in>; 61 <&replicator_in>;
@@ -77,20 +69,20 @@
77 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; 69 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
78 clock-names = "apb_pclk"; 70 clock-names = "apb_pclk";
79 71
80 ports { 72 in-ports {
81 #address-cells = <1>; 73 port {
82 #size-cells = <0>;
83
84 port@0 {
85 reg = <0>;
86 replicator_in: endpoint { 74 replicator_in: endpoint {
87 slave-mode;
88 remote-endpoint = 75 remote-endpoint =
89 <&etf_out>; 76 <&etf_out>;
90 }; 77 };
91 }; 78 };
79 };
92 80
93 port@1 { 81 out-ports {
82 #address-cells = <1>;
83 #size-cells = <0>;
84
85 port@0 {
94 reg = <0>; 86 reg = <0>;
95 replicator_out0: endpoint { 87 replicator_out0: endpoint {
96 remote-endpoint = 88 remote-endpoint =
@@ -98,7 +90,7 @@
98 }; 90 };
99 }; 91 };
100 92
101 port@2 { 93 port@1 {
102 reg = <1>; 94 reg = <1>;
103 replicator_out1: endpoint { 95 replicator_out1: endpoint {
104 remote-endpoint = 96 remote-endpoint =
@@ -114,14 +106,9 @@
114 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; 106 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
115 clock-names = "apb_pclk"; 107 clock-names = "apb_pclk";
116 108
117 ports { 109 in-ports {
118 #address-cells = <1>; 110 port {
119 #size-cells = <0>;
120
121 port@0 {
122 reg = <0>;
123 etr_in: endpoint { 111 etr_in: endpoint {
124 slave-mode;
125 remote-endpoint = 112 remote-endpoint =
126 <&replicator_out0>; 113 <&replicator_out0>;
127 }; 114 };
@@ -135,14 +122,9 @@
135 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; 122 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
136 clock-names = "apb_pclk"; 123 clock-names = "apb_pclk";
137 124
138 ports { 125 in-ports {
139 #address-cells = <1>; 126 port {
140 #size-cells = <0>;
141
142 port@0 {
143 reg = <0>;
144 tpiu_in: endpoint { 127 tpiu_in: endpoint {
145 slave-mode;
146 remote-endpoint = 128 remote-endpoint =
147 <&replicator_out1>; 129 <&replicator_out1>;
148 }; 130 };
@@ -156,85 +138,78 @@
156 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; 138 clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
157 clock-names = "apb_pclk"; 139 clock-names = "apb_pclk";
158 140
159 ports { 141 out-ports {
160 #address-cells = <1>; 142 port {
161 #size-cells = <0>;
162
163 port@0 {
164 reg = <0>;
165 acpu_funnel_out: endpoint { 143 acpu_funnel_out: endpoint {
166 remote-endpoint = 144 remote-endpoint =
167 <&soc_funnel_in>; 145 <&soc_funnel_in>;
168 }; 146 };
169 }; 147 };
148 };
170 149
171 port@1 { 150 in-ports {
151 #address-cells = <1>;
152 #size-cells = <0>;
153
154 port@0 {
172 reg = <0>; 155 reg = <0>;
173 acpu_funnel_in0: endpoint { 156 acpu_funnel_in0: endpoint {
174 slave-mode;
175 remote-endpoint = 157 remote-endpoint =
176 <&etm0_out>; 158 <&etm0_out>;
177 }; 159 };
178 }; 160 };
179 161
180 port@2 { 162 port@1 {
181 reg = <1>; 163 reg = <1>;
182 acpu_funnel_in1: endpoint { 164 acpu_funnel_in1: endpoint {
183 slave-mode;
184 remote-endpoint = 165 remote-endpoint =
185 <&etm1_out>; 166 <&etm1_out>;
186 }; 167 };
187 }; 168 };
188 169
189 port@3 { 170 port@2 {
190 reg = <2>; 171 reg = <2>;
191 acpu_funnel_in2: endpoint { 172 acpu_funnel_in2: endpoint {
192 slave-mode;
193 remote-endpoint = 173 remote-endpoint =
194 <&etm2_out>; 174 <&etm2_out>;
195 }; 175 };
196 }; 176 };
197 177
198 port@4 { 178 port@3 {
199 reg = <3>; 179 reg = <3>;
200 acpu_funnel_in3: endpoint { 180 acpu_funnel_in3: endpoint {
201 slave-mode;
202 remote-endpoint = 181 remote-endpoint =
203 <&etm3_out>; 182 <&etm3_out>;
204 }; 183 };
205 }; 184 };
206 185
207 port@5 { 186 port@4 {
208 reg = <4>; 187 reg = <4>;
209 acpu_funnel_in4: endpoint { 188 acpu_funnel_in4: endpoint {
210 slave-mode;
211 remote-endpoint = 189 remote-endpoint =
212 <&etm4_out>; 190 <&etm4_out>;
213 }; 191 };
214 }; 192 };
215 193
216 port@6 { 194 port@5 {
217 reg = <5>; 195 reg = <5>;
218 acpu_funnel_in5: endpoint { 196 acpu_funnel_in5: endpoint {
219 slave-mode;
220 remote-endpoint = 197 remote-endpoint =
221 <&etm5_out>; 198 <&etm5_out>;
222 }; 199 };
223 }; 200 };
224 201
225 port@7 { 202 port@6 {
226 reg = <6>; 203 reg = <6>;
227 acpu_funnel_in6: endpoint { 204 acpu_funnel_in6: endpoint {
228 slave-mode;
229 remote-endpoint = 205 remote-endpoint =
230 <&etm6_out>; 206 <&etm6_out>;
231 }; 207 };
232 }; 208 };
233 209
234 port@8 { 210 port@7 {
235 reg = <7>; 211 reg = <7>;
236 acpu_funnel_in7: endpoint { 212 acpu_funnel_in7: endpoint {
237 slave-mode;
238 remote-endpoint = 213 remote-endpoint =
239 <&etm7_out>; 214 <&etm7_out>;
240 }; 215 };
@@ -251,10 +226,12 @@
251 226
252 cpu = <&cpu0>; 227 cpu = <&cpu0>;
253 228
254 port { 229 out-ports {
255 etm0_out: endpoint { 230 port {
256 remote-endpoint = 231 etm0_out: endpoint {
257 <&acpu_funnel_in0>; 232 remote-endpoint =
233 <&acpu_funnel_in0>;
234 };
258 }; 235 };
259 }; 236 };
260 }; 237 };
@@ -268,10 +245,12 @@
268 245
269 cpu = <&cpu1>; 246 cpu = <&cpu1>;
270 247
271 port { 248 out-ports {
272 etm1_out: endpoint { 249 port {
273 remote-endpoint = 250 etm1_out: endpoint {
274 <&acpu_funnel_in1>; 251 remote-endpoint =
252 <&acpu_funnel_in1>;
253 };
275 }; 254 };
276 }; 255 };
277 }; 256 };
@@ -285,10 +264,12 @@
285 264
286 cpu = <&cpu2>; 265 cpu = <&cpu2>;
287 266
288 port { 267 out-ports {
289 etm2_out: endpoint { 268 port {
290 remote-endpoint = 269 etm2_out: endpoint {
291 <&acpu_funnel_in2>; 270 remote-endpoint =
271 <&acpu_funnel_in2>;
272 };
292 }; 273 };
293 }; 274 };
294 }; 275 };
@@ -302,10 +283,12 @@
302 283
303 cpu = <&cpu3>; 284 cpu = <&cpu3>;
304 285
305 port { 286 out-ports {
306 etm3_out: endpoint { 287 port {
307 remote-endpoint = 288 etm3_out: endpoint {
308 <&acpu_funnel_in3>; 289 remote-endpoint =
290 <&acpu_funnel_in3>;
291 };
309 }; 292 };
310 }; 293 };
311 }; 294 };
@@ -319,10 +302,12 @@
319 302
320 cpu = <&cpu4>; 303 cpu = <&cpu4>;
321 304
322 port { 305 out-ports {
323 etm4_out: endpoint { 306 port {
324 remote-endpoint = 307 etm4_out: endpoint {
325 <&acpu_funnel_in4>; 308 remote-endpoint =
309 <&acpu_funnel_in4>;
310 };
326 }; 311 };
327 }; 312 };
328 }; 313 };
@@ -336,10 +321,12 @@
336 321
337 cpu = <&cpu5>; 322 cpu = <&cpu5>;
338 323
339 port { 324 out-ports {
340 etm5_out: endpoint { 325 port {
341 remote-endpoint = 326 etm5_out: endpoint {
342 <&acpu_funnel_in5>; 327 remote-endpoint =
328 <&acpu_funnel_in5>;
329 };
343 }; 330 };
344 }; 331 };
345 }; 332 };
@@ -353,10 +340,12 @@
353 340
354 cpu = <&cpu6>; 341 cpu = <&cpu6>;
355 342
356 port { 343 out-ports {
357 etm6_out: endpoint { 344 port {
358 remote-endpoint = 345 etm6_out: endpoint {
359 <&acpu_funnel_in6>; 346 remote-endpoint =
347 <&acpu_funnel_in6>;
348 };
360 }; 349 };
361 }; 350 };
362 }; 351 };
@@ -370,10 +359,12 @@
370 359
371 cpu = <&cpu7>; 360 cpu = <&cpu7>;
372 361
373 port { 362 out-ports {
374 etm7_out: endpoint { 363 port {
375 remote-endpoint = 364 etm7_out: endpoint {
376 <&acpu_funnel_in7>; 365 remote-endpoint =
366 <&acpu_funnel_in7>;
367 };
377 }; 368 };
378 }; 369 };
379 }; 370 };
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 247024df714f..97d5bf2c6ec5 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -99,6 +99,7 @@
99 reg = <0x0 0x1>; 99 reg = <0x0 0x1>;
100 enable-method = "psci"; 100 enable-method = "psci";
101 next-level-cache = <&CLUSTER0_L2>; 101 next-level-cache = <&CLUSTER0_L2>;
102 clocks = <&stub_clock 0>;
102 operating-points-v2 = <&cpu_opp_table>; 103 operating-points-v2 = <&cpu_opp_table>;
103 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 104 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
104 #cooling-cells = <2>; /* min followed by max */ 105 #cooling-cells = <2>; /* min followed by max */
@@ -111,6 +112,7 @@
111 reg = <0x0 0x2>; 112 reg = <0x0 0x2>;
112 enable-method = "psci"; 113 enable-method = "psci";
113 next-level-cache = <&CLUSTER0_L2>; 114 next-level-cache = <&CLUSTER0_L2>;
115 clocks = <&stub_clock 0>;
114 operating-points-v2 = <&cpu_opp_table>; 116 operating-points-v2 = <&cpu_opp_table>;
115 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 117 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
116 #cooling-cells = <2>; /* min followed by max */ 118 #cooling-cells = <2>; /* min followed by max */
@@ -123,6 +125,7 @@
123 reg = <0x0 0x3>; 125 reg = <0x0 0x3>;
124 enable-method = "psci"; 126 enable-method = "psci";
125 next-level-cache = <&CLUSTER0_L2>; 127 next-level-cache = <&CLUSTER0_L2>;
128 clocks = <&stub_clock 0>;
126 operating-points-v2 = <&cpu_opp_table>; 129 operating-points-v2 = <&cpu_opp_table>;
127 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 130 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
128 #cooling-cells = <2>; /* min followed by max */ 131 #cooling-cells = <2>; /* min followed by max */
@@ -135,6 +138,7 @@
135 reg = <0x0 0x100>; 138 reg = <0x0 0x100>;
136 enable-method = "psci"; 139 enable-method = "psci";
137 next-level-cache = <&CLUSTER1_L2>; 140 next-level-cache = <&CLUSTER1_L2>;
141 clocks = <&stub_clock 0>;
138 operating-points-v2 = <&cpu_opp_table>; 142 operating-points-v2 = <&cpu_opp_table>;
139 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 143 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
140 #cooling-cells = <2>; /* min followed by max */ 144 #cooling-cells = <2>; /* min followed by max */
@@ -147,6 +151,7 @@
147 reg = <0x0 0x101>; 151 reg = <0x0 0x101>;
148 enable-method = "psci"; 152 enable-method = "psci";
149 next-level-cache = <&CLUSTER1_L2>; 153 next-level-cache = <&CLUSTER1_L2>;
154 clocks = <&stub_clock 0>;
150 operating-points-v2 = <&cpu_opp_table>; 155 operating-points-v2 = <&cpu_opp_table>;
151 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 156 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
152 #cooling-cells = <2>; /* min followed by max */ 157 #cooling-cells = <2>; /* min followed by max */
@@ -159,6 +164,7 @@
159 reg = <0x0 0x102>; 164 reg = <0x0 0x102>;
160 enable-method = "psci"; 165 enable-method = "psci";
161 next-level-cache = <&CLUSTER1_L2>; 166 next-level-cache = <&CLUSTER1_L2>;
167 clocks = <&stub_clock 0>;
162 operating-points-v2 = <&cpu_opp_table>; 168 operating-points-v2 = <&cpu_opp_table>;
163 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 169 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
164 #cooling-cells = <2>; /* min followed by max */ 170 #cooling-cells = <2>; /* min followed by max */
@@ -171,6 +177,7 @@
171 reg = <0x0 0x103>; 177 reg = <0x0 0x103>;
172 enable-method = "psci"; 178 enable-method = "psci";
173 next-level-cache = <&CLUSTER1_L2>; 179 next-level-cache = <&CLUSTER1_L2>;
180 clocks = <&stub_clock 0>;
174 operating-points-v2 = <&cpu_opp_table>; 181 operating-points-v2 = <&cpu_opp_table>;
175 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 182 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
176 #cooling-cells = <2>; /* min followed by max */ 183 #cooling-cells = <2>; /* min followed by max */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 23:21:35 -0400