diff options
author | Dave Jiang <dave.jiang@intel.com> | 2017-11-10 18:45:27 -0500 |
---|---|---|
committer | Jon Mason <jdmason@kudzu.us> | 2017-11-18 20:54:47 -0500 |
commit | 4201a9918c49bece71d25b2ef30cbadb1fc528e8 (patch) | |
tree | 6cb3a6491dc4385c0603457a083c3bfafbe27ffd | |
parent | 3a814a04e62f45e7d1887025316fc7faa0ce840a (diff) |
ntb: intel: remove b2b memory window workaround for Skylake NTB
The workaround code is never used because Skylake NTB does not need it.
Reported-by: Allen Hubbe <allen.hubbe@dell.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jon Mason <jdmason@kudzu.us>
-rw-r--r-- | drivers/ntb/hw/intel/ntb_hw_intel.c | 75 |
1 files changed, 2 insertions, 73 deletions
diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.c b/drivers/ntb/hw/intel/ntb_hw_intel.c index 2557e2c05b90..4de074a86073 100644 --- a/drivers/ntb/hw/intel/ntb_hw_intel.c +++ b/drivers/ntb/hw/intel/ntb_hw_intel.c | |||
@@ -1742,89 +1742,18 @@ static int skx_setup_b2b_mw(struct intel_ntb_dev *ndev, | |||
1742 | { | 1742 | { |
1743 | struct pci_dev *pdev; | 1743 | struct pci_dev *pdev; |
1744 | void __iomem *mmio; | 1744 | void __iomem *mmio; |
1745 | resource_size_t bar_size; | ||
1746 | phys_addr_t bar_addr; | 1745 | phys_addr_t bar_addr; |
1747 | int b2b_bar; | ||
1748 | u8 bar_sz; | ||
1749 | 1746 | ||
1750 | pdev = ndev->ntb.pdev; | 1747 | pdev = ndev->ntb.pdev; |
1751 | mmio = ndev->self_mmio; | 1748 | mmio = ndev->self_mmio; |
1752 | 1749 | ||
1753 | if (ndev->b2b_idx == UINT_MAX) { | ||
1754 | dev_dbg(&pdev->dev, "not using b2b mw\n"); | ||
1755 | b2b_bar = 0; | ||
1756 | ndev->b2b_off = 0; | ||
1757 | } else { | ||
1758 | b2b_bar = ndev_mw_to_bar(ndev, ndev->b2b_idx); | ||
1759 | if (b2b_bar < 0) | ||
1760 | return -EIO; | ||
1761 | |||
1762 | dev_dbg(&pdev->dev, "using b2b mw bar %d\n", b2b_bar); | ||
1763 | |||
1764 | bar_size = pci_resource_len(ndev->ntb.pdev, b2b_bar); | ||
1765 | |||
1766 | dev_dbg(&pdev->dev, "b2b bar size %#llx\n", bar_size); | ||
1767 | |||
1768 | if (b2b_mw_share && ((bar_size >> 1) >= XEON_B2B_MIN_SIZE)) { | ||
1769 | dev_dbg(&pdev->dev, "b2b using first half of bar\n"); | ||
1770 | ndev->b2b_off = bar_size >> 1; | ||
1771 | } else if (bar_size >= XEON_B2B_MIN_SIZE) { | ||
1772 | dev_dbg(&pdev->dev, "b2b using whole bar\n"); | ||
1773 | ndev->b2b_off = 0; | ||
1774 | --ndev->mw_count; | ||
1775 | } else { | ||
1776 | dev_dbg(&pdev->dev, "b2b bar size is too small\n"); | ||
1777 | return -EIO; | ||
1778 | } | ||
1779 | } | ||
1780 | |||
1781 | /* | ||
1782 | * Reset the secondary bar sizes to match the primary bar sizes, | ||
1783 | * except disable or halve the size of the b2b secondary bar. | ||
1784 | */ | ||
1785 | pci_read_config_byte(pdev, SKX_IMBAR1SZ_OFFSET, &bar_sz); | ||
1786 | dev_dbg(&pdev->dev, "IMBAR1SZ %#x\n", bar_sz); | ||
1787 | if (b2b_bar == 1) { | ||
1788 | if (ndev->b2b_off) | ||
1789 | bar_sz -= 1; | ||
1790 | else | ||
1791 | bar_sz = 0; | ||
1792 | } | ||
1793 | |||
1794 | pci_write_config_byte(pdev, SKX_EMBAR1SZ_OFFSET, bar_sz); | ||
1795 | pci_read_config_byte(pdev, SKX_EMBAR1SZ_OFFSET, &bar_sz); | ||
1796 | dev_dbg(&pdev->dev, "EMBAR1SZ %#x\n", bar_sz); | ||
1797 | |||
1798 | pci_read_config_byte(pdev, SKX_IMBAR2SZ_OFFSET, &bar_sz); | ||
1799 | dev_dbg(&pdev->dev, "IMBAR2SZ %#x\n", bar_sz); | ||
1800 | if (b2b_bar == 2) { | ||
1801 | if (ndev->b2b_off) | ||
1802 | bar_sz -= 1; | ||
1803 | else | ||
1804 | bar_sz = 0; | ||
1805 | } | ||
1806 | |||
1807 | pci_write_config_byte(pdev, SKX_EMBAR2SZ_OFFSET, bar_sz); | ||
1808 | pci_read_config_byte(pdev, SKX_EMBAR2SZ_OFFSET, &bar_sz); | ||
1809 | dev_dbg(&pdev->dev, "EMBAR2SZ %#x\n", bar_sz); | ||
1810 | |||
1811 | /* SBAR01 hit by first part of the b2b bar */ | ||
1812 | if (b2b_bar == 0) | ||
1813 | bar_addr = addr->bar0_addr; | ||
1814 | else if (b2b_bar == 1) | ||
1815 | bar_addr = addr->bar2_addr64; | ||
1816 | else if (b2b_bar == 2) | ||
1817 | bar_addr = addr->bar4_addr64; | ||
1818 | else | ||
1819 | return -EIO; | ||
1820 | |||
1821 | /* setup incoming bar limits == base addrs (zero length windows) */ | 1750 | /* setup incoming bar limits == base addrs (zero length windows) */ |
1822 | bar_addr = addr->bar2_addr64 + (b2b_bar == 1 ? ndev->b2b_off : 0); | 1751 | bar_addr = addr->bar2_addr64; |
1823 | iowrite64(bar_addr, mmio + SKX_IMBAR1XLMT_OFFSET); | 1752 | iowrite64(bar_addr, mmio + SKX_IMBAR1XLMT_OFFSET); |
1824 | bar_addr = ioread64(mmio + SKX_IMBAR1XLMT_OFFSET); | 1753 | bar_addr = ioread64(mmio + SKX_IMBAR1XLMT_OFFSET); |
1825 | dev_dbg(&pdev->dev, "IMBAR1XLMT %#018llx\n", bar_addr); | 1754 | dev_dbg(&pdev->dev, "IMBAR1XLMT %#018llx\n", bar_addr); |
1826 | 1755 | ||
1827 | bar_addr = addr->bar4_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0); | 1756 | bar_addr = addr->bar4_addr64; |
1828 | iowrite64(bar_addr, mmio + SKX_IMBAR2XLMT_OFFSET); | 1757 | iowrite64(bar_addr, mmio + SKX_IMBAR2XLMT_OFFSET); |
1829 | bar_addr = ioread64(mmio + SKX_IMBAR2XLMT_OFFSET); | 1758 | bar_addr = ioread64(mmio + SKX_IMBAR2XLMT_OFFSET); |
1830 | dev_dbg(&pdev->dev, "IMBAR2XLMT %#018llx\n", bar_addr); | 1759 | dev_dbg(&pdev->dev, "IMBAR2XLMT %#018llx\n", bar_addr); |