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authorLinus Torvalds <torvalds@linux-foundation.org>2018-02-07 14:33:08 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2018-02-07 14:33:08 -0500
commit413879a10b0b0eb563a23c4df896773b2d9413f9 (patch)
tree6bf6664b45b28148087fb6b50c2d20bbc8d13d19
parent0bd2afc74808389591894dd7c7c83952006a1283 (diff)
parent4889dec6c87d90619cc1e8436327b91f4bb0e467 (diff)
Merge tag 'riscv-for-linus-4.16-merge_window' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux
Pull RISC-V updates from Palmer Dabbelt: "This contains the fixes we'd like to target for the 4.16 merge window. It's not as much as I was originally hoping to do but between glibc, the chip, and FOSDEM there just wasn't enough time to get everything put together. As such, this merge window is essentially just going to be small changes. This includes mostly cleanups: - A build fix failure to the audit test cases. RISC-V doesn't have renameat because the generic syscall ABI moved to renameat2 by the time of our port. The syscall audit test cases don't understand this, so I added a trivial fix. This went through mailing list review during the 4.15 merge window, but nobody has picked it up so I think it's best to just do this here. - The removal of our command-line argument processing code. The "mem_end" stuff was broken and the rest duplicated generic device tree code. The generic code was already being called. - Some unused/redundant code has been removed, including __ARCH_HAVE_MMU, current_pgdir, and the initialization of init_mm.pgd. - SUM is disabled upon taking a trap, which means that user memory is protected during traps taking inside copy_{to,from}_user(). - The sptbr CSR has been renamed to satp in C code. We haven't changed the assembly code in order to maintain compatibility with binutils 2.29, which doesn't understand the new name. Additionally, we're adding some new features: - Basic ftrace support, thanks to Alan Kao! - Support for ZONE_DMA32. This is necessary for all the normal reasons, but also to deal with a deficiency in the Xilinx PCIe controller we're using on our FPGA-based systems. While the ZONE_DMA32 addition should be sufficient for most uses, it doesn't complete the fix for the Xilinx controller. - TLB shootdowns now only target the harts where they're necessary, instead of applying to all harts in the system. These patches have all been sitting on our linux-next branch for a while now. Due to time constraints this is all I feel comfortable submitting during the 4.16 merge window, hopefully we'll do better next time!" [ Note to self: "harts" is RISC-V speak for "hardware threads". I had to look that up. - Linus ] * tag 'riscv-for-linus-4.16-merge_window' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux: riscv: inline set_pgdir into its only caller riscv: rename sptbr to satp riscv: don't read back satp in paging_init riscv: remove the unused current_pgdir function riscv: add ZONE_DMA32 RISC-V: Limit the scope of TLB shootdowns riscv: disable SUM in the exception handler riscv: remove redundant unlikely() riscv: remove unused __ARCH_HAVE_MMU define riscv/ftrace: Add basic support RISC-V: Remove mem_end command line processing RISC-V: Remove duplicate command-line parsing logic audit: Avoid build failures on systems without renameat
Diffstat
-rw-r--r--arch/riscv/Kconfig10
-rw-r--r--arch/riscv/include/asm/Kbuild1
-rw-r--r--arch/riscv/include/asm/csr.h14
-rw-r--r--arch/riscv/include/asm/ftrace.h10
-rw-r--r--arch/riscv/include/asm/mmu_context.h17
-rw-r--r--arch/riscv/include/asm/tlbflush.h20
-rw-r--r--arch/riscv/include/asm/unistd.h1
-rw-r--r--arch/riscv/kernel/Makefile7
-rw-r--r--arch/riscv/kernel/entry.S9
-rw-r--r--arch/riscv/kernel/ftrace.c41
-rw-r--r--arch/riscv/kernel/head.S6
-rw-r--r--arch/riscv/kernel/mcount.S126
-rw-r--r--arch/riscv/kernel/setup.c44
-rw-r--r--arch/riscv/kernel/vdso.c2
-rw-r--r--arch/riscv/mm/fault.c4
-rw-r--r--arch/riscv/mm/init.c12
-rw-r--r--include/asm-generic/audit_dir_write.h2
17 files changed, 250 insertions, 76 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 865e14f50c14..b6722c246d9c 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -22,6 +22,7 @@ config RISCV
22 select GENERIC_ATOMIC64 if !64BIT || !RISCV_ISA_A 22 select GENERIC_ATOMIC64 if !64BIT || !RISCV_ISA_A
23 select ARCH_WANT_OPTIONAL_GPIOLIB 23 select ARCH_WANT_OPTIONAL_GPIOLIB
24 select HAVE_MEMBLOCK 24 select HAVE_MEMBLOCK
25 select HAVE_MEMBLOCK_NODE_MAP
25 select HAVE_DMA_API_DEBUG 26 select HAVE_DMA_API_DEBUG
26 select HAVE_DMA_CONTIGUOUS 27 select HAVE_DMA_CONTIGUOUS
27 select HAVE_GENERIC_DMA_COHERENT 28 select HAVE_GENERIC_DMA_COHERENT
@@ -43,6 +44,10 @@ config MMU
43config ARCH_PHYS_ADDR_T_64BIT 44config ARCH_PHYS_ADDR_T_64BIT
44 def_bool y 45 def_bool y
45 46
47config ZONE_DMA32
48 bool
49 default y
50
46config ARCH_DMA_ADDR_T_64BIT 51config ARCH_DMA_ADDR_T_64BIT
47 def_bool y 52 def_bool y
48 53
@@ -55,6 +60,9 @@ config PAGE_OFFSET
55config STACKTRACE_SUPPORT 60config STACKTRACE_SUPPORT
56 def_bool y 61 def_bool y
57 62
63config TRACE_IRQFLAGS_SUPPORT
64 def_bool y
65
58config RWSEM_GENERIC_SPINLOCK 66config RWSEM_GENERIC_SPINLOCK
59 def_bool y 67 def_bool y
60 68
@@ -107,6 +115,8 @@ config ARCH_RV64I
107 bool "RV64I" 115 bool "RV64I"
108 select CPU_SUPPORTS_64BIT_KERNEL 116 select CPU_SUPPORTS_64BIT_KERNEL
109 select 64BIT 117 select 64BIT
118 select HAVE_FUNCTION_TRACER
119 select HAVE_FUNCTION_GRAPH_TRACER
110 120
111endchoice 121endchoice
112 122
diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild
index 681ac0d09314..4286a5f83876 100644
--- a/arch/riscv/include/asm/Kbuild
+++ b/arch/riscv/include/asm/Kbuild
@@ -12,7 +12,6 @@ generic-y += errno.h
12generic-y += exec.h 12generic-y += exec.h
13generic-y += fb.h 13generic-y += fb.h
14generic-y += fcntl.h 14generic-y += fcntl.h
15generic-y += ftrace.h
16generic-y += futex.h 15generic-y += futex.h
17generic-y += hardirq.h 16generic-y += hardirq.h
18generic-y += hash.h 17generic-y += hash.h
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 3c7a2c97e377..421fa3585798 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -40,15 +40,15 @@
40#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ 40#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */
41#endif 41#endif
42 42
43/* SPTBR flags */ 43/* SATP flags */
44#if __riscv_xlen == 32 44#if __riscv_xlen == 32
45#define SPTBR_PPN _AC(0x003FFFFF, UL) 45#define SATP_PPN _AC(0x003FFFFF, UL)
46#define SPTBR_MODE_32 _AC(0x80000000, UL) 46#define SATP_MODE_32 _AC(0x80000000, UL)
47#define SPTBR_MODE SPTBR_MODE_32 47#define SATP_MODE SATP_MODE_32
48#else 48#else
49#define SPTBR_PPN _AC(0x00000FFFFFFFFFFF, UL) 49#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
50#define SPTBR_MODE_39 _AC(0x8000000000000000, UL) 50#define SATP_MODE_39 _AC(0x8000000000000000, UL)
51#define SPTBR_MODE SPTBR_MODE_39 51#define SATP_MODE SATP_MODE_39
52#endif 52#endif
53 53
54/* Interrupt Enable and Interrupt Pending flags */ 54/* Interrupt Enable and Interrupt Pending flags */
diff --git a/arch/riscv/include/asm/ftrace.h b/arch/riscv/include/asm/ftrace.h
new file mode 100644
index 000000000000..66d4175eb13e
--- /dev/null
+++ b/arch/riscv/include/asm/ftrace.h
@@ -0,0 +1,10 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (C) 2017 Andes Technology Corporation */
3
4/*
5 * The graph frame test is not possible if CONFIG_FRAME_POINTER is not enabled.
6 * Check arch/riscv/kernel/mcount.S for detail.
7 */
8#if defined(CONFIG_FUNCTION_GRAPH_TRACER) && defined(CONFIG_FRAME_POINTER)
9#define HAVE_FUNCTION_GRAPH_FP_TEST
10#endif
diff --git a/arch/riscv/include/asm/mmu_context.h b/arch/riscv/include/asm/mmu_context.h
index 97424834dce2..336d60ec5698 100644
--- a/arch/riscv/include/asm/mmu_context.h
+++ b/arch/riscv/include/asm/mmu_context.h
@@ -39,16 +39,6 @@ static inline void destroy_context(struct mm_struct *mm)
39{ 39{
40} 40}
41 41
42static inline pgd_t *current_pgdir(void)
43{
44 return pfn_to_virt(csr_read(sptbr) & SPTBR_PPN);
45}
46
47static inline void set_pgdir(pgd_t *pgd)
48{
49 csr_write(sptbr, virt_to_pfn(pgd) | SPTBR_MODE);
50}
51
52/* 42/*
53 * When necessary, performs a deferred icache flush for the given MM context, 43 * When necessary, performs a deferred icache flush for the given MM context,
54 * on the local CPU. RISC-V has no direct mechanism for instruction cache 44 * on the local CPU. RISC-V has no direct mechanism for instruction cache
@@ -93,7 +83,12 @@ static inline void switch_mm(struct mm_struct *prev,
93 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 83 cpumask_clear_cpu(cpu, mm_cpumask(prev));
94 cpumask_set_cpu(cpu, mm_cpumask(next)); 84 cpumask_set_cpu(cpu, mm_cpumask(next));
95 85
96 set_pgdir(next->pgd); 86 /*
87 * Use the old spbtr name instead of using the current satp
88 * name to support binutils 2.29 which doesn't know about the
89 * privileged ISA 1.10 yet.
90 */
91 csr_write(sptbr, virt_to_pfn(next->pgd) | SATP_MODE);
97 local_flush_tlb_all(); 92 local_flush_tlb_all();
98 93
99 flush_icache_deferred(next); 94 flush_icache_deferred(next);
diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h
index 7b9c24ebdf52..7b209aec355d 100644
--- a/arch/riscv/include/asm/tlbflush.h
+++ b/arch/riscv/include/asm/tlbflush.h
@@ -36,7 +36,14 @@ static inline void local_flush_tlb_page(unsigned long addr)
36 36
37#define flush_tlb_all() local_flush_tlb_all() 37#define flush_tlb_all() local_flush_tlb_all()
38#define flush_tlb_page(vma, addr) local_flush_tlb_page(addr) 38#define flush_tlb_page(vma, addr) local_flush_tlb_page(addr)
39#define flush_tlb_range(vma, start, end) local_flush_tlb_all() 39
40static inline void flush_tlb_range(struct vm_area_struct *vma,
41 unsigned long start, unsigned long end)
42{
43 local_flush_tlb_all();
44}
45
46#define flush_tlb_mm(mm) flush_tlb_all()
40 47
41#else /* CONFIG_SMP */ 48#else /* CONFIG_SMP */
42 49
@@ -45,16 +52,13 @@ static inline void local_flush_tlb_page(unsigned long addr)
45#define flush_tlb_all() sbi_remote_sfence_vma(0, 0, -1) 52#define flush_tlb_all() sbi_remote_sfence_vma(0, 0, -1)
46#define flush_tlb_page(vma, addr) flush_tlb_range(vma, addr, 0) 53#define flush_tlb_page(vma, addr) flush_tlb_range(vma, addr, 0)
47#define flush_tlb_range(vma, start, end) \ 54#define flush_tlb_range(vma, start, end) \
48 sbi_remote_sfence_vma(0, start, (end) - (start)) 55 sbi_remote_sfence_vma(mm_cpumask((vma)->vm_mm)->bits, \
56 start, (end) - (start))
57#define flush_tlb_mm(mm) \
58 sbi_remote_sfence_vma(mm_cpumask(mm)->bits, 0, -1)
49 59
50#endif /* CONFIG_SMP */ 60#endif /* CONFIG_SMP */
51 61
52/* Flush the TLB entries of the specified mm context */
53static inline void flush_tlb_mm(struct mm_struct *mm)
54{
55 flush_tlb_all();
56}
57
58/* Flush a range of kernel pages */ 62/* Flush a range of kernel pages */
59static inline void flush_tlb_kernel_range(unsigned long start, 63static inline void flush_tlb_kernel_range(unsigned long start,
60 unsigned long end) 64 unsigned long end)
diff --git a/arch/riscv/include/asm/unistd.h b/arch/riscv/include/asm/unistd.h
index 2f704a5c4196..080fb28061de 100644
--- a/arch/riscv/include/asm/unistd.h
+++ b/arch/riscv/include/asm/unistd.h
@@ -11,7 +11,6 @@
11 * GNU General Public License for more details. 11 * GNU General Public License for more details.
12 */ 12 */
13 13
14#define __ARCH_HAVE_MMU
15#define __ARCH_WANT_SYS_CLONE 14#define __ARCH_WANT_SYS_CLONE
16#include <uapi/asm/unistd.h> 15#include <uapi/asm/unistd.h>
17#include <uapi/asm/syscalls.h> 16#include <uapi/asm/syscalls.h>
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index ab8baf7bd142..196f62ffc428 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -2,6 +2,11 @@
2# Makefile for the RISC-V Linux kernel 2# Makefile for the RISC-V Linux kernel
3# 3#
4 4
5ifdef CONFIG_FTRACE
6CFLAGS_REMOVE_ftrace.o = -pg
7CFLAGS_REMOVE_setup.o = -pg
8endif
9
5extra-y += head.o 10extra-y += head.o
6extra-y += vmlinux.lds 11extra-y += vmlinux.lds
7 12
@@ -29,5 +34,7 @@ CFLAGS_setup.o := -mcmodel=medany
29obj-$(CONFIG_SMP) += smpboot.o 34obj-$(CONFIG_SMP) += smpboot.o
30obj-$(CONFIG_SMP) += smp.o 35obj-$(CONFIG_SMP) += smp.o
31obj-$(CONFIG_MODULES) += module.o 36obj-$(CONFIG_MODULES) += module.o
37obj-$(CONFIG_FUNCTION_TRACER) += mcount.o
38obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
32 39
33clean: 40clean:
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 7404ec222406..87fc045be51f 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -78,10 +78,13 @@ _save_context:
78 REG_S x31, PT_T6(sp) 78 REG_S x31, PT_T6(sp)
79 79
80 /* 80 /*
81 * Disable FPU to detect illegal usage of 81 * Disable user-mode memory access as it should only be set in the
82 * floating point in kernel space 82 * actual user copy routines.
83 *
84 * Disable the FPU to detect illegal usage of floating point in kernel
85 * space.
83 */ 86 */
84 li t0, SR_FS 87 li t0, SR_SUM | SR_FS
85 88
86 REG_L s0, TASK_TI_USER_SP(tp) 89 REG_L s0, TASK_TI_USER_SP(tp)
87 csrrc s1, sstatus, t0 90 csrrc s1, sstatus, t0
diff --git a/arch/riscv/kernel/ftrace.c b/arch/riscv/kernel/ftrace.c
new file mode 100644
index 000000000000..d0de68d144cb
--- /dev/null
+++ b/arch/riscv/kernel/ftrace.c
@@ -0,0 +1,41 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2013 Linaro Limited
4 * Author: AKASHI Takahiro <takahiro.akashi@linaro.org>
5 * Copyright (C) 2017 Andes Technology Corporation
6 */
7
8#include <linux/ftrace.h>
9
10/*
11 * Most of this file is copied from arm64.
12 */
13void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr,
14 unsigned long frame_pointer)
15{
16 unsigned long return_hooker = (unsigned long)&return_to_handler;
17 unsigned long old;
18 struct ftrace_graph_ent trace;
19 int err;
20
21 if (unlikely(atomic_read(&current->tracing_graph_pause)))
22 return;
23
24 /*
25 * We don't suffer access faults, so no extra fault-recovery assembly
26 * is needed here.
27 */
28 old = *parent;
29
30 trace.func = self_addr;
31 trace.depth = current->curr_ret_stack + 1;
32
33 if (!ftrace_graph_entry(&trace))
34 return;
35
36 err = ftrace_push_return_trace(old, self_addr, &trace.depth,
37 frame_pointer, NULL);
38 if (err == -EBUSY)
39 return;
40 *parent = return_hooker;
41}
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 78f670d70133..226eeb190f90 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -74,15 +74,15 @@ relocate:
74 sub a1, a1, a0 74 sub a1, a1, a0
75 add ra, ra, a1 75 add ra, ra, a1
76 76
77 /* Point stvec to virtual address of intruction after sptbr write */ 77 /* Point stvec to virtual address of intruction after satp write */
78 la a0, 1f 78 la a0, 1f
79 add a0, a0, a1 79 add a0, a0, a1
80 csrw stvec, a0 80 csrw stvec, a0
81 81
82 /* Compute sptbr for kernel page tables, but don't load it yet */ 82 /* Compute satp for kernel page tables, but don't load it yet */
83 la a2, swapper_pg_dir 83 la a2, swapper_pg_dir
84 srl a2, a2, PAGE_SHIFT 84 srl a2, a2, PAGE_SHIFT
85 li a1, SPTBR_MODE 85 li a1, SATP_MODE
86 or a2, a2, a1 86 or a2, a2, a1
87 87
88 /* 88 /*
diff --git a/arch/riscv/kernel/mcount.S b/arch/riscv/kernel/mcount.S
new file mode 100644
index 000000000000..c46a778627be
--- /dev/null
+++ b/arch/riscv/kernel/mcount.S
@@ -0,0 +1,126 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (C) 2017 Andes Technology Corporation */
3
4#include <linux/init.h>
5#include <linux/linkage.h>
6#include <asm/asm.h>
7#include <asm/csr.h>
8#include <asm/unistd.h>
9#include <asm/thread_info.h>
10#include <asm/asm-offsets.h>
11#include <asm-generic/export.h>
12#include <asm/ftrace.h>
13
14 .text
15
16 .macro SAVE_ABI_STATE
17 addi sp, sp, -16
18 sd s0, 0(sp)
19 sd ra, 8(sp)
20 addi s0, sp, 16
21 .endm
22
23 /*
24 * The call to ftrace_return_to_handler would overwrite the return
25 * register if a0 was not saved.
26 */
27 .macro SAVE_RET_ABI_STATE
28 addi sp, sp, -32
29 sd s0, 16(sp)
30 sd ra, 24(sp)
31 sd a0, 8(sp)
32 addi s0, sp, 32
33 .endm
34
35 .macro STORE_ABI_STATE
36 ld ra, 8(sp)
37 ld s0, 0(sp)
38 addi sp, sp, 16
39 .endm
40
41 .macro STORE_RET_ABI_STATE
42 ld ra, 24(sp)
43 ld s0, 16(sp)
44 ld a0, 8(sp)
45 addi sp, sp, 32
46 .endm
47
48ENTRY(ftrace_stub)
49 ret
50ENDPROC(ftrace_stub)
51
52#ifdef CONFIG_FUNCTION_GRAPH_TRACER
53ENTRY(return_to_handler)
54/*
55 * On implementing the frame point test, the ideal way is to compare the
56 * s0 (frame pointer, if enabled) on entry and the sp (stack pointer) on return.
57 * However, the psABI of variable-length-argument functions does not allow this.
58 *
59 * So alternatively we check the *old* frame pointer position, that is, the
60 * value stored in -16(s0) on entry, and the s0 on return.
61 */
62#ifdef HAVE_FUNCTION_GRAPH_FP_TEST
63 mv t6, s0
64#endif
65 SAVE_RET_ABI_STATE
66#ifdef HAVE_FUNCTION_GRAPH_FP_TEST
67 mv a0, t6
68#endif
69 la t0, ftrace_return_to_handler
70 jalr t0
71 mv a1, a0
72 STORE_RET_ABI_STATE
73 jalr a1
74ENDPROC(return_to_handler)
75EXPORT_SYMBOL(return_to_handler)
76#endif
77
78ENTRY(_mcount)
79 la t4, ftrace_stub
80#ifdef CONFIG_FUNCTION_GRAPH_TRACER
81 la t0, ftrace_graph_return
82 ld t1, 0(t0)
83 bne t1, t4, do_ftrace_graph_caller
84
85 la t3, ftrace_graph_entry
86 ld t2, 0(t3)
87 la t6, ftrace_graph_entry_stub
88 bne t2, t6, do_ftrace_graph_caller
89#endif
90 la t3, ftrace_trace_function
91 ld t5, 0(t3)
92 bne t5, t4, do_trace
93 ret
94
95#ifdef CONFIG_FUNCTION_GRAPH_TRACER
96/*
97 * A pseudo representation for the function graph tracer:
98 * prepare_to_return(&ra_to_caller_of_caller, ra_to_caller)
99 */
100do_ftrace_graph_caller:
101 addi a0, s0, -8
102 mv a1, ra
103#ifdef HAVE_FUNCTION_GRAPH_FP_TEST
104 ld a2, -16(s0)
105#endif
106 SAVE_ABI_STATE
107 la t0, prepare_ftrace_return
108 jalr t0
109 STORE_ABI_STATE
110 ret
111#endif
112
113/*
114 * A pseudo representation for the function tracer:
115 * (*ftrace_trace_function)(ra_to_caller, ra_to_caller_of_caller)
116 */
117do_trace:
118 ld a1, -8(s0)
119 mv a0, ra
120
121 SAVE_ABI_STATE
122 jalr t5
123 STORE_ABI_STATE
124 ret
125ENDPROC(_mcount)
126EXPORT_SYMBOL(_mcount)
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index cb7b0c63014e..09f7064e898c 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -49,10 +49,6 @@ struct screen_info screen_info = {
49}; 49};
50#endif 50#endif
51 51
52#ifdef CONFIG_CMDLINE_BOOL
53static char __initdata builtin_cmdline[COMMAND_LINE_SIZE] = CONFIG_CMDLINE;
54#endif /* CONFIG_CMDLINE_BOOL */
55
56unsigned long va_pa_offset; 52unsigned long va_pa_offset;
57EXPORT_SYMBOL(va_pa_offset); 53EXPORT_SYMBOL(va_pa_offset);
58unsigned long pfn_base; 54unsigned long pfn_base;
@@ -153,25 +149,6 @@ void __init sbi_save(unsigned int hartid, void *dtb)
153 early_init_dt_scan(__va(dtb)); 149 early_init_dt_scan(__va(dtb));
154} 150}
155 151
156/*
157 * Allow the user to manually add a memory region (in case DTS is broken);
158 * "mem_end=nn[KkMmGg]"
159 */
160static int __init mem_end_override(char *p)
161{
162 resource_size_t base, end;
163
164 if (!p)
165 return -EINVAL;
166 base = (uintptr_t) __pa(PAGE_OFFSET);
167 end = memparse(p, &p) & PMD_MASK;
168 if (end == 0)
169 return -EINVAL;
170 memblock_add(base, end - base);
171 return 0;
172}
173early_param("mem_end", mem_end_override);
174
175static void __init setup_bootmem(void) 152static void __init setup_bootmem(void)
176{ 153{
177 struct memblock_region *reg; 154 struct memblock_region *reg;
@@ -204,22 +181,19 @@ static void __init setup_bootmem(void)
204 early_init_fdt_scan_reserved_mem(); 181 early_init_fdt_scan_reserved_mem();
205 memblock_allow_resize(); 182 memblock_allow_resize();
206 memblock_dump_all(); 183 memblock_dump_all();
184
185 for_each_memblock(memory, reg) {
186 unsigned long start_pfn = memblock_region_memory_base_pfn(reg);
187 unsigned long end_pfn = memblock_region_memory_end_pfn(reg);
188
189 memblock_set_node(PFN_PHYS(start_pfn),
190 PFN_PHYS(end_pfn - start_pfn),
191 &memblock.memory, 0);
192 }
207} 193}
208 194
209void __init setup_arch(char **cmdline_p) 195void __init setup_arch(char **cmdline_p)
210{ 196{
211#ifdef CONFIG_CMDLINE_BOOL
212#ifdef CONFIG_CMDLINE_OVERRIDE
213 strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
214#else
215 if (builtin_cmdline[0] != '\0') {
216 /* Append bootloader command line to built-in */
217 strlcat(builtin_cmdline, " ", COMMAND_LINE_SIZE);
218 strlcat(builtin_cmdline, boot_command_line, COMMAND_LINE_SIZE);
219 strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
220 }
221#endif /* CONFIG_CMDLINE_OVERRIDE */
222#endif /* CONFIG_CMDLINE_BOOL */
223 *cmdline_p = boot_command_line; 197 *cmdline_p = boot_command_line;
224 198
225 parse_early_param(); 199 parse_early_param();
diff --git a/arch/riscv/kernel/vdso.c b/arch/riscv/kernel/vdso.c
index e8a178df8144..582cb153eb24 100644
--- a/arch/riscv/kernel/vdso.c
+++ b/arch/riscv/kernel/vdso.c
@@ -74,7 +74,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm,
74 74
75 down_write(&mm->mmap_sem); 75 down_write(&mm->mmap_sem);
76 vdso_base = get_unmapped_area(NULL, 0, vdso_len, 0, 0); 76 vdso_base = get_unmapped_area(NULL, 0, vdso_len, 0, 0);
77 if (unlikely(IS_ERR_VALUE(vdso_base))) { 77 if (IS_ERR_VALUE(vdso_base)) {
78 ret = vdso_base; 78 ret = vdso_base;
79 goto end; 79 goto end;
80 } 80 }
diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c
index ceebfc29305b..148c98ca9b45 100644
--- a/arch/riscv/mm/fault.c
+++ b/arch/riscv/mm/fault.c
@@ -238,6 +238,10 @@ vmalloc_fault:
238 * Do _not_ use "tsk->active_mm->pgd" here. 238 * Do _not_ use "tsk->active_mm->pgd" here.
239 * We might be inside an interrupt in the middle 239 * We might be inside an interrupt in the middle
240 * of a task switch. 240 * of a task switch.
241 *
242 * Note: Use the old spbtr name instead of using the current
243 * satp name to support binutils 2.29 which doesn't know about
244 * the privileged ISA 1.10 yet.
241 */ 245 */
242 index = pgd_index(addr); 246 index = pgd_index(addr);
243 pgd = (pgd_t *)pfn_to_virt(csr_read(sptbr)) + index; 247 pgd = (pgd_t *)pfn_to_virt(csr_read(sptbr)) + index;
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index 9f4bee5e51fd..c77df8142be2 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -17,6 +17,7 @@
17#include <linux/initrd.h> 17#include <linux/initrd.h>
18#include <linux/memblock.h> 18#include <linux/memblock.h>
19#include <linux/swap.h> 19#include <linux/swap.h>
20#include <linux/sizes.h>
20 21
21#include <asm/tlbflush.h> 22#include <asm/tlbflush.h>
22#include <asm/sections.h> 23#include <asm/sections.h>
@@ -25,11 +26,12 @@
25 26
26static void __init zone_sizes_init(void) 27static void __init zone_sizes_init(void)
27{ 28{
28 unsigned long zones_size[MAX_NR_ZONES]; 29 unsigned long max_zone_pfns[MAX_NR_ZONES] = { 0, };
29 30
30 memset(zones_size, 0, sizeof(zones_size)); 31 max_zone_pfns[ZONE_DMA32] = PFN_DOWN(min(4UL * SZ_1G, max_low_pfn));
31 zones_size[ZONE_NORMAL] = max_mapnr; 32 max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
32 free_area_init_node(0, zones_size, pfn_base, NULL); 33
34 free_area_init_nodes(max_zone_pfns);
33} 35}
34 36
35void setup_zero_page(void) 37void setup_zero_page(void)
@@ -39,8 +41,6 @@ void setup_zero_page(void)
39 41
40void __init paging_init(void) 42void __init paging_init(void)
41{ 43{
42 init_mm.pgd = (pgd_t *)pfn_to_virt(csr_read(sptbr));
43
44 setup_zero_page(); 44 setup_zero_page();
45 local_flush_tlb_all(); 45 local_flush_tlb_all();
46 zone_sizes_init(); 46 zone_sizes_init();
diff --git a/include/asm-generic/audit_dir_write.h b/include/asm-generic/audit_dir_write.h
index da09fb986459..dd5a9dd7a102 100644
--- a/include/asm-generic/audit_dir_write.h
+++ b/include/asm-generic/audit_dir_write.h
@@ -27,7 +27,9 @@ __NR_mknod,
27__NR_mkdirat, 27__NR_mkdirat,
28__NR_mknodat, 28__NR_mknodat,
29__NR_unlinkat, 29__NR_unlinkat,
30#ifdef __NR_renameat
30__NR_renameat, 31__NR_renameat,
32#endif
31__NR_linkat, 33__NR_linkat,
32__NR_symlinkat, 34__NR_symlinkat,
33#endif 35#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 01:20:50 -0400