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authorRomain Perier <romain.perier@free-electrons.com>2016-12-08 09:58:45 -0500
committerMark Brown <broonie@kernel.org>2016-12-08 11:05:34 -0500
commit4049537742b3ed39fac4da10d31f3171a2ee9a3e (patch)
treea5b0ddbf42b0c4dc5235bda5efd2458925537e48
parent1001354ca34179f3db924eb66672442a173147dc (diff)
spi: armada-3700: Add documentation for the Armada 3700 SPI Controller
This adds the devicetree bindings documentation for the SPI controller present in the Marvell Armada 3700 SoCs. Signed-off-by: Romain Perier <romain.perier@free-electrons.com> Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/spi/spi-armada-3700.txt25
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diff --git a/Documentation/devicetree/bindings/spi/spi-armada-3700.txt b/Documentation/devicetree/bindings/spi/spi-armada-3700.txt
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1* Marvell Armada 3700 SPI Controller
2
3Required Properties:
4
5- compatible: should be "marvell,armada-3700-spi"
6- reg: physical base address of the controller and length of memory mapped
7 region.
8- interrupts: The interrupt number. The interrupt specifier format depends on
9 the interrupt controller and of its driver.
10- clocks: Must contain the clock source, usually from the North Bridge clocks.
11- num-cs: The number of chip selects that is supported by this SPI Controller
12- #address-cells: should be 1.
13- #size-cells: should be 0.
14
15Example:
16
17 spi0: spi@10600 {
18 compatible = "marvell,armada-3700-spi";
19 #address-cells = <1>;
20 #size-cells = <0>;
21 reg = <0x10600 0x5d>;
22 clocks = <&nb_perih_clk 7>;
23 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
24 num-cs = <4>;
25 };