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authorPhilipp Zabel <p.zabel@pengutronix.de>2017-10-09 06:03:30 -0400
committerLucas Stach <l.stach@pengutronix.de>2017-10-10 06:09:34 -0400
commit4046217954d4e79d57d34c56ce42dec4f87e2ce9 (patch)
treec20b4b7d0a6579e2f9fcd7a46b0a7b29f44fedf0
parent13cde9f4c62accdb35f769501ae951ecd75cccc9 (diff)
drm/etnaviv: reduce reset delay
After reset assertion, we only have to wait for the reset signals to propagate through the GPU before deasserting the reset again. A few hundred clock cycles should be more than enough. Replace the msleep(1), which can actually take about 30 ms on i.MX6Q in some configurations, with an usleep_range of a few microseconds. If the delay was too short, the FE would not be idle afterwards, and the reset would be retried. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
-rw-r--r--drivers/gpu/drm/etnaviv/etnaviv_gpu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index 3e0fcc1fafb5..95ee479c95cb 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -456,7 +456,7 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
456 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 456 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
457 457
458 /* wait for reset. */ 458 /* wait for reset. */
459 msleep(1); 459 usleep_range(10, 20);
460 460
461 /* reset soft reset bit. */ 461 /* reset soft reset bit. */
462 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 462 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;