diff options
author | Thierry Reding <treding@nvidia.com> | 2015-07-21 10:48:19 -0400 |
---|---|---|
committer | Thierry Reding <treding@nvidia.com> | 2016-07-01 08:42:07 -0400 |
commit | 402f6bcd94fa3437b833931da8e1fbfc1fb6c444 (patch) | |
tree | 35d98bbbf826c31d0ca1ebf9b2ee437baefb1aba | |
parent | a198359e39c0e47a995d8e88638d5738ae4cfbe2 (diff) |
drm/tegra: sor: Split out tegra_sor_apply_config()
This function is useful in both eDP and DP modes, so split it out in
anticipation of adding DP support.
Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r-- | drivers/gpu/drm/tegra/sor.c | 77 |
1 files changed, 43 insertions, 34 deletions
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index fb536c1f5111..5d9a9f2ba4de 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c | |||
@@ -678,6 +678,46 @@ static int tegra_sor_compute_config(struct tegra_sor *sor, | |||
678 | return 0; | 678 | return 0; |
679 | } | 679 | } |
680 | 680 | ||
681 | static void tegra_sor_apply_config(struct tegra_sor *sor, | ||
682 | const struct tegra_sor_config *config) | ||
683 | { | ||
684 | u32 value; | ||
685 | |||
686 | value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); | ||
687 | value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; | ||
688 | value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size); | ||
689 | tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); | ||
690 | |||
691 | value = tegra_sor_readl(sor, SOR_DP_CONFIG0); | ||
692 | value &= ~SOR_DP_CONFIG_WATERMARK_MASK; | ||
693 | value |= SOR_DP_CONFIG_WATERMARK(config->watermark); | ||
694 | |||
695 | value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; | ||
696 | value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count); | ||
697 | |||
698 | value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; | ||
699 | value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac); | ||
700 | |||
701 | if (config->active_polarity) | ||
702 | value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; | ||
703 | else | ||
704 | value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; | ||
705 | |||
706 | value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; | ||
707 | value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; | ||
708 | tegra_sor_writel(sor, value, SOR_DP_CONFIG0); | ||
709 | |||
710 | value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); | ||
711 | value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; | ||
712 | value |= config->hblank_symbols & 0xffff; | ||
713 | tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); | ||
714 | |||
715 | value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); | ||
716 | value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; | ||
717 | value |= config->vblank_symbols & 0xffff; | ||
718 | tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); | ||
719 | } | ||
720 | |||
681 | static int tegra_sor_detach(struct tegra_sor *sor) | 721 | static int tegra_sor_detach(struct tegra_sor *sor) |
682 | { | 722 | { |
683 | unsigned long value, timeout; | 723 | unsigned long value, timeout; |
@@ -1393,13 +1433,11 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) | |||
1393 | value |= drm_dp_link_rate_to_bw_code(link.rate) << 2; | 1433 | value |= drm_dp_link_rate_to_bw_code(link.rate) << 2; |
1394 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); | 1434 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); |
1395 | 1435 | ||
1396 | /* set linkctl */ | 1436 | tegra_sor_apply_config(sor, &config); |
1437 | |||
1438 | /* enable link */ | ||
1397 | value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); | 1439 | value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); |
1398 | value |= SOR_DP_LINKCTL_ENABLE; | 1440 | value |= SOR_DP_LINKCTL_ENABLE; |
1399 | |||
1400 | value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; | ||
1401 | value |= SOR_DP_LINKCTL_TU_SIZE(config.tu_size); | ||
1402 | |||
1403 | value |= SOR_DP_LINKCTL_ENHANCED_FRAME; | 1441 | value |= SOR_DP_LINKCTL_ENHANCED_FRAME; |
1404 | tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); | 1442 | tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); |
1405 | 1443 | ||
@@ -1412,35 +1450,6 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) | |||
1412 | 1450 | ||
1413 | tegra_sor_writel(sor, value, SOR_DP_TPG); | 1451 | tegra_sor_writel(sor, value, SOR_DP_TPG); |
1414 | 1452 | ||
1415 | value = tegra_sor_readl(sor, SOR_DP_CONFIG0); | ||
1416 | value &= ~SOR_DP_CONFIG_WATERMARK_MASK; | ||
1417 | value |= SOR_DP_CONFIG_WATERMARK(config.watermark); | ||
1418 | |||
1419 | value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; | ||
1420 | value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config.active_count); | ||
1421 | |||
1422 | value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; | ||
1423 | value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config.active_frac); | ||
1424 | |||
1425 | if (config.active_polarity) | ||
1426 | value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; | ||
1427 | else | ||
1428 | value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; | ||
1429 | |||
1430 | value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; | ||
1431 | value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; | ||
1432 | tegra_sor_writel(sor, value, SOR_DP_CONFIG0); | ||
1433 | |||
1434 | value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); | ||
1435 | value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; | ||
1436 | value |= config.hblank_symbols & 0xffff; | ||
1437 | tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); | ||
1438 | |||
1439 | value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); | ||
1440 | value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; | ||
1441 | value |= config.vblank_symbols & 0xffff; | ||
1442 | tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); | ||
1443 | |||
1444 | /* enable pad calibration logic */ | 1453 | /* enable pad calibration logic */ |
1445 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); | 1454 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
1446 | value |= SOR_DP_PADCTL_PAD_CAL_PD; | 1455 | value |= SOR_DP_PADCTL_PAD_CAL_PD; |