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authorLinus Torvalds <torvalds@linux-foundation.org>2016-05-28 19:41:39 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2016-05-28 19:41:39 -0400
commit4029632c344142e0e92da3ff4937cd41bd647bb4 (patch)
treee7c737913a21b65f0120cdbea6aa0ecc20608aad
parentd66492bce151ac4c477cf1de97171777c0d62d20 (diff)
parenta8c5ddf08f1f7e587240c44f82f4762bd37df1f3 (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull more MIPS updates from Ralf Baechle: "This is the secondnd batch of MIPS patches for 4.7. Summary: CPS: - Copy EVA configuration when starting secondary VPs. EIC: - Clear Status IPL. Lasat: - Fix a few off by one bugs. lib: - Mark intrinsics notrace. Not only are the intrinsics uninteresting, it would cause infinite recursion. MAINTAINERS: - Add file patterns for MIPS BRCM device tree bindings. - Add file patterns for mips device tree bindings. MT7628: - Fix MT7628 pinmux typos. - wled_an pinmux gpio. - EPHY LEDs pinmux support. Pistachio: - Enable KASLR VDSO: - Build microMIPS VDSO for microMIPS kernels. - Fix aliasing warning by building with `-fno-strict-aliasing' for debugging but also tracing them might result in recursion. Misc: - Add missing FROZEN hotplug notifier transitions. - Fix clk binding example for varioius PIC32 devices. - Fix cpu interrupt controller node-names in the DT files. - Fix XPA CPU feature separation. - Fix write_gc0_* macros when writing zero. - Add inline asm encoding helpers. - Add missing VZ accessor microMIPS encodings. - Fix little endian microMIPS MSA encodings. - Add 64-bit HTW fields and fix its configuration. - Fix sigreturn via VDSO on microMIPS kernel. - Lots of typo fixes. - Add definitions of SegCtl registers and use them" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (49 commits) MIPS: Add missing FROZEN hotplug notifier transitions MIPS: Build microMIPS VDSO for microMIPS kernels MIPS: Fix sigreturn via VDSO on microMIPS kernel MIPS: devicetree: fix cpu interrupt controller node-names MIPS: VDSO: Build with `-fno-strict-aliasing' MIPS: Pistachio: Enable KASLR MIPS: lib: Mark intrinsics notrace MIPS: Fix 64-bit HTW configuration MIPS: Add 64-bit HTW fields MAINTAINERS: Add file patterns for mips device tree bindings MAINTAINERS: Add file patterns for mips brcm device tree bindings MIPS: Simplify DSP instruction encoding macros MIPS: Add missing tlbinvf/XPA microMIPS encodings MIPS: Fix little endian microMIPS MSA encodings MIPS: Add missing VZ accessor microMIPS encodings MIPS: Add inline asm encoding helpers MIPS: Spelling fix lets -> let's MIPS: VR41xx: Fix typo MIPS: oprofile: Fix typo MIPS: math-emu: Fix typo ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt2
-rw-r--r--Documentation/devicetree/bindings/mips/cpu_irq.txt2
-rw-r--r--Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt2
-rw-r--r--Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt2
-rw-r--r--Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt2
-rw-r--r--Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt4
-rw-r--r--Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt4
-rw-r--r--MAINTAINERS2
-rw-r--r--arch/mips/Kconfig1
-rw-r--r--arch/mips/boot/dts/ingenic/jz4740.dtsi2
-rw-r--r--arch/mips/boot/dts/ralink/mt7620a.dtsi2
-rw-r--r--arch/mips/boot/dts/ralink/rt2880.dtsi2
-rw-r--r--arch/mips/boot/dts/ralink/rt3050.dtsi2
-rw-r--r--arch/mips/boot/dts/ralink/rt3883.dtsi2
-rw-r--r--arch/mips/boot/dts/xilfpga/nexys4ddr.dts2
-rw-r--r--arch/mips/cavium-octeon/smp.c2
-rw-r--r--arch/mips/include/asm/asmmacro.h99
-rw-r--r--arch/mips/include/asm/hazards.h8
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h2
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio-au1300.h2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h2
-rw-r--r--arch/mips/include/asm/mach-ip27/dma-coherence.h2
-rw-r--r--arch/mips/include/asm/mach-ip32/dma-coherence.h2
-rw-r--r--arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h2
-rw-r--r--arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h2
-rw-r--r--arch/mips/include/asm/mach-loongson64/loongson_hwmon.h2
-rw-r--r--arch/mips/include/asm/mach-malta/kernel-entry-init.h6
-rw-r--r--arch/mips/include/asm/mips_mt.h2
-rw-r--r--arch/mips/include/asm/mipsregs.h188
-rw-r--r--arch/mips/include/asm/msa.h21
-rw-r--r--arch/mips/include/asm/octeon/cvmx-cmd-queue.h2
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-board.h2
-rw-r--r--arch/mips/include/asm/octeon/cvmx-ipd.h2
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pow.h2
-rw-r--r--arch/mips/include/asm/sgi/hpc3.h2
-rw-r--r--arch/mips/kernel/branch.c4
-rw-r--r--arch/mips/kernel/cps-vec.S15
-rw-r--r--arch/mips/kernel/cpu-probe.c4
-rw-r--r--arch/mips/kernel/elf.c2
-rw-r--r--arch/mips/kernel/irq.c3
-rw-r--r--arch/mips/kernel/mips-r2-to-r6-emul.c2
-rw-r--r--arch/mips/kernel/process.c2
-rw-r--r--arch/mips/kernel/signal.c8
-rw-r--r--arch/mips/kernel/smp-cps.c8
-rw-r--r--arch/mips/lasat/picvue_proc.c4
-rw-r--r--arch/mips/lib/ashldi3.c2
-rw-r--r--arch/mips/lib/ashrdi3.c2
-rw-r--r--arch/mips/lib/bswapdi.c2
-rw-r--r--arch/mips/lib/bswapsi.c2
-rw-r--r--arch/mips/lib/cmpdi2.c2
-rw-r--r--arch/mips/lib/lshrdi3.c2
-rw-r--r--arch/mips/lib/memcpy.S2
-rw-r--r--arch/mips/lib/ucmpdi2.c2
-rw-r--r--arch/mips/loongson64/loongson-3/hpet.c2
-rw-r--r--arch/mips/math-emu/dsemul.c4
-rw-r--r--arch/mips/mm/tlbex.c22
-rw-r--r--arch/mips/oprofile/op_impl.h2
-rw-r--r--arch/mips/pci/ops-bridge.c4
-rw-r--r--arch/mips/pistachio/init.c8
-rw-r--r--arch/mips/ralink/mt7620.c112
-rw-r--r--arch/mips/sgi-ip27/ip27-hubio.c2
-rw-r--r--arch/mips/sgi-ip27/ip27-nmi.c2
-rw-r--r--arch/mips/sgi-ip27/ip27-xtalk.c2
-rw-r--r--arch/mips/sni/rm200.c2
-rw-r--r--arch/mips/vdso/Makefile4
-rw-r--r--arch/mips/vr41xx/common/cmu.c2
-rw-r--r--drivers/irqchip/irq-mips-gic.c10
67 files changed, 373 insertions, 258 deletions
diff --git a/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
index ef3752889496..dd031fc93b55 100644
--- a/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
@@ -33,7 +33,7 @@ gpio0: gpio0@1f860000 {
33 gpio-controller; 33 gpio-controller;
34 interrupt-controller; 34 interrupt-controller;
35 #interrupt-cells = <2>; 35 #interrupt-cells = <2>;
36 clocks = <&PBCLK4>; 36 clocks = <&rootclk PB4CLK>;
37 microchip,gpio-bank = <0>; 37 microchip,gpio-bank = <0>;
38 gpio-ranges = <&pic32_pinctrl 0 0 16>; 38 gpio-ranges = <&pic32_pinctrl 0 0 16>;
39}; 39};
diff --git a/Documentation/devicetree/bindings/mips/cpu_irq.txt b/Documentation/devicetree/bindings/mips/cpu_irq.txt
index fc149f326dae..f080f06da6d8 100644
--- a/Documentation/devicetree/bindings/mips/cpu_irq.txt
+++ b/Documentation/devicetree/bindings/mips/cpu_irq.txt
@@ -13,7 +13,7 @@ Required properties:
13- compatible : Should be "mti,cpu-interrupt-controller" 13- compatible : Should be "mti,cpu-interrupt-controller"
14 14
15Example devicetree: 15Example devicetree:
16 cpu-irq: cpu-irq@0 { 16 cpu-irq: cpu-irq {
17 #address-cells = <0>; 17 #address-cells = <0>;
18 18
19 interrupt-controller; 19 interrupt-controller;
diff --git a/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt b/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt
index 71ad57e050b1..3149297b3933 100644
--- a/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt
+++ b/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt
@@ -20,7 +20,7 @@ Example:
20 compatible = "microchip,pic32mzda-sdhci"; 20 compatible = "microchip,pic32mzda-sdhci";
21 reg = <0x1f8ec000 0x100>; 21 reg = <0x1f8ec000 0x100>;
22 interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; 22 interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
23 clocks = <&REFCLKO4>, <&PBCLK5>; 23 clocks = <&rootclk REF4CLK>, <&rootclk PB5CLK>;
24 clock-names = "base_clk", "sys_clk"; 24 clock-names = "base_clk", "sys_clk";
25 bus-width = <4>; 25 bus-width = <4>;
26 cap-sd-highspeed; 26 cap-sd-highspeed;
diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
index 4b5efa51bec7..29b72e303ebf 100644
--- a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
@@ -34,7 +34,7 @@ pic32_pinctrl: pinctrl@1f801400{
34 #size-cells = <1>; 34 #size-cells = <1>;
35 compatible = "microchip,pic32mzda-pinctrl"; 35 compatible = "microchip,pic32mzda-pinctrl";
36 reg = <0x1f801400 0x400>; 36 reg = <0x1f801400 0x400>;
37 clocks = <&PBCLK1>; 37 clocks = <&rootclk PB1CLK>;
38 38
39 pinctrl_uart2: pinctrl_uart2 { 39 pinctrl_uart2: pinctrl_uart2 {
40 uart2-tx { 40 uart2-tx {
diff --git a/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt b/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt
index 65b38bf60ae0..7a34345d0ca3 100644
--- a/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt
+++ b/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt
@@ -20,7 +20,7 @@ Example:
20 interrupts = <112 IRQ_TYPE_LEVEL_HIGH>, 20 interrupts = <112 IRQ_TYPE_LEVEL_HIGH>,
21 <113 IRQ_TYPE_LEVEL_HIGH>, 21 <113 IRQ_TYPE_LEVEL_HIGH>,
22 <114 IRQ_TYPE_LEVEL_HIGH>; 22 <114 IRQ_TYPE_LEVEL_HIGH>;
23 clocks = <&PBCLK2>; 23 clocks = <&rootclk PB2CLK>;
24 pinctrl-names = "default"; 24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_uart1 25 pinctrl-0 = <&pinctrl_uart1
26 &pinctrl_uart1_cts 26 &pinctrl_uart1_cts
diff --git a/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt b/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt
index 852f694f3177..49485f831373 100644
--- a/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt
+++ b/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt
@@ -8,12 +8,12 @@ Required properties:
8- compatible: must be "microchip,pic32mzda-dmt". 8- compatible: must be "microchip,pic32mzda-dmt".
9- reg: physical base address of the controller and length of memory mapped 9- reg: physical base address of the controller and length of memory mapped
10 region. 10 region.
11- clocks: phandle of parent clock (should be &PBCLK7). 11- clocks: phandle of source clk. Should be <&rootclk PB7CLK>.
12 12
13Example: 13Example:
14 14
15 watchdog@1f800a00 { 15 watchdog@1f800a00 {
16 compatible = "microchip,pic32mzda-dmt"; 16 compatible = "microchip,pic32mzda-dmt";
17 reg = <0x1f800a00 0x80>; 17 reg = <0x1f800a00 0x80>;
18 clocks = <&PBCLK7>; 18 clocks = <&rootclk PB7CLK>;
19 }; 19 };
diff --git a/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt b/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt
index d1401030e75c..f03a29a1b323 100644
--- a/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt
@@ -7,12 +7,12 @@ Required properties:
7- compatible: must be "microchip,pic32mzda-wdt". 7- compatible: must be "microchip,pic32mzda-wdt".
8- reg: physical base address of the controller and length of memory mapped 8- reg: physical base address of the controller and length of memory mapped
9 region. 9 region.
10- clocks: phandle of source clk. should be <&LPRC> clk. 10- clocks: phandle of source clk. Should be <&rootclk LPRCCLK>.
11 11
12Example: 12Example:
13 13
14 watchdog@1f800800 { 14 watchdog@1f800800 {
15 compatible = "microchip,pic32mzda-wdt"; 15 compatible = "microchip,pic32mzda-wdt";
16 reg = <0x1f800800 0x200>; 16 reg = <0x1f800800 0x200>;
17 clocks = <&LPRC>; 17 clocks = <&rootclk LPRCCLK>;
18 }; 18 };
diff --git a/MAINTAINERS b/MAINTAINERS
index 216165a1384d..7304d2e37a98 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2505,6 +2505,7 @@ M: Hauke Mehrtens <hauke@hauke-m.de>
2505M: Rafał Miłecki <zajec5@gmail.com> 2505M: Rafał Miłecki <zajec5@gmail.com>
2506L: linux-mips@linux-mips.org 2506L: linux-mips@linux-mips.org
2507S: Maintained 2507S: Maintained
2508F: Documentation/devicetree/bindings/mips/brcm/
2508F: arch/mips/bcm47xx/* 2509F: arch/mips/bcm47xx/*
2509F: arch/mips/include/asm/mach-bcm47xx/* 2510F: arch/mips/include/asm/mach-bcm47xx/*
2510 2511
@@ -7521,6 +7522,7 @@ W: http://www.linux-mips.org/
7521T: git git://git.linux-mips.org/pub/scm/ralf/linux.git 7522T: git git://git.linux-mips.org/pub/scm/ralf/linux.git
7522Q: http://patchwork.linux-mips.org/project/linux-mips/list/ 7523Q: http://patchwork.linux-mips.org/project/linux-mips/list/
7523S: Supported 7524S: Supported
7525F: Documentation/devicetree/bindings/mips/
7524F: Documentation/mips/ 7526F: Documentation/mips/
7525F: arch/mips/ 7527F: arch/mips/
7526 7528
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 46938847e794..ac91939b9b75 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -398,6 +398,7 @@ config MACH_PISTACHIO
398 select SYS_SUPPORTS_LITTLE_ENDIAN 398 select SYS_SUPPORTS_LITTLE_ENDIAN
399 select SYS_SUPPORTS_MIPS_CPS 399 select SYS_SUPPORTS_MIPS_CPS
400 select SYS_SUPPORTS_MULTITHREADING 400 select SYS_SUPPORTS_MULTITHREADING
401 select SYS_SUPPORTS_RELOCATABLE
401 select SYS_SUPPORTS_ZBOOT 402 select SYS_SUPPORTS_ZBOOT
402 select SYS_HAS_EARLY_PRINTK 403 select SYS_HAS_EARLY_PRINTK
403 select USE_GENERIC_EARLY_PRINTK_8250 404 select USE_GENERIC_EARLY_PRINTK_8250
diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi b/arch/mips/boot/dts/ingenic/jz4740.dtsi
index 4a9c8f2a72d6..f6ae6ed9c4b1 100644
--- a/arch/mips/boot/dts/ingenic/jz4740.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi
@@ -5,7 +5,7 @@
5 #size-cells = <1>; 5 #size-cells = <1>;
6 compatible = "ingenic,jz4740"; 6 compatible = "ingenic,jz4740";
7 7
8 cpuintc: interrupt-controller@0 { 8 cpuintc: interrupt-controller {
9 #address-cells = <0>; 9 #address-cells = <0>;
10 #interrupt-cells = <1>; 10 #interrupt-cells = <1>;
11 interrupt-controller; 11 interrupt-controller;
diff --git a/arch/mips/boot/dts/ralink/mt7620a.dtsi b/arch/mips/boot/dts/ralink/mt7620a.dtsi
index 08bf24fefe9f..793c0c7ca921 100644
--- a/arch/mips/boot/dts/ralink/mt7620a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7620a.dtsi
@@ -9,7 +9,7 @@
9 }; 9 };
10 }; 10 };
11 11
12 cpuintc: cpuintc@0 { 12 cpuintc: cpuintc {
13 #address-cells = <0>; 13 #address-cells = <0>;
14 #interrupt-cells = <1>; 14 #interrupt-cells = <1>;
15 interrupt-controller; 15 interrupt-controller;
diff --git a/arch/mips/boot/dts/ralink/rt2880.dtsi b/arch/mips/boot/dts/ralink/rt2880.dtsi
index 182afde2f2e1..fb2faef0ab79 100644
--- a/arch/mips/boot/dts/ralink/rt2880.dtsi
+++ b/arch/mips/boot/dts/ralink/rt2880.dtsi
@@ -9,7 +9,7 @@
9 }; 9 };
10 }; 10 };
11 11
12 cpuintc: cpuintc@0 { 12 cpuintc: cpuintc {
13 #address-cells = <0>; 13 #address-cells = <0>;
14 #interrupt-cells = <1>; 14 #interrupt-cells = <1>;
15 interrupt-controller; 15 interrupt-controller;
diff --git a/arch/mips/boot/dts/ralink/rt3050.dtsi b/arch/mips/boot/dts/ralink/rt3050.dtsi
index e3203d414fee..d3cb57f985da 100644
--- a/arch/mips/boot/dts/ralink/rt3050.dtsi
+++ b/arch/mips/boot/dts/ralink/rt3050.dtsi
@@ -9,7 +9,7 @@
9 }; 9 };
10 }; 10 };
11 11
12 cpuintc: cpuintc@0 { 12 cpuintc: cpuintc {
13 #address-cells = <0>; 13 #address-cells = <0>;
14 #interrupt-cells = <1>; 14 #interrupt-cells = <1>;
15 interrupt-controller; 15 interrupt-controller;
diff --git a/arch/mips/boot/dts/ralink/rt3883.dtsi b/arch/mips/boot/dts/ralink/rt3883.dtsi
index 3b131dd0d5ac..3d6fc9afdaf6 100644
--- a/arch/mips/boot/dts/ralink/rt3883.dtsi
+++ b/arch/mips/boot/dts/ralink/rt3883.dtsi
@@ -9,7 +9,7 @@
9 }; 9 };
10 }; 10 };
11 11
12 cpuintc: cpuintc@0 { 12 cpuintc: cpuintc {
13 #address-cells = <0>; 13 #address-cells = <0>;
14 #interrupt-cells = <1>; 14 #interrupt-cells = <1>;
15 interrupt-controller; 15 interrupt-controller;
diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
index 686ebd11386d..48d21127c3f3 100644
--- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
+++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
@@ -10,7 +10,7 @@
10 reg = <0x0 0x08000000>; 10 reg = <0x0 0x08000000>;
11 }; 11 };
12 12
13 cpuintc: interrupt-controller@0 { 13 cpuintc: interrupt-controller {
14 #address-cells = <0>; 14 #address-cells = <0>;
15 #interrupt-cells = <1>; 15 #interrupt-cells = <1>;
16 interrupt-controller; 16 interrupt-controller;
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index dff88aa7e377..33aab89259f3 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -384,7 +384,7 @@ static int octeon_cpu_callback(struct notifier_block *nfb,
384{ 384{
385 unsigned int cpu = (unsigned long)hcpu; 385 unsigned int cpu = (unsigned long)hcpu;
386 386
387 switch (action) { 387 switch (action & ~CPU_TASKS_FROZEN) {
388 case CPU_UP_PREPARE: 388 case CPU_UP_PREPARE:
389 octeon_update_boot_vector(cpu); 389 octeon_update_boot_vector(cpu);
390 break; 390 break;
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
index 6741673c92ca..56584a659183 100644
--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -19,6 +19,28 @@
19#include <asm/asmmacro-64.h> 19#include <asm/asmmacro-64.h>
20#endif 20#endif
21 21
22/*
23 * Helper macros for generating raw instruction encodings.
24 */
25#ifdef CONFIG_CPU_MICROMIPS
26 .macro insn32_if_mm enc
27 .insn
28 .hword ((\enc) >> 16)
29 .hword ((\enc) & 0xffff)
30 .endm
31
32 .macro insn_if_mips enc
33 .endm
34#else
35 .macro insn32_if_mm enc
36 .endm
37
38 .macro insn_if_mips enc
39 .insn
40 .word (\enc)
41 .endm
42#endif
43
22#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) 44#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
23 .macro local_irq_enable reg=t0 45 .macro local_irq_enable reg=t0
24 ei 46 ei
@@ -341,38 +363,6 @@
341 .endm 363 .endm
342#else 364#else
343 365
344#ifdef CONFIG_CPU_MICROMIPS
345#define CFC_MSA_INSN 0x587e0056
346#define CTC_MSA_INSN 0x583e0816
347#define LDB_MSA_INSN 0x58000807
348#define LDH_MSA_INSN 0x58000817
349#define LDW_MSA_INSN 0x58000827
350#define LDD_MSA_INSN 0x58000837
351#define STB_MSA_INSN 0x5800080f
352#define STH_MSA_INSN 0x5800081f
353#define STW_MSA_INSN 0x5800082f
354#define STD_MSA_INSN 0x5800083f
355#define COPY_SW_MSA_INSN 0x58b00056
356#define COPY_SD_MSA_INSN 0x58b80056
357#define INSERT_W_MSA_INSN 0x59300816
358#define INSERT_D_MSA_INSN 0x59380816
359#else
360#define CFC_MSA_INSN 0x787e0059
361#define CTC_MSA_INSN 0x783e0819
362#define LDB_MSA_INSN 0x78000820
363#define LDH_MSA_INSN 0x78000821
364#define LDW_MSA_INSN 0x78000822
365#define LDD_MSA_INSN 0x78000823
366#define STB_MSA_INSN 0x78000824
367#define STH_MSA_INSN 0x78000825
368#define STW_MSA_INSN 0x78000826
369#define STD_MSA_INSN 0x78000827
370#define COPY_SW_MSA_INSN 0x78b00059
371#define COPY_SD_MSA_INSN 0x78b80059
372#define INSERT_W_MSA_INSN 0x79300819
373#define INSERT_D_MSA_INSN 0x79380819
374#endif
375
376 /* 366 /*
377 * Temporary until all toolchains in use include MSA support. 367 * Temporary until all toolchains in use include MSA support.
378 */ 368 */
@@ -380,8 +370,8 @@
380 .set push 370 .set push
381 .set noat 371 .set noat
382 SET_HARDFLOAT 372 SET_HARDFLOAT
383 .insn 373 insn_if_mips 0x787e0059 | (\cs << 11)
384 .word CFC_MSA_INSN | (\cs << 11) 374 insn32_if_mm 0x587e0056 | (\cs << 11)
385 move \rd, $1 375 move \rd, $1
386 .set pop 376 .set pop
387 .endm 377 .endm
@@ -391,7 +381,8 @@
391 .set noat 381 .set noat
392 SET_HARDFLOAT 382 SET_HARDFLOAT
393 move $1, \rs 383 move $1, \rs
394 .word CTC_MSA_INSN | (\cd << 6) 384 insn_if_mips 0x783e0819 | (\cd << 6)
385 insn32_if_mm 0x583e0816 | (\cd << 6)
395 .set pop 386 .set pop
396 .endm 387 .endm
397 388
@@ -400,7 +391,8 @@
400 .set noat 391 .set noat
401 SET_HARDFLOAT 392 SET_HARDFLOAT
402 PTR_ADDU $1, \base, \off 393 PTR_ADDU $1, \base, \off
403 .word LDB_MSA_INSN | (\wd << 6) 394 insn_if_mips 0x78000820 | (\wd << 6)
395 insn32_if_mm 0x58000807 | (\wd << 6)
404 .set pop 396 .set pop
405 .endm 397 .endm
406 398
@@ -409,7 +401,8 @@
409 .set noat 401 .set noat
410 SET_HARDFLOAT 402 SET_HARDFLOAT
411 PTR_ADDU $1, \base, \off 403 PTR_ADDU $1, \base, \off
412 .word LDH_MSA_INSN | (\wd << 6) 404 insn_if_mips 0x78000821 | (\wd << 6)
405 insn32_if_mm 0x58000817 | (\wd << 6)
413 .set pop 406 .set pop
414 .endm 407 .endm
415 408
@@ -418,7 +411,8 @@
418 .set noat 411 .set noat
419 SET_HARDFLOAT 412 SET_HARDFLOAT
420 PTR_ADDU $1, \base, \off 413 PTR_ADDU $1, \base, \off
421 .word LDW_MSA_INSN | (\wd << 6) 414 insn_if_mips 0x78000822 | (\wd << 6)
415 insn32_if_mm 0x58000827 | (\wd << 6)
422 .set pop 416 .set pop
423 .endm 417 .endm
424 418
@@ -427,7 +421,8 @@
427 .set noat 421 .set noat
428 SET_HARDFLOAT 422 SET_HARDFLOAT
429 PTR_ADDU $1, \base, \off 423 PTR_ADDU $1, \base, \off
430 .word LDD_MSA_INSN | (\wd << 6) 424 insn_if_mips 0x78000823 | (\wd << 6)
425 insn32_if_mm 0x58000837 | (\wd << 6)
431 .set pop 426 .set pop
432 .endm 427 .endm
433 428
@@ -436,7 +431,8 @@
436 .set noat 431 .set noat
437 SET_HARDFLOAT 432 SET_HARDFLOAT
438 PTR_ADDU $1, \base, \off 433 PTR_ADDU $1, \base, \off
439 .word STB_MSA_INSN | (\wd << 6) 434 insn_if_mips 0x78000824 | (\wd << 6)
435 insn32_if_mm 0x5800080f | (\wd << 6)
440 .set pop 436 .set pop
441 .endm 437 .endm
442 438
@@ -445,7 +441,8 @@
445 .set noat 441 .set noat
446 SET_HARDFLOAT 442 SET_HARDFLOAT
447 PTR_ADDU $1, \base, \off 443 PTR_ADDU $1, \base, \off
448 .word STH_MSA_INSN | (\wd << 6) 444 insn_if_mips 0x78000825 | (\wd << 6)
445 insn32_if_mm 0x5800081f | (\wd << 6)
449 .set pop 446 .set pop
450 .endm 447 .endm
451 448
@@ -454,7 +451,8 @@
454 .set noat 451 .set noat
455 SET_HARDFLOAT 452 SET_HARDFLOAT
456 PTR_ADDU $1, \base, \off 453 PTR_ADDU $1, \base, \off
457 .word STW_MSA_INSN | (\wd << 6) 454 insn_if_mips 0x78000826 | (\wd << 6)
455 insn32_if_mm 0x5800082f | (\wd << 6)
458 .set pop 456 .set pop
459 .endm 457 .endm
460 458
@@ -463,7 +461,8 @@
463 .set noat 461 .set noat
464 SET_HARDFLOAT 462 SET_HARDFLOAT
465 PTR_ADDU $1, \base, \off 463 PTR_ADDU $1, \base, \off
466 .word STD_MSA_INSN | (\wd << 6) 464 insn_if_mips 0x78000827 | (\wd << 6)
465 insn32_if_mm 0x5800083f | (\wd << 6)
467 .set pop 466 .set pop
468 .endm 467 .endm
469 468
@@ -471,8 +470,8 @@
471 .set push 470 .set push
472 .set noat 471 .set noat
473 SET_HARDFLOAT 472 SET_HARDFLOAT
474 .insn 473 insn_if_mips 0x78b00059 | (\n << 16) | (\ws << 11)
475 .word COPY_SW_MSA_INSN | (\n << 16) | (\ws << 11) 474 insn32_if_mm 0x58b00056 | (\n << 16) | (\ws << 11)
476 .set pop 475 .set pop
477 .endm 476 .endm
478 477
@@ -480,8 +479,8 @@
480 .set push 479 .set push
481 .set noat 480 .set noat
482 SET_HARDFLOAT 481 SET_HARDFLOAT
483 .insn 482 insn_if_mips 0x78b80059 | (\n << 16) | (\ws << 11)
484 .word COPY_SD_MSA_INSN | (\n << 16) | (\ws << 11) 483 insn32_if_mm 0x58b80056 | (\n << 16) | (\ws << 11)
485 .set pop 484 .set pop
486 .endm 485 .endm
487 486
@@ -489,7 +488,8 @@
489 .set push 488 .set push
490 .set noat 489 .set noat
491 SET_HARDFLOAT 490 SET_HARDFLOAT
492 .word INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6) 491 insn_if_mips 0x79300819 | (\n << 16) | (\wd << 6)
492 insn32_if_mm 0x59300816 | (\n << 16) | (\wd << 6)
493 .set pop 493 .set pop
494 .endm 494 .endm
495 495
@@ -497,7 +497,8 @@
497 .set push 497 .set push
498 .set noat 498 .set noat
499 SET_HARDFLOAT 499 SET_HARDFLOAT
500 .word INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6) 500 insn_if_mips 0x79380819 | (\n << 16) | (\wd << 6)
501 insn32_if_mm 0x59380816 | (\n << 16) | (\wd << 6)
501 .set pop 502 .set pop
502 .endm 503 .endm
503#endif 504#endif
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index dbb1eb6e284f..e0fecf206f2c 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -58,8 +58,8 @@
58 * address of a label as argument to inline assembler. Gas otoh has the 58 * address of a label as argument to inline assembler. Gas otoh has the
59 * annoying difference between la and dla which are only usable for 32-bit 59 * annoying difference between la and dla which are only usable for 32-bit
60 * rsp. 64-bit code, so can't be used without conditional compilation. 60 * rsp. 64-bit code, so can't be used without conditional compilation.
61 * The alterantive is switching the assembler to 64-bit code which happens 61 * The alternative is switching the assembler to 64-bit code which happens
62 * to work right even for 32-bit code ... 62 * to work right even for 32-bit code...
63 */ 63 */
64#define instruction_hazard() \ 64#define instruction_hazard() \
65do { \ 65do { \
@@ -133,8 +133,8 @@ do { \
133 * address of a label as argument to inline assembler. Gas otoh has the 133 * address of a label as argument to inline assembler. Gas otoh has the
134 * annoying difference between la and dla which are only usable for 32-bit 134 * annoying difference between la and dla which are only usable for 32-bit
135 * rsp. 64-bit code, so can't be used without conditional compilation. 135 * rsp. 64-bit code, so can't be used without conditional compilation.
136 * The alterantive is switching the assembler to 64-bit code which happens 136 * The alternative is switching the assembler to 64-bit code which happens
137 * to work right even for 32-bit code ... 137 * to work right even for 32-bit code...
138 */ 138 */
139#define __instruction_hazard() \ 139#define __instruction_hazard() \
140do { \ 140do { \
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
index ca8077afac4a..456ddba152c4 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -100,7 +100,7 @@ typedef volatile struct au1xxx_ddma_desc {
100 u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */ 100 u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */
101 /* 101 /*
102 * First 32 bytes are HW specific!!! 102 * First 32 bytes are HW specific!!!
103 * Lets have some SW data following -- make sure it's 32 bytes. 103 * Let's have some SW data following -- make sure it's 32 bytes.
104 */ 104 */
105 u32 sw_status; 105 u32 sw_status;
106 u32 sw_context; 106 u32 sw_context;
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
index ce02894271c6..d607d643b973 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
@@ -140,7 +140,7 @@ static inline int au1300_gpio_getinitlvl(unsigned int gpio)
140* Cases 1 and 3 are intended for boards which want to provide their own 140* Cases 1 and 3 are intended for boards which want to provide their own
141* GPIO namespace and -operations (i.e. for example you have 8 GPIOs 141* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
142* which are in part provided by spare Au1300 GPIO pins and in part by 142* which are in part provided by spare Au1300 GPIO pins and in part by
143* an external FPGA but you still want them to be accssible in linux 143* an external FPGA but you still want them to be accessible in linux
144* as gpio0-7. The board can of course use the alchemy_gpioX_* functions 144* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
145* as required). 145* as required).
146*/ 146*/
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
index 466fc85899f4..c4e856f27040 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
@@ -22,7 +22,7 @@ struct bcm63xx_enet_platform_data {
22 int has_phy_interrupt; 22 int has_phy_interrupt;
23 int phy_interrupt; 23 int phy_interrupt;
24 24
25 /* if has_phy, use autonegociated pause parameters or force 25 /* if has_phy, use autonegotiated pause parameters or force
26 * them */ 26 * them */
27 int pause_auto; 27 int pause_auto;
28 int pause_rx; 28 int pause_rx;
diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h
index 1daa64412569..04d862020ac9 100644
--- a/arch/mips/include/asm/mach-ip27/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h
@@ -64,7 +64,7 @@ static inline void plat_post_dma_flush(struct device *dev)
64 64
65static inline int plat_device_is_coherent(struct device *dev) 65static inline int plat_device_is_coherent(struct device *dev)
66{ 66{
67 return 1; /* IP27 non-cohernet mode is unsupported */ 67 return 1; /* IP27 non-coherent mode is unsupported */
68} 68}
69 69
70#endif /* __ASM_MACH_IP27_DMA_COHERENCE_H */ 70#endif /* __ASM_MACH_IP27_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h
index 0a0b0e2ced60..7bdf212587a0 100644
--- a/arch/mips/include/asm/mach-ip32/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h
@@ -86,7 +86,7 @@ static inline void plat_post_dma_flush(struct device *dev)
86 86
87static inline int plat_device_is_coherent(struct device *dev) 87static inline int plat_device_is_coherent(struct device *dev)
88{ 88{
89 return 0; /* IP32 is non-cohernet */ 89 return 0; /* IP32 is non-coherent */
90} 90}
91 91
92#endif /* __ASM_MACH_IP32_DMA_COHERENCE_H */ 92#endif /* __ASM_MACH_IP32_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
index 7023883ca50f..8e9b022c3594 100644
--- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
@@ -22,7 +22,7 @@
22 22
23/* 23/*
24 * during early_printk no ioremap possible at this early stage 24 * during early_printk no ioremap possible at this early stage
25 * lets use KSEG1 instead 25 * let's use KSEG1 instead
26 */ 26 */
27#define LTQ_ASC0_BASE_ADDR 0x1E100C00 27#define LTQ_ASC0_BASE_ADDR 0x1E100C00
28#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR) 28#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index f87310755319..17b41bb5991f 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -75,7 +75,7 @@ extern __iomem void *ltq_cgu_membase;
75 75
76/* 76/*
77 * during early_printk no ioremap is possible 77 * during early_printk no ioremap is possible
78 * lets use KSEG1 instead 78 * let's use KSEG1 instead
79 */ 79 */
80#define LTQ_ASC1_BASE_ADDR 0x1E100C00 80#define LTQ_ASC1_BASE_ADDR 0x1E100C00
81#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR) 81#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
diff --git a/arch/mips/include/asm/mach-loongson64/loongson_hwmon.h b/arch/mips/include/asm/mach-loongson64/loongson_hwmon.h
index 4431fc54a36c..74230d0ca98b 100644
--- a/arch/mips/include/asm/mach-loongson64/loongson_hwmon.h
+++ b/arch/mips/include/asm/mach-loongson64/loongson_hwmon.h
@@ -24,7 +24,7 @@ struct temp_range {
24 u8 level; 24 u8 level;
25}; 25};
26 26
27#define CONSTANT_SPEED_POLICY 0 /* at constent speed */ 27#define CONSTANT_SPEED_POLICY 0 /* at constant speed */
28#define STEP_SPEED_POLICY 1 /* use up/down arrays to describe policy */ 28#define STEP_SPEED_POLICY 1 /* use up/down arrays to describe policy */
29#define KERNEL_HELPER_POLICY 2 /* kernel as a helper to fan control */ 29#define KERNEL_HELPER_POLICY 2 /* kernel as a helper to fan control */
30 30
diff --git a/arch/mips/include/asm/mach-malta/kernel-entry-init.h b/arch/mips/include/asm/mach-malta/kernel-entry-init.h
index 0cf8622db27f..ab03eb3fadac 100644
--- a/arch/mips/include/asm/mach-malta/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-malta/kernel-entry-init.h
@@ -56,7 +56,7 @@
56 (0 << MIPS_SEGCFG_PA_SHIFT) | \ 56 (0 << MIPS_SEGCFG_PA_SHIFT) | \
57 (1 << MIPS_SEGCFG_EU_SHIFT)) << 16) 57 (1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
58 or t0, t2 58 or t0, t2
59 mtc0 t0, $5, 2 59 mtc0 t0, CP0_SEGCTL0
60 60
61 /* SegCtl1 */ 61 /* SegCtl1 */
62 li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \ 62 li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \
@@ -67,7 +67,7 @@
67 (0 << MIPS_SEGCFG_PA_SHIFT) | \ 67 (0 << MIPS_SEGCFG_PA_SHIFT) | \
68 (1 << MIPS_SEGCFG_EU_SHIFT)) << 16) 68 (1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
69 ins t0, t1, 16, 3 69 ins t0, t1, 16, 3
70 mtc0 t0, $5, 3 70 mtc0 t0, CP0_SEGCTL1
71 71
72 /* SegCtl2 */ 72 /* SegCtl2 */
73 li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \ 73 li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \
@@ -77,7 +77,7 @@
77 (4 << MIPS_SEGCFG_PA_SHIFT) | \ 77 (4 << MIPS_SEGCFG_PA_SHIFT) | \
78 (1 << MIPS_SEGCFG_EU_SHIFT)) << 16) 78 (1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
79 or t0, t2 79 or t0, t2
80 mtc0 t0, $5, 4 80 mtc0 t0, CP0_SEGCTL2
81 81
82 jal mips_ihb 82 jal mips_ihb
83 mfc0 t0, $16, 5 83 mfc0 t0, $16, 5
diff --git a/arch/mips/include/asm/mips_mt.h b/arch/mips/include/asm/mips_mt.h
index f6ba004a7711..aa4cca060e0a 100644
--- a/arch/mips/include/asm/mips_mt.h
+++ b/arch/mips/include/asm/mips_mt.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Definitions and decalrations for MIPS MT support that are common between 2 * Definitions and declarations for MIPS MT support that are common between
3 * the VSMP, and AP/SP kernel models. 3 * the VSMP, and AP/SP kernel models.
4 */ 4 */
5#ifndef __ASM_MIPS_MT_H 5#ifndef __ASM_MIPS_MT_H
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 25d01577d0b5..e1ca65c62f6a 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -48,6 +48,9 @@
48#define CP0_CONF $3 48#define CP0_CONF $3
49#define CP0_CONTEXT $4 49#define CP0_CONTEXT $4
50#define CP0_PAGEMASK $5 50#define CP0_PAGEMASK $5
51#define CP0_SEGCTL0 $5, 2
52#define CP0_SEGCTL1 $5, 3
53#define CP0_SEGCTL2 $5, 4
51#define CP0_WIRED $6 54#define CP0_WIRED $6
52#define CP0_INFO $7 55#define CP0_INFO $7
53#define CP0_HWRENA $7, 0 56#define CP0_HWRENA $7, 0
@@ -726,6 +729,8 @@
726#define MIPS_PWFIELD_PTEI_SHIFT 0 729#define MIPS_PWFIELD_PTEI_SHIFT 0
727#define MIPS_PWFIELD_PTEI_MASK 0x0000003f 730#define MIPS_PWFIELD_PTEI_MASK 0x0000003f
728 731
732#define MIPS_PWSIZE_PS_SHIFT 30
733#define MIPS_PWSIZE_PS_MASK 0x40000000
729#define MIPS_PWSIZE_GDW_SHIFT 24 734#define MIPS_PWSIZE_GDW_SHIFT 24
730#define MIPS_PWSIZE_GDW_MASK 0x3f000000 735#define MIPS_PWSIZE_GDW_MASK 0x3f000000
731#define MIPS_PWSIZE_UDW_SHIFT 18 736#define MIPS_PWSIZE_UDW_SHIFT 18
@@ -739,6 +744,12 @@
739 744
740#define MIPS_PWCTL_PWEN_SHIFT 31 745#define MIPS_PWCTL_PWEN_SHIFT 31
741#define MIPS_PWCTL_PWEN_MASK 0x80000000 746#define MIPS_PWCTL_PWEN_MASK 0x80000000
747#define MIPS_PWCTL_XK_SHIFT 28
748#define MIPS_PWCTL_XK_MASK 0x10000000
749#define MIPS_PWCTL_XS_SHIFT 27
750#define MIPS_PWCTL_XS_MASK 0x08000000
751#define MIPS_PWCTL_XU_SHIFT 26
752#define MIPS_PWCTL_XU_MASK 0x04000000
742#define MIPS_PWCTL_DPH_SHIFT 7 753#define MIPS_PWCTL_DPH_SHIFT 7
743#define MIPS_PWCTL_DPH_MASK 0x00000080 754#define MIPS_PWCTL_DPH_MASK 0x00000080
744#define MIPS_PWCTL_HUGEPG_SHIFT 6 755#define MIPS_PWCTL_HUGEPG_SHIFT 6
@@ -1046,6 +1057,33 @@ static inline int mm_insn_16bit(u16 insn)
1046} 1057}
1047 1058
1048/* 1059/*
1060 * Helper macros for generating raw instruction encodings in inline asm.
1061 */
1062#ifdef CONFIG_CPU_MICROMIPS
1063#define _ASM_INSN16_IF_MM(_enc) \
1064 ".insn\n\t" \
1065 ".hword (" #_enc ")\n\t"
1066#define _ASM_INSN32_IF_MM(_enc) \
1067 ".insn\n\t" \
1068 ".hword ((" #_enc ") >> 16)\n\t" \
1069 ".hword ((" #_enc ") & 0xffff)\n\t"
1070#else
1071#define _ASM_INSN_IF_MIPS(_enc) \
1072 ".insn\n\t" \
1073 ".word (" #_enc ")\n\t"
1074#endif
1075
1076#ifndef _ASM_INSN16_IF_MM
1077#define _ASM_INSN16_IF_MM(_enc)
1078#endif
1079#ifndef _ASM_INSN32_IF_MM
1080#define _ASM_INSN32_IF_MM(_enc)
1081#endif
1082#ifndef _ASM_INSN_IF_MIPS
1083#define _ASM_INSN_IF_MIPS(_enc)
1084#endif
1085
1086/*
1049 * TLB Invalidate Flush 1087 * TLB Invalidate Flush
1050 */ 1088 */
1051static inline void tlbinvf(void) 1089static inline void tlbinvf(void)
@@ -1053,7 +1091,9 @@ static inline void tlbinvf(void)
1053 __asm__ __volatile__( 1091 __asm__ __volatile__(
1054 ".set push\n\t" 1092 ".set push\n\t"
1055 ".set noreorder\n\t" 1093 ".set noreorder\n\t"
1056 ".word 0x42000004\n\t" /* tlbinvf */ 1094 "# tlbinvf\n\t"
1095 _ASM_INSN_IF_MIPS(0x42000004)
1096 _ASM_INSN32_IF_MM(0x0000537c)
1057 ".set pop"); 1097 ".set pop");
1058} 1098}
1059 1099
@@ -1274,9 +1314,9 @@ do { \
1274 " .set push \n" \ 1314 " .set push \n" \
1275 " .set noat \n" \ 1315 " .set noat \n" \
1276 " .set mips32r2 \n" \ 1316 " .set mips32r2 \n" \
1277 " .insn \n" \
1278 " # mfhc0 $1, %1 \n" \ 1317 " # mfhc0 $1, %1 \n" \
1279 " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \ 1318 _ASM_INSN_IF_MIPS(0x40410000 | ((%1 & 0x1f) << 11)) \
1319 _ASM_INSN32_IF_MM(0x002000f4 | ((%1 & 0x1f) << 16)) \
1280 " move %0, $1 \n" \ 1320 " move %0, $1 \n" \
1281 " .set pop \n" \ 1321 " .set pop \n" \
1282 : "=r" (__res) \ 1322 : "=r" (__res) \
@@ -1292,8 +1332,8 @@ do { \
1292 " .set mips32r2 \n" \ 1332 " .set mips32r2 \n" \
1293 " move $1, %0 \n" \ 1333 " move $1, %0 \n" \
1294 " # mthc0 $1, %1 \n" \ 1334 " # mthc0 $1, %1 \n" \
1295 " .insn \n" \ 1335 _ASM_INSN_IF_MIPS(0x40c10000 | ((%1 & 0x1f) << 11)) \
1296 " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \ 1336 _ASM_INSN32_IF_MM(0x002002f4 | ((%1 & 0x1f) << 16)) \
1297 " .set pop \n" \ 1337 " .set pop \n" \
1298 : \ 1338 : \
1299 : "r" (value), "i" (register)); \ 1339 : "r" (value), "i" (register)); \
@@ -1743,7 +1783,8 @@ do { \
1743 ".set\tpush\n\t" \ 1783 ".set\tpush\n\t" \
1744 ".set\tnoat\n\t" \ 1784 ".set\tnoat\n\t" \
1745 "# mfgc0\t$1, $%1, %2\n\t" \ 1785 "# mfgc0\t$1, $%1, %2\n\t" \
1746 ".word\t(0x40610000 | %1 << 11 | %2)\n\t" \ 1786 _ASM_INSN_IF_MIPS(0x40610000 | %1 << 11 | %2) \
1787 _ASM_INSN32_IF_MM(0x002004fc | %1 << 16 | %2 << 11) \
1747 "move\t%0, $1\n\t" \ 1788 "move\t%0, $1\n\t" \
1748 ".set\tpop" \ 1789 ".set\tpop" \
1749 : "=r" (__res) \ 1790 : "=r" (__res) \
@@ -1757,7 +1798,8 @@ do { \
1757 ".set\tpush\n\t" \ 1798 ".set\tpush\n\t" \
1758 ".set\tnoat\n\t" \ 1799 ".set\tnoat\n\t" \
1759 "# dmfgc0\t$1, $%1, %2\n\t" \ 1800 "# dmfgc0\t$1, $%1, %2\n\t" \
1760 ".word\t(0x40610100 | %1 << 11 | %2)\n\t" \ 1801 _ASM_INSN_IF_MIPS(0x40610100 | %1 << 11 | %2) \
1802 _ASM_INSN32_IF_MM(0x582004fc | %1 << 16 | %2 << 11) \
1761 "move\t%0, $1\n\t" \ 1803 "move\t%0, $1\n\t" \
1762 ".set\tpop" \ 1804 ".set\tpop" \
1763 : "=r" (__res) \ 1805 : "=r" (__res) \
@@ -1770,9 +1812,10 @@ do { \
1770 __asm__ __volatile__( \ 1812 __asm__ __volatile__( \
1771 ".set\tpush\n\t" \ 1813 ".set\tpush\n\t" \
1772 ".set\tnoat\n\t" \ 1814 ".set\tnoat\n\t" \
1773 "move\t$1, %0\n\t" \ 1815 "move\t$1, %z0\n\t" \
1774 "# mtgc0\t$1, $%1, %2\n\t" \ 1816 "# mtgc0\t$1, $%1, %2\n\t" \
1775 ".word\t(0x40610200 | %1 << 11 | %2)\n\t" \ 1817 _ASM_INSN_IF_MIPS(0x40610200 | %1 << 11 | %2) \
1818 _ASM_INSN32_IF_MM(0x002006fc | %1 << 16 | %2 << 11) \
1776 ".set\tpop" \ 1819 ".set\tpop" \
1777 : : "Jr" ((unsigned int)(value)), \ 1820 : : "Jr" ((unsigned int)(value)), \
1778 "i" (register), "i" (sel)); \ 1821 "i" (register), "i" (sel)); \
@@ -1783,9 +1826,10 @@ do { \
1783 __asm__ __volatile__( \ 1826 __asm__ __volatile__( \
1784 ".set\tpush\n\t" \ 1827 ".set\tpush\n\t" \
1785 ".set\tnoat\n\t" \ 1828 ".set\tnoat\n\t" \
1786 "move\t$1, %0\n\t" \ 1829 "move\t$1, %z0\n\t" \
1787 "# dmtgc0\t$1, $%1, %2\n\t" \ 1830 "# dmtgc0\t$1, $%1, %2\n\t" \
1788 ".word\t(0x40610300 | %1 << 11 | %2)\n\t" \ 1831 _ASM_INSN_IF_MIPS(0x40610300 | %1 << 11 | %2) \
1832 _ASM_INSN32_IF_MM(0x582006fc | %1 << 16 | %2 << 11) \
1789 ".set\tpop" \ 1833 ".set\tpop" \
1790 : : "Jr" (value), \ 1834 : : "Jr" (value), \
1791 "i" (register), "i" (sel)); \ 1835 "i" (register), "i" (sel)); \
@@ -2246,7 +2290,6 @@ do { \
2246 2290
2247#else 2291#else
2248 2292
2249#ifdef CONFIG_CPU_MICROMIPS
2250#define rddsp(mask) \ 2293#define rddsp(mask) \
2251({ \ 2294({ \
2252 unsigned int __res; \ 2295 unsigned int __res; \
@@ -2255,8 +2298,8 @@ do { \
2255 " .set push \n" \ 2298 " .set push \n" \
2256 " .set noat \n" \ 2299 " .set noat \n" \
2257 " # rddsp $1, %x1 \n" \ 2300 " # rddsp $1, %x1 \n" \
2258 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ 2301 _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16)) \
2259 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ 2302 _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14)) \
2260 " move %0, $1 \n" \ 2303 " move %0, $1 \n" \
2261 " .set pop \n" \ 2304 " .set pop \n" \
2262 : "=r" (__res) \ 2305 : "=r" (__res) \
@@ -2271,22 +2314,22 @@ do { \
2271 " .set noat \n" \ 2314 " .set noat \n" \
2272 " move $1, %0 \n" \ 2315 " move $1, %0 \n" \
2273 " # wrdsp $1, %x1 \n" \ 2316 " # wrdsp $1, %x1 \n" \
2274 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ 2317 _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11)) \
2275 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ 2318 _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14)) \
2276 " .set pop \n" \ 2319 " .set pop \n" \
2277 : \ 2320 : \
2278 : "r" (val), "i" (mask)); \ 2321 : "r" (val), "i" (mask)); \
2279} while (0) 2322} while (0)
2280 2323
2281#define _umips_dsp_mfxxx(ins) \ 2324#define _dsp_mfxxx(ins) \
2282({ \ 2325({ \
2283 unsigned long __treg; \ 2326 unsigned long __treg; \
2284 \ 2327 \
2285 __asm__ __volatile__( \ 2328 __asm__ __volatile__( \
2286 " .set push \n" \ 2329 " .set push \n" \
2287 " .set noat \n" \ 2330 " .set noat \n" \
2288 " .hword 0x0001 \n" \ 2331 _ASM_INSN_IF_MIPS(0x00000810 | %X1) \
2289 " .hword %x1 \n" \ 2332 _ASM_INSN32_IF_MM(0x0001007c | %x1) \
2290 " move %0, $1 \n" \ 2333 " move %0, $1 \n" \
2291 " .set pop \n" \ 2334 " .set pop \n" \
2292 : "=r" (__treg) \ 2335 : "=r" (__treg) \
@@ -2294,101 +2337,28 @@ do { \
2294 __treg; \ 2337 __treg; \
2295}) 2338})
2296 2339
2297#define _umips_dsp_mtxxx(val, ins) \ 2340#define _dsp_mtxxx(val, ins) \
2298do { \ 2341do { \
2299 __asm__ __volatile__( \ 2342 __asm__ __volatile__( \
2300 " .set push \n" \ 2343 " .set push \n" \
2301 " .set noat \n" \ 2344 " .set noat \n" \
2302 " move $1, %0 \n" \ 2345 " move $1, %0 \n" \
2303 " .hword 0x0001 \n" \ 2346 _ASM_INSN_IF_MIPS(0x00200011 | %X1) \
2304 " .hword %x1 \n" \ 2347 _ASM_INSN32_IF_MM(0x0001207c | %x1) \
2305 " .set pop \n" \ 2348 " .set pop \n" \
2306 : \ 2349 : \
2307 : "r" (val), "i" (ins)); \ 2350 : "r" (val), "i" (ins)); \
2308} while (0) 2351} while (0)
2309 2352
2310#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c) 2353#ifdef CONFIG_CPU_MICROMIPS
2311#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
2312
2313#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
2314#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
2315
2316#define mflo0() _umips_dsp_mflo(0)
2317#define mflo1() _umips_dsp_mflo(1)
2318#define mflo2() _umips_dsp_mflo(2)
2319#define mflo3() _umips_dsp_mflo(3)
2320
2321#define mfhi0() _umips_dsp_mfhi(0)
2322#define mfhi1() _umips_dsp_mfhi(1)
2323#define mfhi2() _umips_dsp_mfhi(2)
2324#define mfhi3() _umips_dsp_mfhi(3)
2325 2354
2326#define mtlo0(x) _umips_dsp_mtlo(x, 0) 2355#define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2327#define mtlo1(x) _umips_dsp_mtlo(x, 1) 2356#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2328#define mtlo2(x) _umips_dsp_mtlo(x, 2)
2329#define mtlo3(x) _umips_dsp_mtlo(x, 3)
2330 2357
2331#define mthi0(x) _umips_dsp_mthi(x, 0) 2358#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2332#define mthi1(x) _umips_dsp_mthi(x, 1) 2359#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2333#define mthi2(x) _umips_dsp_mthi(x, 2)
2334#define mthi3(x) _umips_dsp_mthi(x, 3)
2335 2360
2336#else /* !CONFIG_CPU_MICROMIPS */ 2361#else /* !CONFIG_CPU_MICROMIPS */
2337#define rddsp(mask) \
2338({ \
2339 unsigned int __res; \
2340 \
2341 __asm__ __volatile__( \
2342 " .set push \n" \
2343 " .set noat \n" \
2344 " # rddsp $1, %x1 \n" \
2345 " .word 0x7c000cb8 | (%x1 << 16) \n" \
2346 " move %0, $1 \n" \
2347 " .set pop \n" \
2348 : "=r" (__res) \
2349 : "i" (mask)); \
2350 __res; \
2351})
2352
2353#define wrdsp(val, mask) \
2354do { \
2355 __asm__ __volatile__( \
2356 " .set push \n" \
2357 " .set noat \n" \
2358 " move $1, %0 \n" \
2359 " # wrdsp $1, %x1 \n" \
2360 " .word 0x7c2004f8 | (%x1 << 11) \n" \
2361 " .set pop \n" \
2362 : \
2363 : "r" (val), "i" (mask)); \
2364} while (0)
2365
2366#define _dsp_mfxxx(ins) \
2367({ \
2368 unsigned long __treg; \
2369 \
2370 __asm__ __volatile__( \
2371 " .set push \n" \
2372 " .set noat \n" \
2373 " .word (0x00000810 | %1) \n" \
2374 " move %0, $1 \n" \
2375 " .set pop \n" \
2376 : "=r" (__treg) \
2377 : "i" (ins)); \
2378 __treg; \
2379})
2380
2381#define _dsp_mtxxx(val, ins) \
2382do { \
2383 __asm__ __volatile__( \
2384 " .set push \n" \
2385 " .set noat \n" \
2386 " move $1, %0 \n" \
2387 " .word (0x00200011 | %1) \n" \
2388 " .set pop \n" \
2389 : \
2390 : "r" (val), "i" (ins)); \
2391} while (0)
2392 2362
2393#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) 2363#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2394#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) 2364#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
@@ -2396,6 +2366,8 @@ do { \
2396#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) 2366#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2397#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) 2367#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2398 2368
2369#endif /* CONFIG_CPU_MICROMIPS */
2370
2399#define mflo0() _dsp_mflo(0) 2371#define mflo0() _dsp_mflo(0)
2400#define mflo1() _dsp_mflo(1) 2372#define mflo1() _dsp_mflo(1)
2401#define mflo2() _dsp_mflo(2) 2373#define mflo2() _dsp_mflo(2)
@@ -2416,7 +2388,6 @@ do { \
2416#define mthi2(x) _dsp_mthi(x, 2) 2388#define mthi2(x) _dsp_mthi(x, 2)
2417#define mthi3(x) _dsp_mthi(x, 3) 2389#define mthi3(x) _dsp_mthi(x, 3)
2418 2390
2419#endif /* CONFIG_CPU_MICROMIPS */
2420#endif 2391#endif
2421 2392
2422/* 2393/*
@@ -2556,28 +2527,32 @@ static inline void guest_tlb_probe(void)
2556{ 2527{
2557 __asm__ __volatile__( 2528 __asm__ __volatile__(
2558 "# tlbgp\n\t" 2529 "# tlbgp\n\t"
2559 ".word 0x42000010"); 2530 _ASM_INSN_IF_MIPS(0x42000010)
2531 _ASM_INSN32_IF_MM(0x0000017c));
2560} 2532}
2561 2533
2562static inline void guest_tlb_read(void) 2534static inline void guest_tlb_read(void)
2563{ 2535{
2564 __asm__ __volatile__( 2536 __asm__ __volatile__(
2565 "# tlbgr\n\t" 2537 "# tlbgr\n\t"
2566 ".word 0x42000009"); 2538 _ASM_INSN_IF_MIPS(0x42000009)
2539 _ASM_INSN32_IF_MM(0x0000117c));
2567} 2540}
2568 2541
2569static inline void guest_tlb_write_indexed(void) 2542static inline void guest_tlb_write_indexed(void)
2570{ 2543{
2571 __asm__ __volatile__( 2544 __asm__ __volatile__(
2572 "# tlbgwi\n\t" 2545 "# tlbgwi\n\t"
2573 ".word 0x4200000a"); 2546 _ASM_INSN_IF_MIPS(0x4200000a)
2547 _ASM_INSN32_IF_MM(0x0000217c));
2574} 2548}
2575 2549
2576static inline void guest_tlb_write_random(void) 2550static inline void guest_tlb_write_random(void)
2577{ 2551{
2578 __asm__ __volatile__( 2552 __asm__ __volatile__(
2579 "# tlbgwr\n\t" 2553 "# tlbgwr\n\t"
2580 ".word 0x4200000e"); 2554 _ASM_INSN_IF_MIPS(0x4200000e)
2555 _ASM_INSN32_IF_MM(0x0000317c));
2581} 2556}
2582 2557
2583/* 2558/*
@@ -2587,7 +2562,8 @@ static inline void guest_tlbinvf(void)
2587{ 2562{
2588 __asm__ __volatile__( 2563 __asm__ __volatile__(
2589 "# tlbginvf\n\t" 2564 "# tlbginvf\n\t"
2590 ".word 0x4200000c"); 2565 _ASM_INSN_IF_MIPS(0x4200000c)
2566 _ASM_INSN32_IF_MM(0x0000517c));
2591} 2567}
2592 2568
2593#endif /* !TOOLCHAIN_SUPPORTS_VIRT */ 2569#endif /* !TOOLCHAIN_SUPPORTS_VIRT */
diff --git a/arch/mips/include/asm/msa.h b/arch/mips/include/asm/msa.h
index 6e4effa6f626..ddf496cb2a2a 100644
--- a/arch/mips/include/asm/msa.h
+++ b/arch/mips/include/asm/msa.h
@@ -192,13 +192,6 @@ static inline void write_msa_##name(unsigned int val) \
192 * allow compilation with toolchains that do not support MSA. Once all 192 * allow compilation with toolchains that do not support MSA. Once all
193 * toolchains in use support MSA these can be removed. 193 * toolchains in use support MSA these can be removed.
194 */ 194 */
195#ifdef CONFIG_CPU_MICROMIPS
196#define CFC_MSA_INSN 0x587e0056
197#define CTC_MSA_INSN 0x583e0816
198#else
199#define CFC_MSA_INSN 0x787e0059
200#define CTC_MSA_INSN 0x783e0819
201#endif
202 195
203#define __BUILD_MSA_CTL_REG(name, cs) \ 196#define __BUILD_MSA_CTL_REG(name, cs) \
204static inline unsigned int read_msa_##name(void) \ 197static inline unsigned int read_msa_##name(void) \
@@ -207,11 +200,12 @@ static inline unsigned int read_msa_##name(void) \
207 __asm__ __volatile__( \ 200 __asm__ __volatile__( \
208 " .set push\n" \ 201 " .set push\n" \
209 " .set noat\n" \ 202 " .set noat\n" \
210 " .insn\n" \ 203 " # cfcmsa $1, $%1\n" \
211 " .word %1 | (" #cs " << 11)\n" \ 204 _ASM_INSN_IF_MIPS(0x787e0059 | %1 << 11) \
205 _ASM_INSN32_IF_MM(0x587e0056 | %1 << 11) \
212 " move %0, $1\n" \ 206 " move %0, $1\n" \
213 " .set pop\n" \ 207 " .set pop\n" \
214 : "=r"(reg) : "i"(CFC_MSA_INSN)); \ 208 : "=r"(reg) : "i"(cs)); \
215 return reg; \ 209 return reg; \
216} \ 210} \
217 \ 211 \
@@ -221,10 +215,11 @@ static inline void write_msa_##name(unsigned int val) \
221 " .set push\n" \ 215 " .set push\n" \
222 " .set noat\n" \ 216 " .set noat\n" \
223 " move $1, %0\n" \ 217 " move $1, %0\n" \
224 " .insn\n" \ 218 " # ctcmsa $%1, $1\n" \
225 " .word %1 | (" #cs " << 6)\n" \ 219 _ASM_INSN_IF_MIPS(0x783e0819 | %1 << 6) \
220 _ASM_INSN32_IF_MM(0x583e0816 | %1 << 6) \
226 " .set pop\n" \ 221 " .set pop\n" \
227 : : "r"(val), "i"(CTC_MSA_INSN)); \ 222 : : "r"(val), "i"(cs)); \
228} 223}
229 224
230#endif /* !TOOLCHAIN_SUPPORTS_MSA */ 225#endif /* !TOOLCHAIN_SUPPORTS_MSA */
diff --git a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
index 8d05d9069823..a07a36f7d814 100644
--- a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
+++ b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
@@ -146,7 +146,7 @@ typedef struct {
146 * This structure contains the global state of all command queues. 146 * This structure contains the global state of all command queues.
147 * It is stored in a bootmem named block and shared by all 147 * It is stored in a bootmem named block and shared by all
148 * applications running on Octeon. Tickets are stored in a differnet 148 * applications running on Octeon. Tickets are stored in a differnet
149 * cahce line that queue information to reduce the contention on the 149 * cache line that queue information to reduce the contention on the
150 * ll/sc used to get a ticket. If this is not the case, the update 150 * ll/sc used to get a ticket. If this is not the case, the update
151 * of queue state causes the ll/sc to fail quite often. 151 * of queue state causes the ll/sc to fail quite often.
152 */ 152 */
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-board.h b/arch/mips/include/asm/octeon/cvmx-helper-board.h
index 893320375aef..cda93aee712c 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper-board.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-board.h
@@ -94,7 +94,7 @@ extern int cvmx_helper_board_get_mii_address(int ipd_port);
94 * @phy_addr: The address of the PHY to program 94 * @phy_addr: The address of the PHY to program
95 * @link_flags: 95 * @link_flags:
96 * Flags to control autonegotiation. Bit 0 is autonegotiation 96 * Flags to control autonegotiation. Bit 0 is autonegotiation
97 * enable/disable to maintain backware compatibility. 97 * enable/disable to maintain backward compatibility.
98 * @link_info: Link speed to program. If the speed is zero and autonegotiation 98 * @link_info: Link speed to program. If the speed is zero and autonegotiation
99 * is enabled, all possible negotiation speeds are advertised. 99 * is enabled, all possible negotiation speeds are advertised.
100 * 100 *
diff --git a/arch/mips/include/asm/octeon/cvmx-ipd.h b/arch/mips/include/asm/octeon/cvmx-ipd.h
index e13490ebbb27..cbdc14b77435 100644
--- a/arch/mips/include/asm/octeon/cvmx-ipd.h
+++ b/arch/mips/include/asm/octeon/cvmx-ipd.h
@@ -39,7 +39,7 @@
39 39
40enum cvmx_ipd_mode { 40enum cvmx_ipd_mode {
41 CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */ 41 CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */
42 CVMX_IPD_OPC_MODE_STF = 1LL, /* All bloccks into L2 */ 42 CVMX_IPD_OPC_MODE_STF = 1LL, /* All blocks into L2 */
43 CVMX_IPD_OPC_MODE_STF1_STT = 2LL, /* 1st block L2, rest DRAM */ 43 CVMX_IPD_OPC_MODE_STF1_STT = 2LL, /* 1st block L2, rest DRAM */
44 CVMX_IPD_OPC_MODE_STF2_STT = 3LL /* 1st, 2nd blocks L2, rest DRAM */ 44 CVMX_IPD_OPC_MODE_STF2_STT = 3LL /* 1st, 2nd blocks L2, rest DRAM */
45}; 45};
diff --git a/arch/mips/include/asm/octeon/cvmx-pow.h b/arch/mips/include/asm/octeon/cvmx-pow.h
index 51531563f8dc..410bb70e5aac 100644
--- a/arch/mips/include/asm/octeon/cvmx-pow.h
+++ b/arch/mips/include/asm/octeon/cvmx-pow.h
@@ -2051,7 +2051,7 @@ static inline void cvmx_pow_tag_sw_desched(uint32_t tag,
2051} 2051}
2052 2052
2053/** 2053/**
2054 * Descchedules the current work queue entry. 2054 * Deschedules the current work queue entry.
2055 * 2055 *
2056 * @no_sched: no schedule flag value to be set on the work queue 2056 * @no_sched: no schedule flag value to be set on the work queue
2057 * entry. If this is set the entry will not be 2057 * entry. If this is set the entry will not be
diff --git a/arch/mips/include/asm/sgi/hpc3.h b/arch/mips/include/asm/sgi/hpc3.h
index 4a9c99050c13..c0e3dc0293a7 100644
--- a/arch/mips/include/asm/sgi/hpc3.h
+++ b/arch/mips/include/asm/sgi/hpc3.h
@@ -39,7 +39,7 @@ struct hpc3_pbus_dmacregs {
39 volatile u32 pbdma_dptr; /* pbus dma channel desc ptr */ 39 volatile u32 pbdma_dptr; /* pbus dma channel desc ptr */
40 u32 _unused0[0x1000/4 - 2]; /* padding */ 40 u32 _unused0[0x1000/4 - 2]; /* padding */
41 volatile u32 pbdma_ctrl; /* pbus dma channel control register has 41 volatile u32 pbdma_ctrl; /* pbus dma channel control register has
42 * copletely different meaning for read 42 * completely different meaning for read
43 * compared with write */ 43 * compared with write */
44 /* read */ 44 /* read */
45#define HPC3_PDMACTRL_INT 0x00000001 /* interrupt (cleared after read) */ 45#define HPC3_PDMACTRL_INT 0x00000001 /* interrupt (cleared after read) */
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index ceca6cc41b2b..6dc3f1fdaccc 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -481,7 +481,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
481 /* 481 /*
482 * OK we are here either because we hit a NAL 482 * OK we are here either because we hit a NAL
483 * instruction or because we are emulating an 483 * instruction or because we are emulating an
484 * old bltzal{,l} one. Lets figure out what the 484 * old bltzal{,l} one. Let's figure out what the
485 * case really is. 485 * case really is.
486 */ 486 */
487 if (!insn.i_format.rs) { 487 if (!insn.i_format.rs) {
@@ -515,7 +515,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
515 /* 515 /*
516 * OK we are here either because we hit a BAL 516 * OK we are here either because we hit a BAL
517 * instruction or because we are emulating an 517 * instruction or because we are emulating an
518 * old bgezal{,l} one. Lets figure out what the 518 * old bgezal{,l} one. Let's figure out what the
519 * case really is. 519 * case really is.
520 */ 520 */
521 if (!insn.i_format.rs) { 521 if (!insn.i_format.rs) {
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 51b98dc371b3..59476a607add 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -441,6 +441,21 @@ LEAF(mips_cps_boot_vpes)
441 mfc0 t0, CP0_CONFIG 441 mfc0 t0, CP0_CONFIG
442 mttc0 t0, CP0_CONFIG 442 mttc0 t0, CP0_CONFIG
443 443
444 /*
445 * Copy the EVA config from this VPE if the CPU supports it.
446 * CONFIG3 must exist to be running MT startup - just read it.
447 */
448 mfc0 t0, CP0_CONFIG, 3
449 and t0, t0, MIPS_CONF3_SC
450 beqz t0, 3f
451 nop
452 mfc0 t0, CP0_SEGCTL0
453 mttc0 t0, CP0_SEGCTL0
454 mfc0 t0, CP0_SEGCTL1
455 mttc0 t0, CP0_SEGCTL1
456 mfc0 t0, CP0_SEGCTL2
457 mttc0 t0, CP0_SEGCTL2
4583:
444 /* Ensure no software interrupts are pending */ 459 /* Ensure no software interrupts are pending */
445 mttc0 zero, CP0_CAUSE 460 mttc0 zero, CP0_CAUSE
446 mttc0 zero, CP0_STATUS 461 mttc0 zero, CP0_STATUS
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 5ac5c3e23460..a88d44247cc8 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -833,10 +833,8 @@ static inline unsigned int decode_config5(struct cpuinfo_mips *c)
833 c->options |= MIPS_CPU_MAAR; 833 c->options |= MIPS_CPU_MAAR;
834 if (config5 & MIPS_CONF5_LLB) 834 if (config5 & MIPS_CONF5_LLB)
835 c->options |= MIPS_CPU_RW_LLB; 835 c->options |= MIPS_CPU_RW_LLB;
836#ifdef CONFIG_XPA
837 if (config5 & MIPS_CONF5_MVH) 836 if (config5 & MIPS_CONF5_MVH)
838 c->options |= MIPS_CPU_XPA; 837 c->options |= MIPS_CPU_MVH;
839#endif
840 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP)) 838 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
841 c->options |= MIPS_CPU_VP; 839 c->options |= MIPS_CPU_VP;
842 840
diff --git a/arch/mips/kernel/elf.c b/arch/mips/kernel/elf.c
index c3c234dc0c07..891f5ee63983 100644
--- a/arch/mips/kernel/elf.c
+++ b/arch/mips/kernel/elf.c
@@ -88,7 +88,7 @@ int arch_elf_pt_proc(void *_ehdr, void *_phdr, struct file *elf,
88 elf32 = ehdr->e32.e_ident[EI_CLASS] == ELFCLASS32; 88 elf32 = ehdr->e32.e_ident[EI_CLASS] == ELFCLASS32;
89 flags = elf32 ? ehdr->e32.e_flags : ehdr->e64.e_flags; 89 flags = elf32 ? ehdr->e32.e_flags : ehdr->e64.e_flags;
90 90
91 /* Lets see if this is an O32 ELF */ 91 /* Let's see if this is an O32 ELF */
92 if (elf32) { 92 if (elf32) {
93 if (flags & EF_MIPS_FP64) { 93 if (flags & EF_MIPS_FP64) {
94 /* 94 /*
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 8eb5af805964..f25f7eab7307 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -54,6 +54,9 @@ void __init init_IRQ(void)
54 for (i = 0; i < NR_IRQS; i++) 54 for (i = 0; i < NR_IRQS; i++)
55 irq_set_noprobe(i); 55 irq_set_noprobe(i);
56 56
57 if (cpu_has_veic)
58 clear_c0_status(ST0_IM);
59
57 arch_init_irq(); 60 arch_init_irq();
58} 61}
59 62
diff --git a/arch/mips/kernel/mips-r2-to-r6-emul.c b/arch/mips/kernel/mips-r2-to-r6-emul.c
index 625ee770b1aa..7ff2a557f4aa 100644
--- a/arch/mips/kernel/mips-r2-to-r6-emul.c
+++ b/arch/mips/kernel/mips-r2-to-r6-emul.c
@@ -2202,7 +2202,7 @@ fpu_emul:
2202 } 2202 }
2203 2203
2204 /* 2204 /*
2205 * Lets not return to userland just yet. It's constly and 2205 * Let's not return to userland just yet. It's costly and
2206 * it's likely we have more R2 instructions to emulate 2206 * it's likely we have more R2 instructions to emulate
2207 */ 2207 */
2208 if (!err && (pass++ < MIPS_R2_EMUL_TOTAL_PASS)) { 2208 if (!err && (pass++ < MIPS_R2_EMUL_TOTAL_PASS)) {
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 411c971e3417..813ed7829c61 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -345,7 +345,7 @@ static int get_frame_info(struct mips_frame_info *info)
345 return 0; 345 return 0;
346 if (info->pc_offset < 0) /* leaf */ 346 if (info->pc_offset < 0) /* leaf */
347 return 1; 347 return 1;
348 /* prologue seems boggus... */ 348 /* prologue seems bogus... */
349err: 349err:
350 return -1; 350 return -1;
351} 351}
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index ab042291fbfd..ae4231452115 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -770,15 +770,7 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs)
770 sigset_t *oldset = sigmask_to_save(); 770 sigset_t *oldset = sigmask_to_save();
771 int ret; 771 int ret;
772 struct mips_abi *abi = current->thread.abi; 772 struct mips_abi *abi = current->thread.abi;
773#ifdef CONFIG_CPU_MICROMIPS
774 void *vdso;
775 unsigned long tmp = (unsigned long)current->mm->context.vdso;
776
777 set_isa16_mode(tmp);
778 vdso = (void *)tmp;
779#else
780 void *vdso = current->mm->context.vdso; 773 void *vdso = current->mm->context.vdso;
781#endif
782 774
783 if (regs->regs[0]) { 775 if (regs->regs[0]) {
784 switch(regs->regs[2]) { 776 switch(regs->regs[2]) {
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index 1061bd2e7e9c..4ed36f288d64 100644
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -359,8 +359,12 @@ static void cps_init_secondary(void)
359 BUG_ON(ident != mips_cm_vp_id(smp_processor_id())); 359 BUG_ON(ident != mips_cm_vp_id(smp_processor_id()));
360 } 360 }
361 361
362 change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 | 362 if (cpu_has_veic)
363 STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7); 363 clear_c0_status(ST0_IM);
364 else
365 change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
366 STATUSF_IP4 | STATUSF_IP5 |
367 STATUSF_IP6 | STATUSF_IP7);
364} 368}
365 369
366static void cps_smp_finish(void) 370static void cps_smp_finish(void)
diff --git a/arch/mips/lasat/picvue_proc.c b/arch/mips/lasat/picvue_proc.c
index b42095880667..27533c109f92 100644
--- a/arch/mips/lasat/picvue_proc.c
+++ b/arch/mips/lasat/picvue_proc.c
@@ -43,7 +43,7 @@ static int pvc_line_proc_show(struct seq_file *m, void *v)
43{ 43{
44 int lineno = *(int *)m->private; 44 int lineno = *(int *)m->private;
45 45
46 if (lineno < 0 || lineno > PVC_NLINES) { 46 if (lineno < 0 || lineno >= PVC_NLINES) {
47 printk(KERN_WARNING "proc_read_line: invalid lineno %d\n", lineno); 47 printk(KERN_WARNING "proc_read_line: invalid lineno %d\n", lineno);
48 return 0; 48 return 0;
49 } 49 }
@@ -67,7 +67,7 @@ static ssize_t pvc_line_proc_write(struct file *file, const char __user *buf,
67 char kbuf[PVC_LINELEN]; 67 char kbuf[PVC_LINELEN];
68 size_t len; 68 size_t len;
69 69
70 BUG_ON(lineno < 0 || lineno > PVC_NLINES); 70 BUG_ON(lineno < 0 || lineno >= PVC_NLINES);
71 71
72 len = min(count, sizeof(kbuf) - 1); 72 len = min(count, sizeof(kbuf) - 1);
73 if (copy_from_user(kbuf, buf, len)) 73 if (copy_from_user(kbuf, buf, len))
diff --git a/arch/mips/lib/ashldi3.c b/arch/mips/lib/ashldi3.c
index beb80f316095..927dc94a030f 100644
--- a/arch/mips/lib/ashldi3.c
+++ b/arch/mips/lib/ashldi3.c
@@ -2,7 +2,7 @@
2 2
3#include "libgcc.h" 3#include "libgcc.h"
4 4
5long long __ashldi3(long long u, word_type b) 5long long notrace __ashldi3(long long u, word_type b)
6{ 6{
7 DWunion uu, w; 7 DWunion uu, w;
8 word_type bm; 8 word_type bm;
diff --git a/arch/mips/lib/ashrdi3.c b/arch/mips/lib/ashrdi3.c
index c884a912b660..9fdf1a598428 100644
--- a/arch/mips/lib/ashrdi3.c
+++ b/arch/mips/lib/ashrdi3.c
@@ -2,7 +2,7 @@
2 2
3#include "libgcc.h" 3#include "libgcc.h"
4 4
5long long __ashrdi3(long long u, word_type b) 5long long notrace __ashrdi3(long long u, word_type b)
6{ 6{
7 DWunion uu, w; 7 DWunion uu, w;
8 word_type bm; 8 word_type bm;
diff --git a/arch/mips/lib/bswapdi.c b/arch/mips/lib/bswapdi.c
index 77e5f9c1f005..e3e77aa52c95 100644
--- a/arch/mips/lib/bswapdi.c
+++ b/arch/mips/lib/bswapdi.c
@@ -1,6 +1,6 @@
1#include <linux/module.h> 1#include <linux/module.h>
2 2
3unsigned long long __bswapdi2(unsigned long long u) 3unsigned long long notrace __bswapdi2(unsigned long long u)
4{ 4{
5 return (((u) & 0xff00000000000000ull) >> 56) | 5 return (((u) & 0xff00000000000000ull) >> 56) |
6 (((u) & 0x00ff000000000000ull) >> 40) | 6 (((u) & 0x00ff000000000000ull) >> 40) |
diff --git a/arch/mips/lib/bswapsi.c b/arch/mips/lib/bswapsi.c
index 2b302ff121d2..530a8afe6fda 100644
--- a/arch/mips/lib/bswapsi.c
+++ b/arch/mips/lib/bswapsi.c
@@ -1,6 +1,6 @@
1#include <linux/module.h> 1#include <linux/module.h>
2 2
3unsigned int __bswapsi2(unsigned int u) 3unsigned int notrace __bswapsi2(unsigned int u)
4{ 4{
5 return (((u) & 0xff000000) >> 24) | 5 return (((u) & 0xff000000) >> 24) |
6 (((u) & 0x00ff0000) >> 8) | 6 (((u) & 0x00ff0000) >> 8) |
diff --git a/arch/mips/lib/cmpdi2.c b/arch/mips/lib/cmpdi2.c
index 8c1306437ed1..06857da96993 100644
--- a/arch/mips/lib/cmpdi2.c
+++ b/arch/mips/lib/cmpdi2.c
@@ -2,7 +2,7 @@
2 2
3#include "libgcc.h" 3#include "libgcc.h"
4 4
5word_type __cmpdi2(long long a, long long b) 5word_type notrace __cmpdi2(long long a, long long b)
6{ 6{
7 const DWunion au = { 7 const DWunion au = {
8 .ll = a 8 .ll = a
diff --git a/arch/mips/lib/lshrdi3.c b/arch/mips/lib/lshrdi3.c
index dcf8d6810b7c..364547449c65 100644
--- a/arch/mips/lib/lshrdi3.c
+++ b/arch/mips/lib/lshrdi3.c
@@ -2,7 +2,7 @@
2 2
3#include "libgcc.h" 3#include "libgcc.h"
4 4
5long long __lshrdi3(long long u, word_type b) 5long long notrace __lshrdi3(long long u, word_type b)
6{ 6{
7 DWunion uu, w; 7 DWunion uu, w;
8 word_type bm; 8 word_type bm;
diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S
index 9245e1705e69..6c303a94a196 100644
--- a/arch/mips/lib/memcpy.S
+++ b/arch/mips/lib/memcpy.S
@@ -256,7 +256,7 @@
256 256
257 /* 257 /*
258 * Macro to build the __copy_user common code 258 * Macro to build the __copy_user common code
259 * Arguements: 259 * Arguments:
260 * mode : LEGACY_MODE or EVA_MODE 260 * mode : LEGACY_MODE or EVA_MODE
261 * from : Source operand. USEROP or KERNELOP 261 * from : Source operand. USEROP or KERNELOP
262 * to : Destination operand. USEROP or KERNELOP 262 * to : Destination operand. USEROP or KERNELOP
diff --git a/arch/mips/lib/ucmpdi2.c b/arch/mips/lib/ucmpdi2.c
index bb4cb2f828ea..bd599f58234c 100644
--- a/arch/mips/lib/ucmpdi2.c
+++ b/arch/mips/lib/ucmpdi2.c
@@ -2,7 +2,7 @@
2 2
3#include "libgcc.h" 3#include "libgcc.h"
4 4
5word_type __ucmpdi2(unsigned long long a, unsigned long long b) 5word_type notrace __ucmpdi2(unsigned long long a, unsigned long long b)
6{ 6{
7 const DWunion au = {.ll = a}; 7 const DWunion au = {.ll = a};
8 const DWunion bu = {.ll = b}; 8 const DWunion bu = {.ll = b};
diff --git a/arch/mips/loongson64/loongson-3/hpet.c b/arch/mips/loongson64/loongson-3/hpet.c
index a2631a52ca99..249039af66c4 100644
--- a/arch/mips/loongson64/loongson-3/hpet.c
+++ b/arch/mips/loongson64/loongson-3/hpet.c
@@ -212,7 +212,7 @@ static void hpet_setup(void)
212 /* set hpet base address */ 212 /* set hpet base address */
213 smbus_write(SMBUS_PCI_REGB4, HPET_ADDR); 213 smbus_write(SMBUS_PCI_REGB4, HPET_ADDR);
214 214
215 /* enable decodeing of access to HPET MMIO*/ 215 /* enable decoding of access to HPET MMIO*/
216 smbus_enable(SMBUS_PCI_REG40, (1 << 28)); 216 smbus_enable(SMBUS_PCI_REG40, (1 << 28));
217 217
218 /* HPET irq enable */ 218 /* HPET irq enable */
diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c
index d4ceacd4fa12..47074887e64c 100644
--- a/arch/mips/math-emu/dsemul.c
+++ b/arch/mips/math-emu/dsemul.c
@@ -8,7 +8,7 @@
8#include "ieee754.h" 8#include "ieee754.h"
9 9
10/* 10/*
11 * Emulate the arbritrary instruction ir at xcp->cp0_epc. Required when 11 * Emulate the arbitrary instruction ir at xcp->cp0_epc. Required when
12 * we have to emulate the instruction in a COP1 branch delay slot. Do 12 * we have to emulate the instruction in a COP1 branch delay slot. Do
13 * not change cp0_epc due to the instruction 13 * not change cp0_epc due to the instruction
14 * 14 *
@@ -88,7 +88,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
88 fr = (struct emuframe __user *) 88 fr = (struct emuframe __user *)
89 ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7); 89 ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7);
90 90
91 /* Verify that the stack pointer is not competely insane */ 91 /* Verify that the stack pointer is not completely insane */
92 if (unlikely(!access_ok(VERIFY_WRITE, fr, sizeof(struct emuframe)))) 92 if (unlikely(!access_ok(VERIFY_WRITE, fr, sizeof(struct emuframe))))
93 return SIGBUS; 93 return SIGBUS;
94 94
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 274da90adf0d..4004b659ce50 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -2361,8 +2361,9 @@ static void print_htw_config(void)
2361 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT); 2361 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT);
2362 2362
2363 config = read_c0_pwsize(); 2363 config = read_c0_pwsize();
2364 pr_debug("PWSize (0x%0*lx): GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n", 2364 pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n",
2365 field, config, 2365 field, config,
2366 (config & MIPS_PWSIZE_PS_MASK) >> MIPS_PWSIZE_PS_SHIFT,
2366 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT, 2367 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT,
2367 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT, 2368 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT,
2368 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT, 2369 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT,
@@ -2370,9 +2371,12 @@ static void print_htw_config(void)
2370 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT); 2371 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT);
2371 2372
2372 pwctl = read_c0_pwctl(); 2373 pwctl = read_c0_pwctl();
2373 pr_debug("PWCtl (0x%x): PWEn: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n", 2374 pr_debug("PWCtl (0x%x): PWEn: 0x%x XK: 0x%x XS: 0x%x XU: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n",
2374 pwctl, 2375 pwctl,
2375 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT, 2376 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT,
2377 (pwctl & MIPS_PWCTL_XK_MASK) >> MIPS_PWCTL_XK_SHIFT,
2378 (pwctl & MIPS_PWCTL_XS_MASK) >> MIPS_PWCTL_XS_SHIFT,
2379 (pwctl & MIPS_PWCTL_XU_MASK) >> MIPS_PWCTL_XU_SHIFT,
2376 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT, 2380 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT,
2377 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT, 2381 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT,
2378 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT); 2382 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT);
@@ -2427,15 +2431,25 @@ static void config_htw_params(void)
2427 if (CONFIG_PGTABLE_LEVELS >= 3) 2431 if (CONFIG_PGTABLE_LEVELS >= 3)
2428 pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT; 2432 pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT;
2429 2433
2430 pwsize |= ilog2(sizeof(pte_t)/4) << MIPS_PWSIZE_PTEW_SHIFT; 2434 /* Set pointer size to size of directory pointers */
2435 if (config_enabled(CONFIG_64BIT))
2436 pwsize |= MIPS_PWSIZE_PS_MASK;
2437 /* PTEs may be multiple pointers long (e.g. with XPA) */
2438 pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT)
2439 & MIPS_PWSIZE_PTEW_MASK;
2431 2440
2432 write_c0_pwsize(pwsize); 2441 write_c0_pwsize(pwsize);
2433 2442
2434 /* Make sure everything is set before we enable the HTW */ 2443 /* Make sure everything is set before we enable the HTW */
2435 back_to_back_c0_hazard(); 2444 back_to_back_c0_hazard();
2436 2445
2437 /* Enable HTW and disable the rest of the pwctl fields */ 2446 /*
2447 * Enable HTW (and only for XUSeg on 64-bit), and disable the rest of
2448 * the pwctl fields.
2449 */
2438 config = 1 << MIPS_PWCTL_PWEN_SHIFT; 2450 config = 1 << MIPS_PWCTL_PWEN_SHIFT;
2451 if (config_enabled(CONFIG_64BIT))
2452 config |= MIPS_PWCTL_XU_MASK;
2439 write_c0_pwctl(config); 2453 write_c0_pwctl(config);
2440 pr_info("Hardware Page Table Walker enabled\n"); 2454 pr_info("Hardware Page Table Walker enabled\n");
2441 2455
diff --git a/arch/mips/oprofile/op_impl.h b/arch/mips/oprofile/op_impl.h
index 7c2da27ece04..a4e758a39af4 100644
--- a/arch/mips/oprofile/op_impl.h
+++ b/arch/mips/oprofile/op_impl.h
@@ -24,7 +24,7 @@ struct op_counter_config {
24 unsigned long unit_mask; 24 unsigned long unit_mask;
25}; 25};
26 26
27/* Per-architecture configury and hooks. */ 27/* Per-architecture configure and hooks. */
28struct op_mips_model { 28struct op_mips_model {
29 void (*reg_setup) (struct op_counter_config *); 29 void (*reg_setup) (struct op_counter_config *);
30 void (*cpu_setup) (void *dummy); 30 void (*cpu_setup) (void *dummy);
diff --git a/arch/mips/pci/ops-bridge.c b/arch/mips/pci/ops-bridge.c
index 438319465cb4..57e1463fcd02 100644
--- a/arch/mips/pci/ops-bridge.c
+++ b/arch/mips/pci/ops-bridge.c
@@ -33,9 +33,9 @@ static u32 emulate_ioc3_cfg(int where, int size)
33 * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is 33 * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
34 * not really documented, so right now I can't write code which uses it. 34 * not really documented, so right now I can't write code which uses it.
35 * Therefore we use type 0 accesses for now even though they won't work 35 * Therefore we use type 0 accesses for now even though they won't work
36 * correcly for PCI-to-PCI bridges. 36 * correctly for PCI-to-PCI bridges.
37 * 37 *
38 * The function is complicated by the ultimate brokeness of the IOC3 chip 38 * The function is complicated by the ultimate brokenness of the IOC3 chip
39 * which is used in SGI systems. The IOC3 can only handle 32-bit PCI 39 * which is used in SGI systems. The IOC3 can only handle 32-bit PCI
40 * accesses and does only decode parts of it's address space. 40 * accesses and does only decode parts of it's address space.
41 */ 41 */
diff --git a/arch/mips/pistachio/init.c b/arch/mips/pistachio/init.c
index 956c92eabfab..ab79828230ab 100644
--- a/arch/mips/pistachio/init.c
+++ b/arch/mips/pistachio/init.c
@@ -83,12 +83,16 @@ static void __init plat_setup_iocoherency(void)
83 } 83 }
84} 84}
85 85
86void __init plat_mem_setup(void) 86void __init *plat_get_fdt(void)
87{ 87{
88 if (fw_arg0 != -2) 88 if (fw_arg0 != -2)
89 panic("Device-tree not present"); 89 panic("Device-tree not present");
90 return (void *)fw_arg1;
91}
90 92
91 __dt_setup_arch((void *)fw_arg1); 93void __init plat_mem_setup(void)
94{
95 __dt_setup_arch(plat_get_fdt());
92 96
93 plat_setup_iocoherency(); 97 plat_setup_iocoherency();
94} 98}
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index 88b82fe21ae6..d40edda0ca3b 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -188,6 +188,41 @@ static struct rt2880_pmx_func gpio_grp_mt7628[] = {
188 FUNC("gpio", 0, 11, 1), 188 FUNC("gpio", 0, 11, 1),
189}; 189};
190 190
191static struct rt2880_pmx_func p4led_kn_grp_mt7628[] = {
192 FUNC("jtag", 3, 30, 1),
193 FUNC("util", 2, 30, 1),
194 FUNC("gpio", 1, 30, 1),
195 FUNC("p4led_kn", 0, 30, 1),
196};
197
198static struct rt2880_pmx_func p3led_kn_grp_mt7628[] = {
199 FUNC("jtag", 3, 31, 1),
200 FUNC("util", 2, 31, 1),
201 FUNC("gpio", 1, 31, 1),
202 FUNC("p3led_kn", 0, 31, 1),
203};
204
205static struct rt2880_pmx_func p2led_kn_grp_mt7628[] = {
206 FUNC("jtag", 3, 32, 1),
207 FUNC("util", 2, 32, 1),
208 FUNC("gpio", 1, 32, 1),
209 FUNC("p2led_kn", 0, 32, 1),
210};
211
212static struct rt2880_pmx_func p1led_kn_grp_mt7628[] = {
213 FUNC("jtag", 3, 33, 1),
214 FUNC("util", 2, 33, 1),
215 FUNC("gpio", 1, 33, 1),
216 FUNC("p1led_kn", 0, 33, 1),
217};
218
219static struct rt2880_pmx_func p0led_kn_grp_mt7628[] = {
220 FUNC("jtag", 3, 34, 1),
221 FUNC("rsvd", 2, 34, 1),
222 FUNC("gpio", 1, 34, 1),
223 FUNC("p0led_kn", 0, 34, 1),
224};
225
191static struct rt2880_pmx_func wled_kn_grp_mt7628[] = { 226static struct rt2880_pmx_func wled_kn_grp_mt7628[] = {
192 FUNC("rsvd", 3, 35, 1), 227 FUNC("rsvd", 3, 35, 1),
193 FUNC("rsvd", 2, 35, 1), 228 FUNC("rsvd", 2, 35, 1),
@@ -195,16 +230,61 @@ static struct rt2880_pmx_func wled_kn_grp_mt7628[] = {
195 FUNC("wled_kn", 0, 35, 1), 230 FUNC("wled_kn", 0, 35, 1),
196}; 231};
197 232
233static struct rt2880_pmx_func p4led_an_grp_mt7628[] = {
234 FUNC("jtag", 3, 39, 1),
235 FUNC("util", 2, 39, 1),
236 FUNC("gpio", 1, 39, 1),
237 FUNC("p4led_an", 0, 39, 1),
238};
239
240static struct rt2880_pmx_func p3led_an_grp_mt7628[] = {
241 FUNC("jtag", 3, 40, 1),
242 FUNC("util", 2, 40, 1),
243 FUNC("gpio", 1, 40, 1),
244 FUNC("p3led_an", 0, 40, 1),
245};
246
247static struct rt2880_pmx_func p2led_an_grp_mt7628[] = {
248 FUNC("jtag", 3, 41, 1),
249 FUNC("util", 2, 41, 1),
250 FUNC("gpio", 1, 41, 1),
251 FUNC("p2led_an", 0, 41, 1),
252};
253
254static struct rt2880_pmx_func p1led_an_grp_mt7628[] = {
255 FUNC("jtag", 3, 42, 1),
256 FUNC("util", 2, 42, 1),
257 FUNC("gpio", 1, 42, 1),
258 FUNC("p1led_an", 0, 42, 1),
259};
260
261static struct rt2880_pmx_func p0led_an_grp_mt7628[] = {
262 FUNC("jtag", 3, 43, 1),
263 FUNC("rsvd", 2, 43, 1),
264 FUNC("gpio", 1, 43, 1),
265 FUNC("p0led_an", 0, 43, 1),
266};
267
198static struct rt2880_pmx_func wled_an_grp_mt7628[] = { 268static struct rt2880_pmx_func wled_an_grp_mt7628[] = {
199 FUNC("rsvd", 3, 35, 1), 269 FUNC("rsvd", 3, 44, 1),
200 FUNC("rsvd", 2, 35, 1), 270 FUNC("rsvd", 2, 44, 1),
201 FUNC("gpio", 1, 35, 1), 271 FUNC("gpio", 1, 44, 1),
202 FUNC("wled_an", 0, 35, 1), 272 FUNC("wled_an", 0, 44, 1),
203}; 273};
204 274
205#define MT7628_GPIO_MODE_MASK 0x3 275#define MT7628_GPIO_MODE_MASK 0x3
206 276
277#define MT7628_GPIO_MODE_P4LED_KN 58
278#define MT7628_GPIO_MODE_P3LED_KN 56
279#define MT7628_GPIO_MODE_P2LED_KN 54
280#define MT7628_GPIO_MODE_P1LED_KN 52
281#define MT7628_GPIO_MODE_P0LED_KN 50
207#define MT7628_GPIO_MODE_WLED_KN 48 282#define MT7628_GPIO_MODE_WLED_KN 48
283#define MT7628_GPIO_MODE_P4LED_AN 42
284#define MT7628_GPIO_MODE_P3LED_AN 40
285#define MT7628_GPIO_MODE_P2LED_AN 38
286#define MT7628_GPIO_MODE_P1LED_AN 36
287#define MT7628_GPIO_MODE_P0LED_AN 34
208#define MT7628_GPIO_MODE_WLED_AN 32 288#define MT7628_GPIO_MODE_WLED_AN 32
209#define MT7628_GPIO_MODE_PWM1 30 289#define MT7628_GPIO_MODE_PWM1 30
210#define MT7628_GPIO_MODE_PWM0 28 290#define MT7628_GPIO_MODE_PWM0 28
@@ -223,9 +303,9 @@ static struct rt2880_pmx_func wled_an_grp_mt7628[] = {
223#define MT7628_GPIO_MODE_GPIO 0 303#define MT7628_GPIO_MODE_GPIO 0
224 304
225static struct rt2880_pmx_group mt7628an_pinmux_data[] = { 305static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
226 GRP_G("pmw1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK, 306 GRP_G("pwm1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK,
227 1, MT7628_GPIO_MODE_PWM1), 307 1, MT7628_GPIO_MODE_PWM1),
228 GRP_G("pmw0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK, 308 GRP_G("pwm0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK,
229 1, MT7628_GPIO_MODE_PWM0), 309 1, MT7628_GPIO_MODE_PWM0),
230 GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK, 310 GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK,
231 1, MT7628_GPIO_MODE_UART2), 311 1, MT7628_GPIO_MODE_UART2),
@@ -251,8 +331,28 @@ static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
251 1, MT7628_GPIO_MODE_GPIO), 331 1, MT7628_GPIO_MODE_GPIO),
252 GRP_G("wled_an", wled_an_grp_mt7628, MT7628_GPIO_MODE_MASK, 332 GRP_G("wled_an", wled_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
253 1, MT7628_GPIO_MODE_WLED_AN), 333 1, MT7628_GPIO_MODE_WLED_AN),
334 GRP_G("p0led_an", p0led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
335 1, MT7628_GPIO_MODE_P0LED_AN),
336 GRP_G("p1led_an", p1led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
337 1, MT7628_GPIO_MODE_P1LED_AN),
338 GRP_G("p2led_an", p2led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
339 1, MT7628_GPIO_MODE_P2LED_AN),
340 GRP_G("p3led_an", p3led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
341 1, MT7628_GPIO_MODE_P3LED_AN),
342 GRP_G("p4led_an", p4led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
343 1, MT7628_GPIO_MODE_P4LED_AN),
254 GRP_G("wled_kn", wled_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, 344 GRP_G("wled_kn", wled_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
255 1, MT7628_GPIO_MODE_WLED_KN), 345 1, MT7628_GPIO_MODE_WLED_KN),
346 GRP_G("p0led_kn", p0led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
347 1, MT7628_GPIO_MODE_P0LED_KN),
348 GRP_G("p1led_kn", p1led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
349 1, MT7628_GPIO_MODE_P1LED_KN),
350 GRP_G("p2led_kn", p2led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
351 1, MT7628_GPIO_MODE_P2LED_KN),
352 GRP_G("p3led_kn", p3led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
353 1, MT7628_GPIO_MODE_P3LED_KN),
354 GRP_G("p4led_kn", p4led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
355 1, MT7628_GPIO_MODE_P4LED_KN),
256 { 0 } 356 { 0 }
257}; 357};
258 358
diff --git a/arch/mips/sgi-ip27/ip27-hubio.c b/arch/mips/sgi-ip27/ip27-hubio.c
index 328ceb3c86ec..2abe016a0ffc 100644
--- a/arch/mips/sgi-ip27/ip27-hubio.c
+++ b/arch/mips/sgi-ip27/ip27-hubio.c
@@ -105,7 +105,7 @@ static void hub_setup_prb(nasid_t nasid, int prbnum, int credits)
105 prb.iprb_ff = force_fire_and_forget ? 1 : 0; 105 prb.iprb_ff = force_fire_and_forget ? 1 : 0;
106 106
107 /* 107 /*
108 * Set the appropriate number of PIO cresits for the widget. 108 * Set the appropriate number of PIO credits for the widget.
109 */ 109 */
110 prb.iprb_xtalkctr = credits; 110 prb.iprb_xtalkctr = credits;
111 111
diff --git a/arch/mips/sgi-ip27/ip27-nmi.c b/arch/mips/sgi-ip27/ip27-nmi.c
index a2358b44420c..cfceaea92724 100644
--- a/arch/mips/sgi-ip27/ip27-nmi.c
+++ b/arch/mips/sgi-ip27/ip27-nmi.c
@@ -23,7 +23,7 @@ typedef unsigned long machreg_t;
23static arch_spinlock_t nmi_lock = __ARCH_SPIN_LOCK_UNLOCKED; 23static arch_spinlock_t nmi_lock = __ARCH_SPIN_LOCK_UNLOCKED;
24 24
25/* 25/*
26 * Lets see what else we need to do here. Set up sp, gp? 26 * Let's see what else we need to do here. Set up sp, gp?
27 */ 27 */
28void nmi_dump(void) 28void nmi_dump(void)
29{ 29{
diff --git a/arch/mips/sgi-ip27/ip27-xtalk.c b/arch/mips/sgi-ip27/ip27-xtalk.c
index 20f582a2137a..4fe5678ba74d 100644
--- a/arch/mips/sgi-ip27/ip27-xtalk.c
+++ b/arch/mips/sgi-ip27/ip27-xtalk.c
@@ -67,7 +67,7 @@ static int xbow_probe(nasid_t nasid)
67 return -ENODEV; 67 return -ENODEV;
68 68
69 /* 69 /*
70 * Okay, here's a xbow. Lets arbitrate and find 70 * Okay, here's a xbow. Let's arbitrate and find
71 * out if we should initialize it. Set enabled 71 * out if we should initialize it. Set enabled
72 * hub connected at highest or lowest widget as 72 * hub connected at highest or lowest widget as
73 * master. 73 * master.
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index a046b302623e..160b88000b4b 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -263,7 +263,7 @@ spurious_8259A_irq:
263 static int spurious_irq_mask; 263 static int spurious_irq_mask;
264 /* 264 /*
265 * At this point we can be sure the IRQ is spurious, 265 * At this point we can be sure the IRQ is spurious,
266 * lets ACK and report it. [once per IRQ] 266 * let's ACK and report it. [once per IRQ]
267 */ 267 */
268 if (!(spurious_irq_mask & irqmask)) { 268 if (!(spurious_irq_mask & irqmask)) {
269 printk(KERN_DEBUG 269 printk(KERN_DEBUG
diff --git a/arch/mips/vdso/Makefile b/arch/mips/vdso/Makefile
index b369509e9753..3b4538ec0102 100644
--- a/arch/mips/vdso/Makefile
+++ b/arch/mips/vdso/Makefile
@@ -5,10 +5,12 @@ obj-vdso-y := elf.o gettimeofday.o sigreturn.o
5ccflags-vdso := \ 5ccflags-vdso := \
6 $(filter -I%,$(KBUILD_CFLAGS)) \ 6 $(filter -I%,$(KBUILD_CFLAGS)) \
7 $(filter -E%,$(KBUILD_CFLAGS)) \ 7 $(filter -E%,$(KBUILD_CFLAGS)) \
8 $(filter -mmicromips,$(KBUILD_CFLAGS)) \
8 $(filter -march=%,$(KBUILD_CFLAGS)) 9 $(filter -march=%,$(KBUILD_CFLAGS))
9cflags-vdso := $(ccflags-vdso) \ 10cflags-vdso := $(ccflags-vdso) \
10 $(filter -W%,$(filter-out -Wa$(comma)%,$(KBUILD_CFLAGS))) \ 11 $(filter -W%,$(filter-out -Wa$(comma)%,$(KBUILD_CFLAGS))) \
11 -O2 -g -fPIC -fno-common -fno-builtin -G 0 -DDISABLE_BRANCH_PROFILING \ 12 -O2 -g -fPIC -fno-strict-aliasing -fno-common -fno-builtin -G 0 \
13 -DDISABLE_BRANCH_PROFILING \
12 $(call cc-option, -fno-stack-protector) 14 $(call cc-option, -fno-stack-protector)
13aflags-vdso := $(ccflags-vdso) \ 15aflags-vdso := $(ccflags-vdso) \
14 $(filter -I%,$(KBUILD_CFLAGS)) \ 16 $(filter -I%,$(KBUILD_CFLAGS)) \
diff --git a/arch/mips/vr41xx/common/cmu.c b/arch/mips/vr41xx/common/cmu.c
index 05302bfdd114..89bac9885695 100644
--- a/arch/mips/vr41xx/common/cmu.c
+++ b/arch/mips/vr41xx/common/cmu.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright (C) 2001-2002 MontaVista Software Inc. 4 * Copyright (C) 2001-2002 MontaVista Software Inc.
5 * Author: Yoichi Yuasa <source@mvista.com> 5 * Author: Yoichi Yuasa <source@mvista.com>
6 * Copuright (C) 2003-2005 Yoichi Yuasa <yuasa@linux-mips.org> 6 * Copyright (C) 2003-2005 Yoichi Yuasa <yuasa@linux-mips.org>
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index c089f49b63fb..3b5e10aa48ab 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -968,7 +968,7 @@ static void __init __gic_init(unsigned long gic_base_addr,
968 unsigned int cpu_vec, unsigned int irqbase, 968 unsigned int cpu_vec, unsigned int irqbase,
969 struct device_node *node) 969 struct device_node *node)
970{ 970{
971 unsigned int gicconfig; 971 unsigned int gicconfig, cpu;
972 unsigned int v[2]; 972 unsigned int v[2];
973 973
974 __gic_base_addr = gic_base_addr; 974 __gic_base_addr = gic_base_addr;
@@ -985,6 +985,14 @@ static void __init __gic_init(unsigned long gic_base_addr,
985 gic_vpes = gic_vpes + 1; 985 gic_vpes = gic_vpes + 1;
986 986
987 if (cpu_has_veic) { 987 if (cpu_has_veic) {
988 /* Set EIC mode for all VPEs */
989 for_each_present_cpu(cpu) {
990 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR),
991 mips_cm_vp_id(cpu));
992 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_CTL),
993 GIC_VPE_CTL_EIC_MODE_MSK);
994 }
995
988 /* Always use vector 1 in EIC mode */ 996 /* Always use vector 1 in EIC mode */
989 gic_cpu_pin = 0; 997 gic_cpu_pin = 0;
990 timer_cpu_pin = gic_cpu_pin; 998 timer_cpu_pin = gic_cpu_pin;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-13 22:16:21 -0400