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authorYuantian Tang <andy.tang@nxp.com>2018-02-08 02:54:35 -0500
committerShawn Guo <shawnguo@kernel.org>2018-02-24 02:10:02 -0500
commit3fd366d8cbb372386c14b7dbf86b05885e04b482 (patch)
tree90b584a1618cf7a28650af5a439e6c0ed9e29ffc
parent9b4eefcb70ca79d7dbd3a2a2d29ef9682762eeeb (diff)
arm64: dts: ls1043a: add cpu idle support
Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi21
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 4d15e111cf12..beb3c3500ed6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -81,6 +81,7 @@
81 clocks = <&clockgen 1 0>; 81 clocks = <&clockgen 1 0>;
82 next-level-cache = <&l2>; 82 next-level-cache = <&l2>;
83 #cooling-cells = <2>; 83 #cooling-cells = <2>;
84 cpu-idle-states = <&CPU_PH20>;
84 }; 85 };
85 86
86 cpu1: cpu@1 { 87 cpu1: cpu@1 {
@@ -89,6 +90,7 @@
89 reg = <0x1>; 90 reg = <0x1>;
90 clocks = <&clockgen 1 0>; 91 clocks = <&clockgen 1 0>;
91 next-level-cache = <&l2>; 92 next-level-cache = <&l2>;
93 cpu-idle-states = <&CPU_PH20>;
92 }; 94 };
93 95
94 cpu2: cpu@2 { 96 cpu2: cpu@2 {
@@ -97,6 +99,7 @@
97 reg = <0x2>; 99 reg = <0x2>;
98 clocks = <&clockgen 1 0>; 100 clocks = <&clockgen 1 0>;
99 next-level-cache = <&l2>; 101 next-level-cache = <&l2>;
102 cpu-idle-states = <&CPU_PH20>;
100 }; 103 };
101 104
102 cpu3: cpu@3 { 105 cpu3: cpu@3 {
@@ -105,6 +108,7 @@
105 reg = <0x3>; 108 reg = <0x3>;
106 clocks = <&clockgen 1 0>; 109 clocks = <&clockgen 1 0>;
107 next-level-cache = <&l2>; 110 next-level-cache = <&l2>;
111 cpu-idle-states = <&CPU_PH20>;
108 }; 112 };
109 113
110 l2: l2-cache { 114 l2: l2-cache {
@@ -112,6 +116,23 @@
112 }; 116 };
113 }; 117 };
114 118
119 idle-states {
120 /*
121 * PSCI node is not added default, U-boot will add missing
122 * parts if it determines to use PSCI.
123 */
124 entry-method = "arm,psci";
125
126 CPU_PH20: cpu-ph20 {
127 compatible = "arm,idle-state";
128 idle-state-name = "PH20";
129 arm,psci-suspend-param = <0x00010000>;
130 entry-latency-us = <1000>;
131 exit-latency-us = <1000>;
132 min-residency-us = <3000>;
133 };
134 };
135
115 memory@80000000 { 136 memory@80000000 {
116 device_type = "memory"; 137 device_type = "memory";
117 reg = <0x0 0x80000000 0 0x80000000>; 138 reg = <0x0 0x80000000 0 0x80000000>;