powerpc/8xx: Enable 512k hugepage support with HW assistance

For using 512k pages with hardware assistance, the PTEs have to be spread
every 128 bytes in the L2 table.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

3 files changed, 15 insertions, 2 deletions

diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
index dfb8bf236586..62a0ca02ca7d 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -74,7 +74,9 @@ static inline pte_t *hugepte_offset(hugepd_t hpd, unsigned long addr,
         unsigned long idx = 0;
 
         pte_t *dir = hugepd_page(hpd);
-#ifndef CONFIG_PPC_FSL_BOOK3E
+#ifdef CONFIG_PPC_8xx
+        idx = (addr & ((1UL << pdshift) - 1)) >> PAGE_SHIFT;
+#elif !defined(CONFIG_PPC_FSL_BOOK3E)
         idx = (addr & ((1UL << pdshift) - 1)) >> hugepd_shift(hpd);
 #endif
 
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index bc97874d7c74..5b236621d302 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -65,6 +65,9 @@ static int __hugepte_alloc(struct mm_struct *mm, hugepd_t *hpdp,
         if (pshift >= pdshift) {
                 cachep = PGT_CACHE(PTE_T_ORDER);
                 num_hugepd = 1 << (pshift - pdshift);
+        } else if (IS_ENABLED(CONFIG_PPC_8xx)) {
+                cachep = PGT_CACHE(PTE_INDEX_SIZE);
+                num_hugepd = 1;
         } else {
                 cachep = PGT_CACHE(pdshift - pshift);
                 num_hugepd = 1;
@@ -331,6 +334,9 @@ static void free_hugepd_range(struct mmu_gather *tlb, hugepd_t *hpdp, int pdshif
 
         if (shift >= pdshift)
                 hugepd_free(tlb, hugepte);
+        else if (IS_ENABLED(CONFIG_PPC_8xx))
+                pgtable_free_tlb(tlb, hugepte,
+                                 get_hugepd_cache_index(PTE_INDEX_SIZE));
         else
                 pgtable_free_tlb(tlb, hugepte,
                                  get_hugepd_cache_index(pdshift - shift));
@@ -700,7 +706,9 @@ static int __init hugetlbpage_init(void)
                  * if we have pdshift and shift value same, we don't
                  * use pgt cache for hugepd.
                  */
-                if (pdshift > shift)
+                if (pdshift > shift && IS_ENABLED(CONFIG_PPC_8xx))
+                        pgtable_cache_add(PTE_INDEX_SIZE);
+                else if (pdshift > shift)
                         pgtable_cache_add(pdshift - shift);
 #if defined(CONFIG_PPC_FSL_BOOK3E) || defined(CONFIG_PPC_8xx)
                 else
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 8ad7aab150b7..ae5d568e267f 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -97,6 +97,9 @@ struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
                 .shift  = 14,
         },
 #endif
+        [MMU_PAGE_512K] = {
+                .shift  = 19,
+        },
         [MMU_PAGE_8M] = {
                 .shift  = 23,
         },